Ferroelectric gating of graphene 4

Chapter 4
Ferroelectric gated graphene field
effect transistors (GFeFETs) as
non-volatile memory devices
In this chapter, we will describe experimental studies of ferroelectrically gated charge
transport in mechanically exfoliated graphene and its potential applications as non-
volatile memory devices. A pronounced hysteresis of the resistance as a function
of gate voltage was observed. This hysteretic resistance change can be reversibly
switched by controlling the polarization of the ferroelectric thin film. Based on this,
a prototype of a non-volatile memory device was developed. Furthermore, we demon-
strate that such non-linear, hysteretic ferroelectric gating can be controlled by the
independent background doping of graphene.
The results discussed in this chapter have been published in Physics Review Let-
ters [84] and Applied Physics Letters [66].
38
39
4.1 Introduction and background
Nonvolatile memory is a general term for all forms of solid state memory that do
not need to have their memory contents periodically refreshed. The first non-volatile
semiconductor memory was a 1 kB UV-erasable programmable read only memory
(PROM), introduced in the 1970s [85]. Later on EEPROM, electrically erasable
PROM, was presented which, as its name suggests, could be erased by an electrical
pulse [86]. Hence, it is also called flash memory. Flash memory is one of the most
powerful and cost-effective solid-state storage technology widely used in various elec-
tronics devices and consumer applications. Flash memory works by storing charge in
the gate of a transistor. The stored charge changes the threshold voltage (V
T
) of the
transistor, which can be read out as the stored state. These devices use hot-electron
injection for programming and tunneling injection for erasing. Therefore, erasing is
generally slower and is accompanied by several bytes at once, typically a sector.

There are two major types of flash memory, NAND and NOR [87]. NOR flash
memory has a larger cell size, high read speed, slow write speed, slow erase speed,
and random data access ability. NAND flash chips are serial access devices with high
density, medium read speed, high write speed, high erase speed and an indirect access.
In general, the fast “read” times of NOR allow for its usage in code storage, primarily
in cell phones and other hand-held devices. On the other hand, the fast “write/erase”
times and the significantly lower power requirements of NAND allows for its usage in
general storage and transfer of data, such as memory cards, solid state drives, USB
flash drives, digital cameras, etc.
However, as part of the semiconductor industry, flash memory also faces the fun-
damental physical barrier of shrinking cell sizes. In addition, flash memory also suffers
40
Control gate
D
Floating gate
N
N
P
Dielectrics
Figure 4.1: (a) Structure of a flash memory device.
from its relatively long programming time (> 10 µs), and limited cycle endurance.
Furthermore, the high programming voltages (> 10 V) complicate its scaling down
to nanometer cell sizes [88].
Many of the shortcomings of NAND flash can be addressed by ferroelectric non-
volatile RAM (FeRAM). FeRAM utilizes ferroelectric capacitors for data storage such
that “1” and “0” are represented by two opposite polarization states, which can
be retained without electrical power. Unlike NAND flash, FeRAM only needs a
marginally higher writing voltage than the reading voltage. Moreover, both read
and write can be done in a bit-by-bit fashion in FeRAM. These two features allow
FeRAM to use less power than NAND flash for devices with more balanced read

and write. However, two obstacles prevent FeRAM from being the ideal non-volatile
memory. The main disadvantage of FeRAM is that the reading process of “1” state
is destructive, and a subsequent writing process is required to return the state to “1”.
Furthermore, while 130 nm FeRAM is commercially available, it remains unclear how
much further it can b e scaled down [89]. Consequently, novel types of non-volatile
memory devices are in high demand.
41
Among the many candidates, graphene is intriguing because of its ultrahigh carrier
mobility and pronounced field effect. However, despite graphene intrinsically having
a high resistance state at the Dirac point and a low resistance state when heavily
doped, reports on graphene in the context of non-volatile memory information stor-
age are rarely seen. This is due to the difficulty in maintaining the resistance states
in graphene without an electric field. Although a chemical modification approach
to achieve non-volatile switching with high on-off ratios in graphene has been pro-
posed by Lemme et al. [90], this method alters the unique crystalline structure of
graphene and decreases carrier mobility dramatically, making the modified graphene
no different than other common semiconductor materials.
In the following, we propose a new type of non-volatile memory device in a
graphene field-effect-transistor structure using ferroelectric gating. In section 4.2, we
present ferroelectric polymer (P(VDF-TrFE)) gated graphene-field effect transistor
structure (GFeFET), which is further divided to three parts, asymmetric bit writing,
symmetric bit writing and understanding of ferroelectric gating. The summary for
this chapter is in section 4.3.
4.2 P(VDF-TrFE) gated GFeFET non-volatile mem-
ory
This section is divided into three parts. In section 4.2.1, we demonstrate a prototype
of non-volatile memory device using a ferroelectric polymer (P(VDF-TrFE)) gated
graphene-field effect transistor structure (GFeFET). By solely using ferroelectric gat-
ing, the high and low resistance states can only be maintained via the asymmetric
42

polarization of P(VDF-TrFE) thin film. Thus, this strategy is referred to asymmet-
ric bit writing. In section 4.2.2, we show that simple symmetric P(VDF-TrFE) gate
sweeping for two distinct resistance states in graphene can be achieved through the
introduction of independent background doping (n
BG
). We therefore call it symmet-
ric bit writing. In section 4.2.3, we discuss the impact of electron-hole puddles in
ferroelectric gated graphene devices.
4.2.1 Asymmetric bit writing using ferroelectric gating
The working principle of graphene-P(VDF-TrFE) non-volatile memory for asymmet-
ric bit writing is shown in Fig. 4.2a. The binary bits “1” and “0” are represented
by the high resistance state near the charge neutral point and the low resistance
state when graphene is heavily doped respectively. The reading of binary information
is realized by measuring the device resistance using an excitation current of 1 nA.
The switching of binary information between “1” (“0”) and “0” (“1”) is achieved
by tuning the polarization of the ferroelectric to be either zero (E
C
) or at remnant
polarization (P
r
). Correspondingly, the resistance in graphene will be either at the
higher resistance value, R
1
, or at the low resistance value, R
0
, depending on the exact
charge density introduced from the ferroelectric thin film. Compared to the chemical
modification method, the graphene-ferroelectric memory has two key advantages [90].
First, this hybrid memory structure can in principle retain the high charge carrier
mobility of graphene, which is crucial for ultrafast device applications. In fact, the

reading speed of an ideal graphene-ferroelectric memory can be as fast as several tens
femtoseconds for a device operating at 1 V with a channel length of 1 µm and charge
carrier mobility of 200,000 cm
2
V
−1
s
−1
. The second advantage of this memory device
43
is the significantly faster writing speed. It is only limited by the switching time of
the ferroelectric thin film and can reach several ten nanoseconds. While the focus
here is mainly on graphene, such a graphene-ferroelectric hybrid device is also likely
to solve the challenges of an ordinary ferroelectric random access memory (FeRAM).
Among these p erhaps the most important are the destructive reading process of “1”
state and the scalability problem [91].
Vmax
Vmax
-Pr
-Pr
Vmax
-Pr
D
E
D
E
D
E
D
E

Vmax
Pmin
Pmin
Pmin
“0” to “0”
“1” to “1”
“1” to “0”
“0” to “1”
a
“1” to “1”
“0” to “0”
“0” to “1”
“1” to “0”
b
(i)
(ii)
(iii)
(iv)
(i) (ii)
(iii)
(iv)
Figure 4.2: Working principles and device operations of asymmetric bit writing. (a)
Working principle of asymmetric bit writing. (i) Writing from “0” to “0”; (ii) Writing
from “1” to “1”; (iii) Writing from “0” to “1”; (iv) Writing from “1” to “0”. (b):
(i) Writing “0” into graphene-ferroelectric memory by a full loop sweep of V
TG
(±85
V). The memory bit is in “0” state before writing. (ii) Writing “1” into graphene-
ferroelectric memory by an asymmetrical loop sweep of V
TG

(85 V to -34 V). The
memory bit is in “1” state before writing. (iii) Writing “0” into graphene-ferroelectric
memory by a full loop sweep of V
TG
. The memory bit is in “1” state before writing.
(iv) Writing “1” into graphene-ferroelectric memory by an asymmetrical loop sweep
of V
TG
. The memory bit is in “0” state before writing.
The sample geometry of our graphene-ferroelectric memory devices is shown in
Fig. 4.3a. Graphene flakes were sitting on top of Si/SiO
2
substrate. Multiple Cr/Au
(5/30 nm) contacts were patterned in the edge of graphene flakes by electron-beam
lithography. A ferroelectric thin film of poly(vinylidene fluoride-trifluoroethylene)
44
Figure 4.3: (a) Sample geometry of a finished graphene-ferroelectric memory device.
(b) Optical image of a graphene samples showing the Hall bar geometry of the bottom
electrodes. (c) R vs V
BG
of the graphene sample before P(VDF-TrFE) coating,
measured in two-terminal configuration. (d) AFM image of another graphene sample
after P(VDF-TrFE) spin coating. The contrast comes from the slightly different
crystallization of P(VDF-TrFE) on SiO
2
, graphene, and Au electrodes, respectively.
(P(VDF-TrFE)) was then spin-coated (0.5 µm) on top of the GFET structures. From
atomic force microscopy (AFM), we conclude that P(VDF-TrFE) forms a continu-
ous thin film on graphene devices (Fig. 4.3d). For all devices, resistance (R) vs the
bottom gate voltage (V

BG
) has been recorded for reference before P(VDF-TrFE) coat-
ing. After thermally evaporating the top gate electrodes, samples were electrically
characterized at room temperature in vacuum in a four-contact configuration using
a lock-in amplifier with an AC excitation current of 10 nA. The number of graphene
layers is confirmed by Raman spectroscopy. In total, we have successfully studied 15
samples. For the representative sample used here, the charge carrier mobility before
P(VDF-TrFE) is ∼ 1500 cm
2
V
−1
s
−1
, estimated from the linear slope of the R vs V
BG
45
Figure 4.4: Electric hysteresis loop; R as a function of V
TG
for the graphene-
ferroelectric sample. The resistance peak at 44 V (-32 V) corresponds to the flipping
of electric dipoles in P(VDF-TrFE) from upward (downward) to downward (upward).
From the linear part of this curve at high voltage, the charge carrier mobility is esti-
mated to be 700 cm
2
V
−1
s
−1
, taking κ
PVDF

= 10 [93].
curve [92], as shown in Fig. 4.3c.
We now present the main experimental observations. As shown in Fig. 4.4, the
most important feature for all measured samples is a pronounced hysteresis in resis-
tance measurements when the top gate voltage (V
TG
) is swept in a closed loop: 0 V
to 85 V, 85 V to -85 V, and finally from -85 V back to 0 V. Similar to the magne-
toresistance measurements of a GMR/TMR device, we observe a hysteretic switching
between the maximum resistance (R
max
) and the minimum resistance (R
min
), but now
as a function of the applied electric field, E, instead of a magnetic field, B. For the
sample in Fig. 4.4, the resistance change between R
max
and R
min
is larger than 350%.
This hysteretic behavior and the double peak structure in R vs V
TG
curves are
closely related to the polarization of P(VDF-TrFE) thin film. As illustrated in the
46
inset of Fig. 4.5, the continuity of electric displacement field, D, at the ferroelec-
tric/graphene interface requires D = ε
0
κ
ferro

E
ferro
+ P(V
TG
) = −n(V
TG
)e, where E
ferro
and n(V
TG
) are the electric field in ferroelectric and the charge carrier concentration
in graphene respectively [94]. Here, the dielectric response of the ferroelectric sep-
arates into a linear part (ε
0
κ
ferro
E
ferro
) and a hysteretic part (P(V
TG
)). While the
linear dielectric part induces electrical doping in graphene with an opposite sign to
V
TG
, P(V
TG
) can induce electrical doping with either sign. These two components
compete with each other such that graphene can remain p-doped (n-doped) even
with a positive (negative) V
TG

until either the doping contribution from the linear
part exceeds P(V
TG
) or the polarization direction of the ferroelectric is switched. It
is this behavior which leads to the hysteretic doping of graphene as a function of
V
TG
. Considering that the conductance of graphene is σ = n(V
TG
)eµ, the observed
resistance hysteresis loop is now directly related to P(V
TG
) by
D = ε
0
κ
ferro
E
ferro
+ P(V
TG
) = −n(V
TG
)e = σ /µ. (4.2.1)
Using this equation, we convert the R vs V
TG
curve in Fig. 4.5 into D vs E
characteristics, which is further compared with the direct polarization measurement
of P(VDF-TrFE) thin film alone, D’. As show in Fig. 4.5, D and D’ have very
similar coercive fields (E

C
) of ∼ 50 MV/m, consistent with the typical E
C
reported
in literature [95]. This agreement strongly suggests that the hysteresis observed in
the transport measurements is indeed caused by the hysteretic polarization of the
ferroelectric gate dielectric. From Fig. 4.5, we can also see that the left and right
resistance peaks in Fig. 4.4 correspond to the flipping of electric dipoles from upward
to downward and from downward to upward, respectively, while R
min
in Fig. 4.4 is
related to the maximum polarization point in Fig. 4.5. Another important parameter
47
Figure 4.5: D vs V
T G
characteristics deduced from the R vs V
T G
curve in Fig. 4.9. The
black curve represents the experimental measured D’ of P(VDF-TrFE) thin film with
similar thickness. The kinks near E
C
in D are caused by the assumption of a constant
charge carrier mobility, which does not hold near the charge neutral regime. Inset
(a): the electric displacement continuity equation at ferroelectric/graphene interface.
Inset (b): a polarized P(VDF-TrFE) molecule. Cyan, grey and white atoms represent
fluorine, carbon and hydrogen respectively.
in Fig. 4.4 is the zero-field resistance R
P
r
, corresponding to a remnant polarization

P
r
of P(VDF-TrFE) in Fig. 4.5.
For device operation, we utilize the maximum resistance peak (R
1
≃ R
max
) as bit
“1”, while bit “0” is represented by R
P
r
. As shown in Fig. 4.2b, a major hysteresis
loop, corresponding to a full symmetrical V
TG
sweep (±V
max
), can set the memory to
“0”, independent of the existing state. In Fig. 4.2b(i), “0” has been rewritten into
“0”, while in Fig 4.2b(iv), the binary information has been reset from “1” to “0”.
In contrast, writing “1” into graphene-ferroelectric memory requires a minor hys-
teresis loop with an asymmetrical V
TG
sweep to minimize the polarization in P(VDF-
TrFE) thin film when V
TG
is back to zero. As shown in Fig Fig. 4.2b(ii) and Fig.
4.2b(iii), a minor hysteresis loop with V
max
= 85 V and −V
′

max
= −34 V can set the
48
resistance state of graphene channel to near R
max
, independent on the initial state of
“1” (Fig 4.2b(ii)) or “0” (Fig. 4.2b(iii)).
Thus, using major and minor hysteresis loops, we can realize non-volatile switching
in graphene-ferroelectric memory. Note that the switching voltage can be reduced
by one order of magnitude by simply scaling the thickness of P(VDF-TrFE) to the
range of 100 nm. The difference between the two resistance states (∆R/R=(R
1
-
R
P
r
)/R
P
r
) is determined by the difference between the minimum polarization (P
min
)
and the remnant polarization (P
r
) in P(VDF-TrFE). For the sample discussed here,
the resistance change ∆R/R is ≈ 200%.
Next, we discuss how to improve the performance of such GFeFET devices. First,
∆R/R can be much increased by removing contaminant residues on graphene surface.
For an ideal ferroelectric/graphene interface, ∆R/R can be as large as ∼ (
1

P
min
µ
′
−
1
P
r
µ
)/
1
P
r
µ
, where µ
′
is the mobility at P
min
. Another important approach is to increase
the remnant polarization by applying larger electric fields. Thus, a better approach
would be the preparation of graphene sheets directly on ferroelectric substrates with
much higher remnant polarization. Last but least strategy would be to open a band
gap in graphene, either by using bilayer graphene or graphene nanoribbons.
4.2.2 Symmetric bit writing using ferroelectric gating and
back ground doping
Although two distinct resistance states are created by polarizing and depolarizing
the P(VDF-TrFE) thin film alternately, the depolarized state (“1”) is not in ther-
modynamic equilibrium and less stable than the polarized state (“0”) (Fig. 4.6). To
solve this problem, we introduce an independent background doping (n
BG

) provided
49
Figure 4.6: Free energy as a function of polarization for a ferroelectric material.
by a normal dielectric gating. The key idea is use this n
BG
to control the ferro elec-
tric gating by shifting the hysteretic ferroelectric doping in graphene. Utilizing this
electrostatic effect, we demonstrate symmetric bit writing in GFeFET with resistance
change over 500 % and reproducible non-volatile switching over 10
5
cycles.
The working principle of GFeFET non-volatile memory for symmetric bit writing
is shown in Fig. 4.7. By applying an independent doping n
BG
, the ferroelectric gating
can be effectively controlled by unidirectionally shifting the hysteresis ferroelectric
doping in graphene, yielding an asymmetric hysteresis doping loop. Utilizing this
effect, the switching from “1” (“0”) to “0” (“1”) can be realized by simply applying an
external positive (negative) voltage to the top electrode. After this positive (negative)
pulse, the polarization in the ferroelectric will remain at P
r
(−P
r
) without the need of
an external electric field. Correspondingly, the resistance in graphene with be either
at the higher resistance value, R
1
, or at the low resistance value, R
0
. Thus, the bit

50
n
E
n1
E
-Vmax
E E
Vmax
n
n
n
n0
n1
n0
nBG
Figure 4.7: Working principle of symmetric bit writing from ”1” (”0”) to ”0” (”1”).
Hysteresis loop shown here is representing the charge density n in graphene as a
function of external gate voltage. The corresponding n
BG
is shown on the right side.
writing in GFeFETs can be much simplified and faster bit switching speed can be
achieved by releasing the full advantage of ferroelectric.
The sample geometry and detailed sample fabrication procedures have been dis-
cussed in Chapter 4.2.1. For the samples used in this study, the ferroelectric thin film
of poly(vinylidene fluoride-trifluoroethylene 72:28) (P(VDF-TrFE)) is approximately
0.5 µm thick. The GFeFETs were electrically characterized at room temperature in
vacuum in a four-contact configuration using lock-in amplifiers with an AC excitation
current of 10 −100 nA.
Before polarizing the ferroelectric, we first measured the Hall mobility and the re-
sistance vs SiO

2
gate voltage characteristics (R vs V
BG
) to determine the sample qual-
ity. Most of our samples retain their high charge carrier mobility after P(VDF-TrFE)
spin-coating and annealing, as shown in Fig. 4.8. Quantitatively, the ambipolar R vs
51
Figure 4.8: R vs V
BG
of one sample after P(VDF-TrFE) coating. Red open square
and black solid line are the experimental and fitting results (µ = 4,600 cm
2
V
−1
s
−1
[94]) respectively. Inset: Atomic force microscopy of the sample after P(VDF-TrFE).
Color scale: 0 to 164 nm.
V
BG
characteristics can be fitted by,
R =
L
W eµ
Hall
√
n
2
res
+ n

2
, (4.2.2)
using the Hall mobility µ
Hall
[96]. For the sample shown here, the fitting yields a
residual carrier concentration n
res
= 2.77 ×10
11
cm
−2
.
In the following, we present the main results after introducing an independent n
BG
using the the SiO
2
/Si back gate to GFeFETs. This provides a well defined, constant
reference for determining the charge carrier concentration induced by ferroelectric
doping. To study the effect of n
BG
on the ferroelectric gating of GFeFETs, it is also
important to limit the polarization magnitude in the ferroelectric thin film, since
ferroelectric gating is nearly 10 times stronger than the SiO
2
gating [66]. Thus, we
first introduced very small |P
r
| in P(VDF-TrFE) by limiting the maximum top gate
voltage (V
TG−max

) to ±5 V. Such low V
TG
only slightly polarizes the ferroelectric,
allowing n
BG
to match or even exceed the |P
r
| induced doping in graphene.
52
Figure 4.9: (a) R vs V
TG
and V
BG
of the GFeFET with very small P
r
and -P
r
. (b)
Extracted single traces of R vs V
TG
with different V
BG
. The blue dotted lines are
simulated results. (c) Origin of the resistance peaks and the change in △R/R.
53
In Figure 4.9a, we show the resistance of the representative GFeFET as a function
of both V
TG
and V
BG

. With V
BG
≈ 6 V, the R vs V
TG
curve shows two symmetrical
resistance peaks and nearly negligible △R/R (Fig. 4.9b(iii)). By gradually tuning
n
BG
with V
BG
, the two resistance peaks become more asymmetrical and shift leftward
(rightward) for n
BG
< 0 (n
BG
> 0). The shift in peak positions leads to an increase in
△R/R, which has a maximum at V
BG
≈ −6 V (Fig. 4.9b(ii)) and V
BG
≈ 18 V (Fig.
4.9b(iv)), respectively. Crossing these two points, △R/R decreases as |n
BG
| keeps on
increasing. At large enough n
BG
, the double peak structure eventually disappears in
the R vs V
TG
hysteresis (Fig. 4.9b(i) and Fig. 4.9b(v)).

The evolution of the resistance peaks and the change in △R/R can both be ex-
plained by two independent but competing doping processes in graphene by polarized
ferroelectric dipoles and V
BG
, respectively. For such a dual-gated system, the inter-
facial electric displacement continuity equation is expressed by
−βP(V
TG
) + n
∗
= n(V
TG
, V
BG
)e, (4.2.3)
where βP(V
TG
) represents the hysteretic dipole doping by the ferroelectric gating [94],
and n
∗
= n
env
+n
BG
is the reference doping induced by the dielectric environment and
V
BG
respectively. For n
∗
≈ 0, the doping in graphene is dominated by the ferroelectric

gating by n(V
TG
, n
∗
≈ 0) = −βP(V
TG
)/e. Using Eq. 4.2.2, it is now straightforward
to see that n(V
TG
, n
∗
≈ 0) will produce a R vs V
TG
hysteresis with two symmetrical
resistance peaks, centering on the two coercive-field points where P(V
TG
) crossing
zero. Experimentally, this is the R vs V
TG
curve in Fig. 4.9b(iii) with V
BG
= 6 V, in
which two resistance peaks are centered at V
TG
= ±2.2 V respectively. By converting
each R in Fig. 4.9b(iii) into doping using Eq. 4.2.3, we directly determined the doping
curve n(V
TG
, n
∗

≈ 0). The result is shown in Fig. 4.9c (red curve). As exp ected,
54
this doping curve is hysteretic and characterized by two zero-field doping levels with
equal magnitude, i.e. |n
1
| = |n
0
| = βP
r
/e.
After acquiring n(V
TG
, n
∗
≈ 0), we can deduce individual R(V
TG
, n
∗
) curves for
non-zero n
∗
by substituting n(V
TG
, V
BG
) = −βP(V
TG
)/e+n
env
+αV

BG
into Eq. 4.2.2.
Here α = 7.2 × 10
10
cm
−2
V
−1
is the doping coefficient of 300 nm SiO
2
, and n
env
is a fitting parameter [97]. By tuning n
env
and matching the resistance peaks of the
simulation to the experimental, we simulated each experimental R(V
TG
, V
BG
) curve in
Fig. 4.9b. As shown by blue dotted lines, the simulation reproduces the evolution of
the experimental results very well. Two resulting doping hysteresis for the resistance
curves in Fig. 4.9b(i) and Fig. 4.9b(ii) are further compared with n(V
TG
, n
∗
≈ 0) in
Fig. 4.9c. From the comparison, we can see that △R/R approaches the maxima as
one zero-filed doping level sits near the Dirac point when |n
∗

| ≈ βP
r
/e (blue hysteresis
loop). Further increase in n
BG
moves both n
1
and n
0
away from the Dirac point, and
△R/R decreases (black hysteresis loop).
Thus, we have shown that using a background doping introduced by normal dielec-
tric gating as a reference, the hysteretic behavior of R vs ferroelectric gating in GFe-
FETs can be quantitatively determined by solving the electric displacement continu-
ity equation. For memory applications, △R/R is of great importance. Following the
above discussions, the two zero-field resistance states are R
1
=
L
W eµ
√
n
2
res
+(βP
r
/e−n
∗
)
2

and R
0
=
L
W eµ
√
n
2
res
+(βP
r
/e+n
∗
)
2
respectively. Thus, the best strategy to utilize the field-
dependent resistance is fully p olarizing the ferroelectric and introducing a matching
n
BG
, as demonstrated in Fig. 4.10a. With V
TG−max
= 5 V, two maxima of ∼250%
are present in the △R/R vs V
BG
curve, which can be also simulated very well by Eq.
4.2.2 and 4.2.3 with βP
r
/e = 4.2 × 10
11
cm

−2
. By increasing V
TG−max
to 30 V, the
55
Figure 4.10: (a) Summary of △R/R as a function of V
BG
with different V
TG−max
.
Two maxima are observable with V
TG−max
= 5 V (black open circles). The red solid
line shows the simulation with βP
r
= 4.2 × 10
11
cm
2
. For V
TG−max
= 30 V, the
maximum △R/R is increased to 500% (V
BG
= 32 V), while another maximum is out
of the V
BG
measurement range. (b) R (V
TG
, V

BG
) of the GFeFET with higher βP
r
(∼ 2 ×10
12
cm
−2
). Double peak structures dominate over the whole V
BG
range.
maximum △R/R is increased to 500%. The fast increase in P
r
not only increases the
maximum △R/R, but also increases the separation between the two △R/R maxima,
resulting in one maximum out of the V
BG
measurement range. For this V
TG−max
, R
vs V
TG
shows a dominant double peak structure over the full V
BG
range (Fig. 4.10b).
However, we can still see the tendency of a transition from double peak structure to
single peak structure as V
BG
exceeding 40 V.
Such n
BG

shifted hysteretic doping in graphene is a ferroelectric analogy to the
ferromagnetic exchange bias [98]. Utilizing this electrostatic effect, the bit writing in
GFeFETs can be much simplified by switching the ferroelectric polarization between
P
r
and -P
r
, using symmetrical voltage sweeps. With a negative n
BG
, to write the
high resistance “1”, a negative writing voltage (-V
writing
) is applied to the ferroelectric
thin film, setting the dipole polarization to -P
r
independent of the initial states in the
unit cell (Fig. 4.11a and 4.11b). In contrast, a positive writing voltage with the same
56
Figure 4.11: Symmetrical bit writing in GFeFETs. (a) and (b) Writing “1” using a
negative V
writing
. (c) and (d) Writing “0” using a positive V
writing
. Dashed and solid
arrows indicate the forward and backward voltage sweep directions respectively. The
writing procedures are independent on the initial states before writing. Here, n
BG
is
chosen to match -βP
r

/e so that one of the resistance peaks is near the Dirac point.
(e) and (f) Fatigue test of one GFeFET with symmetrical bit writing. Non-volatile
switching cycles exceeding 100k cycles is shown. Inset: Raw data of the fatigue test.
n
BG
≈ 1.2 ×10
12
cm
2
is chosen to match -βP
r
/e.
magnitude sets the GFeFET into low resistance “0”, as shown in Fig. 4.11c and 4.11d.
Compared to the asymmetrical bit writing by polarizing (P
↑
= P
r
) and depolarizing
the ferroelectric (P
↓
≈ 0) alternately [66], such symmetrical writing in GFeFETs
not only provides simplicity but also takes full advantage of the fast switching speed
of ferroelectric. For lead zirconate titanate (PZT) based materials, this can be as
fast as 280 ps [99]. Another potential application of this electrostatic effect could be
multi-bit-per-cell data storage in GFeFETs utilizing the n
BG
tunable △R/R.
We have also tested the reproducibility of our GFeFETs working with βP
r
≈ |n

∗
|e.
During the fatigue test, a triangular wave of 1k Hz was applied to the P(VDF-TrFE)
57
thin film. Every 12 (24) seconds, the triangular wave was interrupted and one R vs
V
TG
curve was recorded. The corresponding △R/R as a function of switching cycles
and the raw data of individual R vs V
TG
curve are summarized in Fig. 4.11e and 4.11f
respectively. The fatigue test clearly demonstrates reproducible non-volatile switching
exceeding 100k cycles in the GFeFET. Ultimately, the life span of P(VDF-TrFE)-
based GFeFETs is only limited by the endurance of P(VDF-TrFE) (10
7
[95]). Thus,
P(VDF-TrFE)-GFeFET memory could provide a cost-effective solution for flexible
non-volatile data storage with sub-µs switching speed. On the other hand, inorganic
ferroelectric (such as PZT) should be used if fast writing speed (< 10 ns) and ultra-
high endurance (10
10
) are required.
4.2.3 Understanding of ferroelectric gating
In the following, we show a quantitative understanding of graphene devices under
ferroelectric gating. This is because although GFeFETs have potential applications
for non-volatile memory and data storage [66], a comprehensive understanding in the
hysteretic ferroelectric gating is still missing. In contrast to linear doping with nor-
mal gate dielectrics, n = αV
g
[21], the non-linear dielectric behavior of ferroelectrics

introduces a pronounced hysteresis in the charge carrier doping. Furthermore, ferro-
electric gating introduces strong electron-hole puddles in graphene even far away from
the Dirac point. Therefore, Hall measurements alone can not be used to determine
the induced charge carrier concentration (Fig. 4.12). Last but not least, ferroelectric
gating is characterized by two symmetrical remnant polarizations, i.e., P
↑
= P
r
and
P
↓
= −P
r
for upwards and downwards dipole configurations, respectively. Conse-
quently, P
↑
and P
↓
induce two identical zero-field resistance states in graphene [66],
58
which is not practical for devices applications.
d
Figure 4.12: (a) R vs V
TG
and V
BG
of GFeFET. (b) Top: Single trace of R vs V
TG
with V
BG

= 30 V; Bottom: the corresponding V
Hall
vs V
TG
characteristic showing all
negative Hall signals, independent of ferroelectric dip ole flipping. (c) Top: Single
trace of R vs V
TG
with V
BG
= −6 V; Bottom: the corresponding V
Hall
vs V
TG
char-
acteristic showing all positive Hall signals. (d) The corresponding ferroelectric and
non-ferroelectric phase diagram for the explanation of the Hall measurement results.
When P(VDF-TrFE) is polarized, gate-tunable electron-hole puddles exist in
graphene over a wide range away from the Dirac point. Thus, Hall signals can not
be directly used to deduce the mobility. Fig. 4.12a shows the resistance vs V
TG
and
V
BG
characteristics of a GFeFET after fully polarizing P(VDF-TrFE). V
TG
is swept
in a close loop (0 → 30 → −30 → 0 V) with different set points of V
BG
. For single

59
traces of R vs V
TG
, Hall signals also show pronounced hysteresis due to ferroelectric
gating. However, Hall signals do not change the signs over the whole V
TG
sweeping
range, indicating the existence of minority charge carriers which are not controlled
by ferroelectric gating (Figs. 4.12b and 4.12c).
The origin of all positive/negative Hall signals is illustrated in Fig. 4.12d. Around
5-20% area of P(VDF-TrFE) thin films is non-ferroelectric, which cannot be polarized
by external electric field [95]. Thus, ferroelectric gating introduces strong electron-
hole puddles in GFeFETs since graphene is inhomogeneously doped by ferroelectric
and non-ferroelectric phases respectively. As shown in Fig. 4.12, the sign of the Hall
signal dependents on the minority charge carriers in the non-ferroelectric doped areas,
which is controlled by the SiO
2
gating.
4.3 Summary and conclusion
In summary, we have demonstrated the working principle and real device operation
of a novel hybrid non-volatile memory device using graphene based on ferroelectric
substrates. By tuning the ferro electric dipoles to be either highly order or highly
disorder, a reversible non-volatile switching between the high and low resistance states
in graphene have been realized. Using an independent linear dielectric gating (n
BG
) as
a reference, we show that ferroelectric gating can be quantitatively determined by the
electric displacement continuity equation. n
BG
can also be used to control ferroelectric

gating by introducing a unidirectional shift in the hysteretic ferroelectric doping in
GFeFETs. This effect allows symmetrical bit writing in non-volatile GFeFETs with
resistance change ratio over 500% and switching cycles exceeding 10
5
cycles. These
make this new memory structure a promising candidate for the next generation of
60
ultra-fast non-volatile memory. To realize precise control of n
BG
, it will be crucial
to prepare graphene on ferroelectric substrates and introduce fixed molecular doping
by donor/acceptor molecules. An alternative way to introduce a fixed strong n
BG
in
graphene can be realized by using epitaxial graphene on SiC wafers.