Control of resist processing in lithography

CONTROL OF RESIST
PROCESSING IN LITHOGRAPHY
KIEW CHOON MENG
B.Eng.(Hons.), NUS
A THESIS SUBMITTED
FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
NUS Graduate School for
Integrative Sciences and Engineering
NATIONAL UNIVERSITY OF SINGAPORE
2007
Acknowledgments
Firstly, I would like to thank Agency for Science, Technology and Research
(A*STAR) for giving me the scholarship to do my graduate studies locally.
I also like to thank Institute of Chemical and Engineering Sciences (ICES)
for providing my living exp enses during my one year attachment at Georgia
Institute of Technology, USA.
Secondly, I would like to express my deepest gratitude to the following
supervisors. They are Dr Lim Khiang Wee, Dr Arthur Tay and Associate
Professor Ho Weng Khuen. I thank them for their support, guidance and en-
couragement during my graduate years in National University of Singapore.
I thank them for their consistent involvements, suggestions, enlightenments
and help in every aspect of my research. Without their guidance, this work
would not have been possible. I thank them for their gracious understanding
and supports on many aspects of life beyond research. I would also like to
express my greatest gratitude to Professor Jay H. Lee from Georgia Institute
of Technology, USA and Ms Zhou Ying from ICES for their helpful insights,
invaluable suggestions and comments on my research. I thank them for their
detailed guidance at different stages of my research progress as well as their
professional attitudes towards research.
Then, I would like to thank Mr Wu Xiao Dong and Ms Hu Ni for sharing
precious ideas and comments on this work. I would also like to thank mem-

bers of Integrated Sensing, System Identification, and Control (ISSICS) Lab-
i
Acknowledgments ii
oratory, at Georgia Institute of Technology, especially Mr Wong Wee Chin,
Mr Nikolaos Pratokakis and Mr Jihoon Lee, for their hospitality and contri-
butions during my one year attachment there. I would like to thank Mdm S.
Mainavathi of Advanced Control Technology (ACT) Laboratory, NUS and
Mr Lok Boon Keng and Ms Lu Haijing of Singapore Institute of Manufactur-
ing Technology (SIMTech) for the logistics and technical support during my
graduate years. I would like to thank all my friends in the student cluster at
SIMTech for their friendship and encouragement during my attachment at
the institute.
Finally, I would like to thank my two good friends, Mr Johnathan Cheah
and Mr James Goh, who constantly gave me their moral support and en-
couragement during all these years. I would like to thank my parents, Mr
Kiew Seng Fatt and Mdm Leow Soon Yen, for their unconditional love and
support. I would also like to thank my two sisters, Ms Kiew Mee Ling and
Ms Kiew Mee Foong, for their help and encouragement.
Contents
Acknowledgments i
Summary v
List of Figures vii
List of Tables x
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Film Thickness Analysis & Estimations During Develop Step 10
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Optical Interference in Thin Film . . . . . . . . . . . . . . . . 12

2.3 Equipment Setup . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Conventional Thickness Estimation
Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5 Proposed Methods . . . . . . . . . . . . . . . . . . . . . . . . 21
2.6 Comparison of Different Thickness
Estimation Methods . . . . . . . . . . . . . . . . . . . . . . . 28
2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3 Real-Time Feedback Control for Develop Step 31
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . 32
iii
Contents iv
3.3 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 37
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4 Optimal Multi-Zone Feed-Forward Control in Baking Steps 45
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2 Multi-Zone Bake-Plate Thermal Model . . . . . . . . . . . . . 48
4.3 Multi-Zone Feed-forward Control . . . . . . . . . . . . . . . . 52
4.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 56
4.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5 A Robust Run-to-Run Control using Minimax Function 63
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2 Review of Run-to-Run Controller . . . . . . . . . . . . . . . . 65
5.3 Minimax Formulation . . . . . . . . . . . . . . . . . . . . . . . 68
5.4 Simulation & Results . . . . . . . . . . . . . . . . . . . . . . . 69
5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6 Conclusions 82
6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Appendix : Proof 87
Author’s Award & Publications 91
Bibliography 93
Summary
Optical lithography is a key enabling technology in semiconductor manufac-
turing industry that represents 30-35% of chip manufacturing cost. As device
size gets smaller, lithography process needs to meet the tighter constraints
and more stringent specifications to achieve tight line-width or critical dimen-
sion (CD) uniformity. This is because CD is the most important variable that
needs to be well controlled as it affects not only the final device speed but
also the overall circuit performance.
Lithography involves many steps and non-uniformity introduced at each
step can roll over to subsequent steps to cause CD variations. This thesis
proposes control strategies to reduce CD variations by improving various
steps/aspects of the lithography process. Firstly, real-time control of develop
step, i.e. the step where photoresist take the final form of the desired features,
is performed using a reconfigurable bake/chill system with an online film
thickness estimation. Results showed four times reduction in deviation of
the end-point time and 20% reduction in overall developing time.
As lithography advances, chemically amplified photoresist is introduced
to achieve smaller line-width. This photoresist, however, requires stringent
temperature control during post-exposure-bake step because the heat from
this baking step is used to enhance and amplify the chemical reaction of the
exposed site in the photoresist. The main source of CD variations at this
step is poor temperature uniformity control and temperature disturbances
v
Summary vi
caused by placement of cold wafers on the bakeplate. To overcome this, a
feed-forward control strategy is applied to the bake/chill system used in the
develop step earlier. Results showed that the temperature disturbance is

almost eliminated, with overall temperature uniformity within 0.1
o
C.
Lastly, variations in lithography process such as process drifts and deteri-
oration of equipment often increase sensitivity of plant model to disturbances.
Nevertheless, the bounds of these variations are usually known, although on-
line information is unavailable. In this case, a robust run-to-run controller
that uses minimax function can be used to minimize the worst predicted
scenario, thus compensating for the plant model variations. Results showed
that using this approach, a ten times reduction in overshoot is achievable.
As the approach is reducible to a minimization problem, faster and more
efficient computation can also be performed.
List of Figures
1.1 A flowchart showing the typical steps involved in a lithography
process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 An optical model of the reflected light intensity in the pho-
toresist and wafer substrate interface. . . . . . . . . . . . . . . 12
2.2 A schematic diagram of the spectrometry system setup used
in experiment for thickness analysis. . . . . . . . . . . . . . . . 14
2.3 Emulating puddle spray method for develop step . . . . . . . . 15
2.4 Experimental setup showing the bake/chill system and an ar-
ray of spectrometry probes . . . . . . . . . . . . . . . . . . . . 16
2.5 Experimentally acquired reflected light intensity plots corre-
sponding to six different film thicknesses in comparison to the-
oretical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6 Graph showing turning points in the reflected light intensity
profile, acquired at one time instance, that are used in the
Fringe Order Computation (FOC) method. . . . . . . . . . . . 19
2.7 Illustrations showing the tagging of six intensity plots with
reference thickness information that are used in the Lookup

Table Referencing (LTR) Method. . . . . . . . . . . . . . . . . 22
2.8 3D plot of the reflected light intensity with 2D planes drawn
to show the different analytical perspectives of this data. . . . 25
2.9 A graph showing the reflected light intensity profile of a fre-
quency slice at wavelength, λ = 707nm, which shows turning
points similar to that of a time slice. . . . . . . . . . . . . . . 26
2.10 A flow chart showing the procedures for MFOC computation
during real-time thickness estimation. . . . . . . . . . . . . . . 27
vii
List of Figures viii
2.11 Comparing different thickness estimation methods on a set of
intensity data with end-point near 70 seconds . . . . . . . . . 29
3.1 Graph showing that a develop trend follows exponentially de-
caying function. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2 A schematic block diagram of the bake/chill system . . . . . . 36
3.3 Block diagrams of of the overall control system, showing the
flow of information between software and hardware. . . . . . . 37
3.4 Graph showing the time taken to reach end-point for 9 con-
ventional runs and 9 controlled runs . . . . . . . . . . . . . . . 38
3.5 Two experimental results for a single point real-time develop
control of different wafer. (a) Thickness profiles of this two
points during different develop step. (b) The tracking error
in thickness during these two experiments. (c) Bake plate
temperature during the experiment. (d) The corresponding
control signal applied. . . . . . . . . . . . . . . . . . . . . . . 42
3.6 Experimental results of an uncontrolled develop step with 2
sites thickness monitoring system. (a) Thickness profiles of
these 2 sites during develop step. (b) The within wafer thick-
ness non-uniformity during the develop step. . . . . . . . . . . 43
3.7 Experimental results of a within wafer thickness uniformity

control of 2 points on a wafer. (a) Thickness profiles of these 2
points during one develop step. (b) The within wafer thickness
non-uniformity plot. (c) Bake plate temperature of the points
under controlled. (d) The corresponding control signal applied. 44
4.1 Comparison of bake-plate temperature disturbance caused by
the placement of a cold wafer on the multi-zone bake-plate.
Multi-zone feed-forward algorithm: solid-line; single-zone feed-
forward algorithm: dashed-line; proportional-integral feedback
control only: dotted-line. . . . . . . . . . . . . . . . . . . . . . 47
4.2 Schematic diagram of the multi-zone bake-plate . . . . . . . . 48
5.1 Input-output relationship for (a) Example 1 and (b) Example
2, assuming no disturbance. . . . . . . . . . . . . . . . . . . . 72
List of Figures ix
5.2 Disturbance signal for (a) Example 1 and (b) Example 2 . . . 74
5.3 Output response of (a) Example 1 and (b) Example 2 using
formulation I with linearized gain . . . . . . . . . . . . . . . . 75
5.4 Output response of (a) Example 1 and (b) Example 2 using
formulation II . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.5 Five different type of gain variations . . . . . . . . . . . . . . 77
5.6 Results obtained for (a) Plant Type I and (b) Plant Type II . 81
List of Tables
4.1 Comparison of the settling time, temperature deviation and
integrated square error for multi-zone and single-zone feed-
forward control algorithm. . . . . . . . . . . . . . . . . . . . . 62
5.1 Performance of d-EWMA versus optimal filter . . . . . . . . . 71
5.2 Performance of two control formulations on two different plant
types models . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
x
Chapter 1
Introduction

1.1 Motivation
Optical lithography has been the key technology in semiconductor manufac-
turing for the past fifty years that drives the trend of smaller and cheaper
electronic devices. Semiconductor manufacturing is now facing an increas-
ing challenge to keep up with Moore’s Law. Currently, optical lithography
is capable of printing 32nm size features with optical wavelength at 193nm
(Trouiller, 2006). However, this has led to the belief that optical lithography
has reached its physical limit.
This theoretical optical limitation has been discussed by Harriott (2001),
Mack (2004) and Trouiller (2006). As a result, this brought about many
new and innovative printing transfer methods being developed but none has
yet to take over lithography’s role totally. One of the reasons why new
methods fall short is that optical lithography remains the most cost effective
method ever invented. Despite this cost effectiveness, it represents around
30%-35% of the manufacturing cost (Plummer et al., 2000) which impedes
technological change for existing semiconductor manufacturing industries.
One of the measures for lithographic quality discussed by Mack (2004) is
‘Manufacturability’ and he commented that:
1
Chapter 1. Introduction 2
“What makes this metric so interesting, and difficult to optimize,
is the relationship between cost and other metrics of quality such
as CD control. While buying ultra flat wafers or upgrading to
the newest stepper platform may provide an easy improvement
in CD and overlay performance, their benefit may be negated by
the cost increase. It is interesting to note that throughput (or
more correctly overall equipment productivity) is one of the major
components of lithographic cost for a fab that is at or near capacity
due to the normal factory design that places lithography as the fab
bottleneck.”

In lithography process, the most important variable is the linewidth or
critical dimension (CD), which is the variable with the most impact on de-
vice speed and performance (Edgar et al., 2000). The ability to reach today’s
32nm standard is attributed to the countless efforts to keep abreast with the
International Technology Roadmap for Semiconductors (ITRS). These in-
clude the introduction of new lithography techniques, new photoresist mate-
rials, new equipment and tighter process specifications. Multi-zone control-
lable bakeplate system has been introduced to compensate non-uniformity
caused by conventional bakeplate during baking steps (Berger et al., 2004;
Chua et al., 2007; Ho et al., 2000; Lee et al., 2002; Narasimhan and Ramanan,
2004; Tay et al., 2001). Researchers also see the importance of controlling
develop step since it is one of the crucial steps in lithography that deter-
mines the final CD. Their efforts include determining the best time to switch
from developing to rinsing (Carroll and Ramirez, 1991), controlling flow-rate
of developer solution from the dispenser (Sakamoto, 2001; Sakamoto et al.,
2002), and using multiple develop steps with different developer concentra-
tions (Kyoda et al., 2003) in order to achieve better CD uniformity.
Chapter 1. Introduction 3
There are also reports of increasing utilization and application of ad-
vanced computational and control methodologies that showed improvement
in yields, throughput and in some cases, enable lithography process to print
even smaller features (Harriott, 2001; Mack, 2004; Schaper et al., 1999). The
success of applying such mathematical systems and advanced tools to micro-
electronics manufacturing has also been demonstrated in the area of rapid
thermal processing (Cho and Kailath, 1993; Stuber et al., 1998) and plasma
processing (Hankison et al., 1997). A report of the international panel on
future directions in control, dynamics and systems has also identified control
as a critical research topic to future progress in the semiconductor manufac-
turing sectors (Mack, 2004; Murray et al., 2003).
Lithography plays an important role in semiconductor manufacturing. It

is a fabrication process that transfers desired circuit patterns from a photo-
mask onto a photosensitive resist film that has been coated on top of a silicon
substrate or wafer. (In this thesis, photosensitive resist, photoresist and resist
are used interchangeably to refer to the same thing unless otherwise stated.)
It determines the device dimensions, which affects not only device’s quality
but also production quantity and manufacturing cost. Figure 1.1 depicts the
various steps involved in lithography process, of which four are baking steps.
There are many factors that contribute to the final variation of the printed
CD. Any drifts or variations in the lithographic process variables will affect
the final CD. Very often, non-uniformities from earlier steps are rolled over
to the next step. In addition to that, equipment used for any particular
step may contribute non-uniformity to the final CD. It is known that spin
coating causes non-uniform film thickness spatially. Subsequently, thickness
non-uniformity will result in variation of UV absorption in the resist during
exposure step. Despite that, light intensity varies spatially in the exposure
Chapter 1. Introduction 4
1. HMDS
Vapor Prime
2. Spin Coat
3. Soft Bake
4. Align &
Exposure
5. Post-
Exposure Bake
6. Develop
7. Hard Bake8. Etch
Figure 1.1: A flowchart showing the typical steps involved in a lithography
process.
machine which adds on to the overall non-uniformity. This explains why
resist thickness has to be well controlled at the extrema of the swing curve

(Brunner, 1991) where sensitivity of CD to thickness variations is minimal.
One of the “grand challenges” mentioned in ITRS (2006) is to make lithog-
raphy affordable and available even beyond 100nm size.
Therefore, one exciting new challenge in lithography is the development
of control and optimization strategies that has the ability to comp ensate any
non-uniformities in earlier steps/processes (Edgar et al., 2000). An effective
process control scheme should not only resolve many integration problems,
but also speed up development time with little or no change to current equip-
ment. Develop step is an important step in lithography. As mentioned before,
it is where the photoresist takes the form of the desired pattern. Thus, it
will be ideal if this step can be controlled and used to compensate any non-
Chapter 1. Introduction 5
uniformities built-up from previous steps. However, Morton et al. (1999)
mentioned the difficulty of monitoring the thickness trend during develop
step which this thesis will address and overcome. Other than controlling
develop step, with the introduction of chemically amplified photoresist, the
demand for tighter temperature uniformity and ability to reject temperature
disturbance caused by placement of cold wafer on the bakeplate need to be
addressed. In addition to that, it is important to formulate a way to minimise
the worst senario when controlling lithography process because this process
often suffer gain variations.
1.2 Contributions
The main focus of this thesis is in reducing CD variation by applying con-
trol strategy in lithography process and the use of advanced reconfigurable
bakeplate system. There are four main contributions,
• Real-Time Film Thickness Monitoring System
• Real-Time Develop Rate Control
• Optimal Feed-Forward Control for Multi-zone Baking
• Robust run-to-run control
Real-Time Film Thickness Monitoring System

To have better CD control, mere end-point (the time when all unwanted
photoresist are removed/dissolved) detection in develop step is insufficient.
It will be ideal to be able to monitor the trend at which photoresist dissolves
during develop step at real-time. Unlike common film thickness estimation
which has air as the medium, the develop step has developer solution as the
Chapter 1. Introduction 6
medium. This makes analysis more difficult because the refractive index of
the developer solution varies with time as the photoresist dissolves. There are
many methods to compute film thickness by analyzing reflected light inten-
sity profile but all of them fail to give reasonable thickness estimation. They
either produce results that show diverging thickness trend or erroneous re-
sults. Therefore, Lookup Table Referencing (LTR) is first introduced to solve
this problem because it is able to compensate the change in optical properties
during develop process by storing a set of reflected light intensity profile of a
typical develop step. However, LTR is not robust to batch or recipe change.
Thus, Modified Fringe Order Computation (MFOC) is later introduced as a
more robust thickness estimator. MFOC does not require prior experimental
data and it is computationally less intensive than conventional methods.
Real-Time Control of Develop Step
Most semiconductor manufacturing industries practise longer develop times
to ensure that there will be less under-developed features. Others would
choose a tradeoff between the number of over-developed and under-developed
features. However, to push lithography to its limits, a better control need
to be developed. It is known that developer temperature has a direct influ-
ence over develop rate (Arthur et al., 1997; Pantenburg et al., 1998; Shaw
and Hatzakis, 1979). Thus, if the developer temperature were to be con-
trolled, then spatial and temporal uniformities during develop step would
be achievable. A reconfigurable multi-zone bake/chill system is used which
allows the manipulation of its plate temperature by adjusting the amount of
electrical power flowing into the resistive elements. It has been shown that

this system, together with real-time thickness estimator mentioned earlier, is
able to compensate and reduce the non-uniformities from previous steps in
Chapter 1. Introduction 7
lithography process. Results showed that a controlled develop step is capable
of reducing the deviation of the time to reach end-point by four times. In
addition to that, this system is also capable of reducing the overall develop
time by 20%. This real-time control approach produces better uniformity
with shorter developing time.
Optimal Feed-Forward Control for Multi-zone Baking
In lithography, as depicted in Figure 1.1, wafers are frequently transferred
from one processing step to another. One of the most common steps is the
baking step. The same reconfigurable multi-zone bakeplate used for develop
control mentioned earlier can be used for these baking steps too. Among
these many baking steps, the most important (or temperature sensitive) is
the post-exp osure bake step. For chemically amplified photoresists, the tem-
perature of the wafer during this thermal step must be controlled to a high
degree of precision for better CD control. The requirements call for tem-
perature to be controlled within ±0.1
o
C at temperature between 70
o
C and
150
o
C. Conventional bakeplates are not capable of providing adequate spa-
tially temperature uniformity. Multi-zone bakeplate with independent Single
Input Single Output (SISO) controlled zones had issues like overheating and
slow response time because this approach assumed no coupling effect like
heat exchange from neighboring zones. Thus, a multi-zone bakeplate ther-
mal model, with wafer taken into consideration, is derived. An algorithm for

a feed-forward control of the multi-zone bake plate is developed which almost
eliminates the temperature disturbance caused by the placement of a cold
wafer on the bake plate. With feed-forward control in-force, temperature
uniformity of ±0.1
o
C is achievable, as compared to ±0.5
o
C for independent
SISO method.
Chapter 1. Introduction 8
Robust Run-to-Run Control
Most semiconductor manufacturing processes exhibit linear drifts from run-
to-run due to changing processing environments like batch, recipe and mate-
rial changes. Electro-migration is another problem which a bakeplate system
may suffer that causes the system to deviate from its initial mathematical
model. In addition to that, the mode and size of variation of the process gain
is often unknown. These issues often increase sensitivity of plant models to
disturbances. If these variations bounds are known, then a robust run-to-run
control method that takes into account of this knowledge can perform better
than conventional methods. This method uses a minimax function which
in general tries to minimize the worst predicted case scenario. The benefits
from this approach for scenarios where disturbances are injected into the sys-
tem are lower overshoot (more than ten times reduction) and shorter settling
time. In addition to that, this minimax approach is reducible to a mini-
mization problem under a specific condition, which gives this approach the
computational advantage over solving the original minimax problem. This
approach can be solved more easily and also have the benefit of minimizing
the worst predicted case.
1.3 Thesis Organization
This thesis consists of six chapters. The first chapter gives the motivation of

this research work and the author’s main contributions. Chapter 2 provides
the working principle behind the optical model for determining thin film
thickness information from reflected light intensity acquired by a spectrom-
etry system. It then introduces two conventional techniques for estimating
film thickness profile, after which, two new methods are proposed. Chapter
Chapter 1. Introduction 9
3 presents the work on real-time control of the develop step. It first describes
the analysis of the relationship between develop rate and temperature. Fol-
lowing that, the use of a Proportional and Integral (PI) controller to achieve
develop control will be presented. Chapter 4 will present the work on optimal
feed-forward control for multi-zone baking in lithography. It will first derive
the thermal model and then elaborate on the control algorithm used. Chap-
ter 5 describes an optimal filter for Integrated Moving Average, IMA(2,2),
process and a robust run-to-run controller that uses the minimax approach
that is capable of reducing overshoot by at least ten times as compared to
conventional run-to-run controllers. This minimax approach is reducible to
a simple minimization problem. Finally, this thesis will end with conclusions
and recommendations for future work and directions.
Chapter 2
Film Thickness Analysis &
Estimations During Develop
Step
2.1 Introduction
Develop step is a crucial step in lithography because it determines how fea-
tures on the wafer are developed. Over developed or under-developed is
deemed undesirable. The desirable time to stop develop step is when all
the exposed positive photoresist or all the unexposed negative photoresist
at a particular site are removed. Therefore, it will be useful if a monitoring
system can be developed for this purpose.
An equipment with this monitoring capability is commonly known as a

Develop Rate Monitor (DRM). The detection of the desirable time to stop
develop step is known as ‘end-point detection’. In industry, DRM has been
used as end-point detector. DRM is able to monitor the rate at which pho-
toresist dissolves in the developer solution during develop step. It identifies
end-point when the dissolution rate becomes zero. In recent years, there are
innovative development in DRM sensors with the use of Ultra Sonic Sensor
(Morton et al., 1999) and the deduction made from measuring the resistivity
10
Chapter 2. Film Thickness Analysis & Estimations During Develop Step 11
of the develop solution (Wang et al., 2003) to estimate develop rate. How-
ever, as mentioned in Chapter 1, in order to push lithography technology to
its limit, mere end-point detection control is inadequate.
Develop rate monitoring is very similar to thin film thickness estimation
in any etching or metal deposition processes found in semiconductor manu-
facturing. For example, Lee et al. (2002) have used an optical spectrometry
system to estimate film thickness in their real-time film thickness uniformity
control during soft bake step. However, the only difference between these
settings is the medium at which optical light passes through during thick-
ness detection. Develop step has a fluid medium instead of air. Morton
et al. (1999) has mentioned the difficulty of estimating film thickness dur-
ing dissolution of photoresist in developer solution. In general, dissolution
of photoresist often leads to changes in chemical and optical properties of
the developer solution which hinder thickness estimation algorithms. The
deviation becomes larger as more photoresist dissolve in the solution. This
chapter will proposed two thickness estimation methods to addressed this
issue.
The organization of this chapter is as follows. In the next section, the
mathematical model of the reflected light intensity in thin film will be pre-
sented. Following that, the experimental setup used for this work will be
presented in Section 2.3. Then, in Section 2.4, conventional thickness esti-

mations will be discussed, after which, two new methods, namely Lookup
Table Referencing (LTR) and Modified Fringe Order Computation (MFOC)
will be proposed and their strengths and weaknesses will be discussed in Sec-
tion 2.5. In Section 2.6, a comparison of the results obtained using these
methods will be presented. Finally, this chapter will end with a conclusion.
Chapter 2. Film Thickness Analysis & Estimations During Develop Step 12
Developer Solution
Photoresist
Silicon Substrate
Incident
Light
Reflected
Light
N
a
Y
N
r
N
s
Figure 2.1: An optical model of the reflected light intensity in the photoresist
and wafer substrate interface.
2.2 Optical Interference in Thin Film
This section will explain the fundamental principles behind using optical
spectrometry for film thickness estimation. This will help the development
of film thickness estimation algorithms in later sections.
When an incident light is made to shine normally onto a thin photoresist
film, as shown in Figure 2.1, phase difference between the incident and re-
flected light creates interference effects within the photoresist of thickness, Y .
This phenomenon is dependent on the wavelength of the incident light and

the refractive index of the materials which the light passes through (Born
and Wolf, 1985; Hariharan, 2003).
Refractive index of a material is nonlinear in nature and can be described
by Cauchy Equation with three parameters, A , B and C. In this chapter,
refractive index is denoted by N
∗
with the subscript denoting the medium
concerns. Thus, N
a
, N
r
and N
s
denote the refractive index of the develop er
solution, the photoresist and the silicon substrate, respectively. Therefore,
the refractive index of the photoresist corresponding to a particular wave-
length, λ
i
, can be expressed in the form as shown in Equation (2.1).
Chapter 2. Film Thickness Analysis & Estimations During Develop Step 13
N
r,i
= A +
B
λ
2
i
+
C
λ

4
i
(2.1)
The mathematical representation of the reflected light intensity signal,
H
i
(t), for a particular wavelength, λ
i
, can be expressed in the form as shown
in Equation (2.2).
H
i
(t) =




R
2,i
· e
−jβ
i
(t)
+ R
1,i
· e
jβ
i
(t)
R

1,i
· R
2,i
· e
−jβ
i
(t)
+ e
jβ
i
(t)




2
×
1
R
2
0,i
(2.2)
where j denotes the imaginary part,
| • |
2
represents the complex norm operator,
R
0,i
=
N

a,i
− N
s,i
N
a,i
+ N
r,i
,
R
1,i
=
N
a,i
− N
r,i
N
a,i
+ N
r,i
,
R
2,i
=
N
r,i
− N
s,i
N
s,i
+ N

r,i
, and
β
i
(t) =
2πN
r,i
Y (t)
λ
i
.
2.3 Equipment Setup
In this work, S1813 positive photoresist is used. It is first spin-coated at 2000
rpm for 45 seconds onto a 4-inch silicon wafer. The wafer is then baked at
105
o
C for 90 seconds during soft bake step. After which, the coated wafer
is exposed to ultraviolet light for 3 seconds, which destroys the photoactive
compound, which is a dissolution inhibitor found in the photoresist resin
(Chang and Sze, 1996). The exposed photoresist then becomes more soluble
in MF319 developer solution. The post exposure bake is conducted at 105
o
C
for 60 seconds.
Chapter 2. Film Thickness Analysis & Estimations During Develop Step 14
Figure 2.2: A schematic diagram of the spectrometry system setup used in
experiment for thickness analysis.
Optical Spectrometry System for Thickness Estimation
An optical spectrometry system from Oceans Optics is used to acquire the
reflected light intensity signal. The system, as shown in Figure 2.2, consists

of a light source, optical probes and an acquisition unit which is capable of
measuring light intensity at discrete wavelengths between 400nm and 900nm.
Let the discrete wavelengths detectable by the system be denoted by an
vector, λ. The optical probe is made up of a bundle of 7 optical fibers
(6 illumination fibres around 1 read fiber) is positioned above the wafer to
monitor the photoresist thickness at real-time. It is made to shine light from
a broadband light source, normal to the thin film surface. The reflected light
intensity signal, denoted by an vector, H, is sampled at a rate of 10Hz.
Emulating Develop Step
In lithography, there are two basic approaches to photoresist develop step:
the puddle spray method and the immersion method. In the puddle spray
method, developer solution is sprayed onto the film surface so that a puddle
of developer solution forms on top of the resist surface. As for immersion