Hafnium oxide based high k dielectric gate stack

Acknowledgements

ACKNOWLEDGEMENTS

Firstly, I would like to express my deepest appreciation to my supervisors, Professor
Ong Chong Kim (Department of Physics, National University of Singapore) and
Professor Alfred, Huan Cheng Hon (Division of Physics & Applied Physics, Nanyang
Technology University and Institute of Materials Research & Engineering), for their
excellent guidance, constructive comments, and valuable support during my PhD
candidacy. Their profound knowledge and rigorous scientific approach have greatly
inspired me in the research.
Secondly, I would like to express my sincere gratitude to my co-supervisor, Dr. Wang
Shijie, research scientist from Institute of Materials Research & Engineering. He has
constantly provided me with excellent guidance and support for both of my professional
and personal developments. His kindness and integrity have always been a good example
for me even in my future career. Thanks for teaching me many experimental and
analytical skills used in this research work. I am truly grateful for all his help and
encouragement during the course of this research.
My thankfulness also extends to two great persons in our research group, Dr. Dong
Yufeng and Dr. Mi Yanyu, for their self-giving help and kindly encouragement in the last
few years. Thanks for the happy time with them during my PhD study.

i


Acknowledgements

This research would not have been possible without much assistance from scientists
and researchers at NUS and IMRE as well as excellent research equipments provided by
NUS and IMRE. I would like to specially thank a few more persons here: Prof. Feng
Yuanping, Dr. Pan Jisheng, Dr. Chai Jianwei, Mr. Lim Poh Chong, Ms. Chow Shue Yin,

Mr. Wang Weide, Dr. Li Zhengwen, Dr. Kong Lingbin, Dr. Yan Lei, Dr. Tan Chin Yaw,
and Mr. Liu Huajun. Many thanks also go to Dr. Ng Tsu Hau, and his supervisor,
Associate Prof. Chim Wai Kin, from Department of Electrical and Computer Engineering,
NUS, for their technical supports to this work.
Finally, I would like to dedicate this thesis to my parents, for their consistent
encouragement, support and understanding during my study in Singapore. Lastly but not
least, I wish to express sincere gratefulness and indebtedness to my husband, Mr. Guan
Zhiyong, for his endless love and strong support.
If I forgot anybody in this list, it was done by mistake rather than intention.

ii


Table of Contents

TABLE OF CONTENTS

ACKNOWLEDGEMENTS...................................................................................................................i
TABLE OF CONTENTS .....................................................................................................................iii
SUMMARY............................................................................................................................................v
LIST OF FIGURES.............................................................................................................................vii
LIST OF TABLES ...............................................................................................................................xi
LIST OF PUBLICATIONS ................................................................................................................xii
Chapter 1 Introduction .........................................................................................................................1
1.1 Introduction .......................................................................................................................................1
1.2 An overview of device scaling ..........................................................................................................3
1.3 Limitations for gate oxide (SiO2) scaling..........................................................................................5
1.4 Alternative high-k gate dielectrics candidates and materials properties considerations ....................9
1.5 Metal gate candidates and materials properties considerations....................................................... 17
1.6 Band alignments at metal/high-k/semiconductor interfaces............................................................ 19

1.7 Motivations and scope for present work ......................................................................................... 23
Reference ............................................................................................................................................ 26
Chapter 2 Film Deposition, Characterization Techniques and Modeling Methods ...................... 33
2.1 Introduction ..................................................................................................................................... 33
2.2 Film deposition techniques.............................................................................................................. 34
2.3 Characterization techniques ............................................................................................................ 39
2.4 First-principles calculation.............................................................................................................. 46
Reference ............................................................................................................................................ 49
Chapter 3 Thermodynamics and Thermal Stability Study of HfO2 films in Contact with Si....... 51
3.1 Introduction ..................................................................................................................................... 51
3.2 Thermodynamic study of HfO2 films on SiO2-covered silicon ....................................................... 53
3.3 Thermal stability of UHV sputtering HfO2 films by plasma oxidation and low temperature

iii


Table of Contents
annealing ............................................................................................................................................... 60
3.4 Conclusion....................................................................................................................................... 70
Reference ............................................................................................................................................ 72
Chapter 4 Highly Thermal Stable (HfO2)1-x(Al2O3)x Films.............................................................. 75
4.1 Introduction ..................................................................................................................................... 75
4.2 (HfO2)1-x(Al2O3)x films fabricated by dual-beam pulse laser deposition......................................... 76
4.3 Thermal stability of (HfO2)1-x(Al2O3)x/Si interface ......................................................................... 77
4.4 (HfO2)1-x(Al2O3)x/Si interface structure at atomic scale .................................................................. 82
4.5 Electrical characterization of (HfO2)1-x(Al2O3)x/Si stacks............................................................... 85
4.6 Stress testing of (HfO2)1-x(Al2O3)x films as gate dielectric.............................................................. 88
4.7 Frequency dependent properties of (HfO2)1-x(Al2O3)x films as gate dielectric................................ 93
4.8 Conclusion....................................................................................................................................... 95
Reference ............................................................................................................................................ 96

Chapter 5 Interfaces of Metal Gate/ HfO2/semiconductor System ................................................. 98
5.1 Introduction ..................................................................................................................................... 98
5.2 HfO2/Semiconductor interface ...................................................................................................... 100
5.3 Metal gate/HfO2 interface ............................................................................................................. 110
5.4 Band alignments of RuOx on HfO2/Si system ............................................................................... 116
5.5 Conclusion..................................................................................................................................... 121
Reference .......................................................................................................................................... 122
Chapter 6 Evolution of Schottky Barrier Heights at Metal/HfO2 Interfaces............................... 126
6.1 Introduction ................................................................................................................................... 126
6.2 Evolution of Schottky barrier heights at metal/HfO2 interfaces.................................................... 127
6.3 Atomistic modeling of Ni/HfO2 interfaces .................................................................................... 134
6.4 Conclusion..................................................................................................................................... 148
Reference .......................................................................................................................................... 150
Chapter 7 Conclusions and Future Work ....................................................................................... 152
7.1 Conclusions ................................................................................................................................... 152
7.2 Future work ................................................................................................................................... 154
Reference .......................................................................................................................................... 156

iv


Summary

SUMMARY

High-k dielectrics are proposed to replace traditional SiO2 as gate dielectric layer.
Meanwhile, conventional poly-silicon electrode should also be replaced by metal gates.
Metal/HfO2/semiconductor system is very promising to be used in future generation
CMOS. In this thesis, the physical, electrical and electronic properties of
metal/HfO2/semiconductor systems have been systematically studied by combining film

fabrication and characterization techniques and first-principles calculations.
The thermodynamic stability of HfO2 film has been investigated by studying the
reactions during the deposition of HfO2 thin films on SiO2-covered silicon substrates in
oxygen-deficient conditions. Thermodynamic analysis indicates that even if there is a
layer of silicate forming at the initial stage of deposition, the silicate layer or the SiO2
layer will be decomposed by metal ions and oxygen in the interfacial layer will be
absorbed by HfOx<2 to form fully oxidized metal oxide. The thermal stability of HfO2
film on silicon has been systematically investigated. As a result of high temperature
annealing, a SiO2-rich interface layer is formed after high temperature rapid thermal
annealing and the phase change of HfO2 from amorphous to crystalline has been
observed at about 700ºC. Highly thermal stable thin films of (HfO2)1-x(Al2O3)x were
fabricated on p-type Si (100), which maintain an amorphous state even with rapid thermal
annealing at 1000ºC.
The interfacial atomic structure and band discontinuity of metal/HfO2/semiconductor

v


Summary

systems for the application in electronic devices have been studied using x-ray
photoemission spectroscopy (XPS). It was found that the band alignments are substratedependent. Sufficient high valence-band and conduction-band offsets (>1.0 eV) were
obtained for HfO2/semiconductor (Si, Si0.75Ge0.25 and Ge) interfaces, which guarantees
HfO2 as an effective carrier barrier for the channels and the most promising high-k gate
dielectric candidate on Si and other high performance substrates (Si0.75Ge0.25 and Ge).
For metal/HfO2 interfaces, in situ XPS methods were performed to accurately
determine the Schottky barrier heights for Ni(Co)/HfO2 stacks. The band discontinuities
for the vacuum level were found at the interfaces of metal/HfO2. It is believed that this is
due to the dipole formed at the metal/oxide interface. Detailed studies on the evolution of
the band alignment during the formation of metal-dielectric contacts were conducted on

Ni/HfO2 stacks to clarify how the interface dipole is formed even for the simple nonreactive metal gate/high-k dielectric interface and how it influences the effective work
function of metal gate by in situ XPS and first-principles calculations based on density
functional theory. This work identified that the interface dipole was induced by the weak
interaction of Ni thin film and HfO2 dielectric.
The energy-band alignments for the RuOx/HfO2/Si stacks and the oxidation-state
dependent barrier heights for RuOx in contact with HfO2 dielectrics have been
investigated by XPS technique. The results in this work imply that the ruthenium oxide,
RuO2, is a promising alternative gate electrode to be integrated with high-k gate
dielectrics.

vi


List of Figures

LIST OF FIGURES

Figure 1.1 Gate current density as a function of gate voltage for MOS capacitors with different SiO2
gate dielectric thickness. .......................................................................................................7
Figure 1.2 Schematic energy band diagram of direct tunneling of electron from the Si substrate to the
gate in a turned on n-MOSFET (Si/SiO2/poly-Si gate structure). .........................................7
Figure 1.3 Band offset calculations for a number of potential high-k gate dielectric materials. ........... 12
Figure 1.4 Schematic band diagrams for metal/oxide/Si stacks. Definitions of band offsets (VBO and
CBO) and of SBHs (Φn and Φp) are shown. ...................................................................... 21
Figure 2.1 Schematic view of the pulse laser deposition system. ........................................................ 35
Figure 2.2 Schematic view of e-beam evaporator. ................................................................................ 39
Figure 2.3 Schematic views of the main basic requirements for XPS system. ..................................... 40
Figure 2.4 Schematic view of photon induced electron emission (photoemission) in XPS (Carbon
atom). .................................................................................................................................. 41
Figure 2.5 Schematic view of a transmission electron microscope....................................................... 45

Figure 3.1 (a) Si 2p core-level; (b) O 1s core-level; (c) Hf 4f core-level XPS spectra at different stages
of HfO2 deposition on SiO2-covered silicon. ...................................................................... 55
Figure 3.2 TEM image of 8.75 nm HfO2 film on silicon, free of underlying amorphous SiO2. ........... 57
Figure 3.3 XPS depth profile for 8.75 nm HfO2 film on silicon, the sputtering time of 30 s for each
level. (a) Si 2p; (b) Hf 4f; (c) O 1s core-level spectra. ........................................................ 59
Figure 3.4 Si 2p core-level spectra of ~4 nm as-deposited HfO2 film. ................................................. 62
Figure 3.5 Si 2p core-level spectra of ~4 nm as-deposited HfO2 film. ................................................. 62
Figure 3.6 Cross-sectional HRTEM image of ~4 nm as-deposited HfO2 film. ..................................... 63
Figure 3.7 (a) Si 2p (b) Hf 4f core-level spectra of ~4 nm as-deposited HfO2 film and the films with
rapid thermal annealing at different temperatures. .............................................................. 65
Figure 3.8 Cross-sectional HRTEM images of HfO2 film with different rapid thermal annealing, (a)
500ºC; (b) 700ºC; (c) 900ºC; (d) 1000ºC in N2 for 10 s. The thicknesses of interface layers

vii


List of Figures
were labeled. ....................................................................................................................... 66
Figure 3.9 Capacitance-voltage characteristics of ~4 nm as-deposited HfO2 film and films with rapid
thermal annealing at different temperature.......................................................................... 67
Figure 3.10 EOT and effective dielectric constant for Al/HfO2/Si capacitors as a function of annealing
temperature.......................................................................................................................... 69
Figure 3.11 Current-voltage characteristics of ~4 nm as-deposited HfO2 film and films with rapid
thermal annealing at different temperature.......................................................................... 70
Figure 4.1 Si 2p, Hf 4f, Al 2p and O 1s XPS depth profiling spectra of 10.0 nm HAO film before (a)
and after (b) RTA on p-type Si (100) substrate.................................................................... 80
Figure 4.2 SIMS analysis of Hf-Al-O film before RTA (a) and after RTA (b). (Analysis parameters: Ga
Gun. Energy: 25 KeV. Current: 3.00 pA. Area: 49.8ì49.8 àm2. Sputter parameters: Ar
Gun. Energy: 0.50 KeV. Current: 3.00 nA. Area: 150ì150 àm2. )...................................... 81
Figure 4.3 HRTEM images of 10.0 nm HAO film before RTA (a), and after RTA (b). Islands of Hf

silicide are formed from interface reaction, and obviously reduced after RTA. RTA
temperature is 1000ºC in N2 for 10 s. The island is indicated by the circle in white. ......... 84
Figure 4.4 Capacitance-voltage and current-voltage characteristics of 10.0 nm HAO film before RTA
(a) and after RTA (b). The driving frequency is 100 kHz. The equivalent oxide thickness is
1.7 nm with dielectric constant at ~22.5.............................................................................. 87
Figure 4.5 Flow chart showing the procedure of the measurement and stressing cycles in the
developed program. ............................................................................................................. 89
Figure 4.6 Schematic diagrams showing the setup for the p-substrate capacitor biased in the (a)
inversion and (b) accumulation mode. ................................................................................ 89
Figure 4.7 Energy band diagram of a capacitor when stressed in the (a) inversion and (b) accumulation
mode.................................................................................................................................... 90
Figure 4.8 Constant voltage stress induced at accumulation. (a) C-V curve, (b) I-V curve. (Stress
condition: 10 cycles at -0.01 mA followed by another 10 cycles at -1 mA). No major
changes in C-V and I-V curves after 10 cycles stress. ........................................................ 92
Figure 4.9 (a) Frequency dependence of C-V properties, the diameter of electrode is 200 µm. (b) The
leakage current density of the HAO film. ........................................................................... 94
Figure 5.1 Band alignments at HfO2/Si interface................................................................................ 101
Figure 5.2 The valence-band spectra of bulk silicon and HfO2/Si system (left).The Si 2p core-level
spectra of HfO2/Si system (right). ..................................................................................... 103
Figure 5.3 The valence-band and Hf 4f core-level spectra of HfO2/Si system.................................... 104
Figure 5.4 The Hf 4f spectra of HfO2/Si, HfO2/Si0.75Ge0.25 and HfO2/Ge interfaces. ......................... 105
Figure 5.5 The valence-band and Si 2p spectra of Si without and with HfO2 overlayer. .................... 107

viii


List of Figures
Figure 5.6 The valence-band and Si 2p spectra of Si0.75Ge0.25 without and with HfO2 overlayer. ...... 108
Figure 5.7 The valence-band and Ge 3p spectra of Ge without and with HfO2 overlayer. ................. 109
Figure 5.8 The Δ Gibbs free energy calculation of Co and HfO2 reaction. ......................................... 112

Figure 5.9 Hf 4f (a) and Co 2p (b) core-level XPS spectra at different Co deposition time. .............. 113
Figure 5.10 Co 2p3/2 (a) and Co 2p1/2 (b) core-level XPS spectra at the first 5 minutes deposition.... 113
Figure 5.11 Co 2p3/2 and Hf 4f relative area ratio as a function of Co deposition time....................... 114
Figure 5.12 (a) Valence-band spectra for HfO2; (b) Hf 4f core-level spectra for HfO2; (c) Valence-band
spectra for 20 Å Co/HfO2; (d) Hf 4f core-level spectra for Co/HfO2................................ 115
Figure 5.13 The Ru 3d core-level XPS spectra of RuOx/HfO2/Si system under different oxidation-state.
........................................................................................................................................... 118
Figure 5.14 The valence-band and Hf 4f core-level spectra of RuOx/HfO2/Si system........................ 120
Figure 5.15 The schematic view of band alignment at RuO2/HfO2 interface...................................... 120
Figure 6.1 Hf 4f and Si 2p core-level spectra for Ni/HfO2/n-Si stack as a function of Ni thickness (for
0.3, 0.6, 0.9, 1.3, 1.6, 1.9, and 2.5 nm Ni thickness). The shifts of the binding energy for Hf
4f 5/2 and Si 2p3/2 are indicated by discontinuity lines. ...................................................... 129
Figure 6.2 Valence-band and Ni 2p spectra of the Ni/HfO2/n-Si stack as a function of Ni thickness. For
the clean HfO2 surface, the VB edge is denoted at 3.80 eV. The zero of binding energy
corresponds to the Fermi level. ......................................................................................... 129
Figure 6.3 The Fermi level positions with respect to the valence-band maximum of HfO2 as a function
of Ni and Co coverage on HfO2/Si. The n-type SBHs for Ni and Co on HfO2 are given. 132
Figure 6.4 The band diagrams of Ni/HfO2 stacks. .............................................................................. 133
Figure 6.5 Electronic band structures for c-HfO2................................................................................ 136
Figure 6.6 Total (solid line) and atom-projected (dotted line: O atom; dot-dashed: Hf) density of states
(DOS) for c-HfO2. ............................................................................................................. 137
Figure 6.7 Relaxed interface structures for (a) 1L, (b) 2L, (c)3L, (d) 4L, and (e) 5L of Ni on HfO2(111)
surface. (Red atom: O; Deep blue: Ni; Light blue: Hf.) .................................................... 139
Figure 6.8 PDOS for Ni atoms in different layer (from surface to interface). The Fermi level is at
energy zero, denoted by the dotted line............................................................................. 141
Figure 6.9 PDOS for O atoms in different layer (from interface to surface). The Fermi level is at
energy zero, denoted by the dotted line............................................................................. 143
Figure 6.10 PDOS for the O atom in the bulk region (O-5), calculated by Gaussian- based method
(solid lines) and the tetrahedron method (the dotted lines). .............................................. 143
Figure 6.11 Atom-projected density of states (PDOS) for different atoms in 5L Ni/HfO2 interface

ix


List of Figures
supercell. O-bulk: oxygen atom in the central layer of HfO2; O-inter: oxygen atom at the
interface; Ni-bulk: Ni atom in the central layer of Ni thin film; Ni-inter: Ni atom at the
interface. Accurate PDOS for O-bulk was also shown in dotted line to determine the VB
edge of HfO2. The Fermi level is at energy zero. .............................................................. 144
Figure 6.12 Penetration of electronic density ρ (z ) of the gap states into the HfO2 for Ni/HfO2
interfaces. Position of the first layer of HfO2 (111) is set to z = 0 Å................................. 146
Figure 6.13 Calculation of vacuum work function for Ni(111) surface: (up) supercell (relaxed) for
Ni(111) surface with 11 layers of Ni and 15 Å of vacuum; (down) electrostatic potential
(ESP) for Ni(111) surface with the Fermi level (EF) at energy zero.................................. 147
Figure 6.14 Plane-averaged electrostatic potential (ESP, dotted line) along the interface normal for 5L
Ni/HfO2 interface supercell. The metal vacuum work function

φ

Φ

φ m,vac

, effective work

Φ

function m,eff , n(p)-type SBH n ( p ), HfO2 electron affinity χ , and the potential
drop ΔEvac across the vacuum were shown. The position zero is at the interface. Values in
the figure are in eV. ........................................................................................................... 148

x


List of Tables

LIST OF TABLES

Table 1.1 The dielectric constants and energy band gaps of various dielectric materials. .................... 11
Table 2.1 Reference binding energies (eV). .......................................................................................... 42
Table 4.1 Relationship of accumulation capacitance value with EOT .................................................. 91
Table 5.1 Band alignments at HfO2/Si, HfO2/Si0.75Ge0.25 and HfO2/Ge interfaces. ............................ 110
Table 6.1 Comparison of experimental valence-band alignments for Ni on different dielectrics. ...... 134
Table 6.2 The rumpling parameters (%) for Ni layers in different thickness (from 1L to 5L). The
number of layer was counted from the interface................................................................ 140
Table 6.3 Calculated SBHs for Ni/HfO2 interface with different thickness of Ni overlayer. .............. 144

xi


List of Publications

LIST OF PUBLICATIONS

1. Q. Li, Y. F. Dong, S. J. Wang, J. W. Chai, A. C. H. Huan, Y. P. Feng, and C. K.
Ong, ”Evolution of Schottky barrier heights at Ni/HfO2 interfaces”, APPLIED PHYSICS
LETTERS, 88 (22), 222102 (2006).
2. Q. Li, S. J. Wang, T. H. Ng, W. K. Chim, A. C. H. Huan, and C. K. Ong, “Highthermal-stability (HfO2)1-x (Al2O3)x film fabricated by dual-beam laser ablation”, THIN
SOLID FILMS, 504 (1-2), 45-49 (2006).
3. Q. Li, S. J. Wang, W. D. Wang, D. Z. Chi, A. C. H. Huan, and C. K. Ong, ”Growth

and characterization of UHV sputtering HfO2 film by plasma oxidation and low
temperature annealing”, JOURNAL OF ELECTROCERAMICS, 16 (4), 517-521 (2006).
4. Q. Li, S. J. Wang, K. B. Li, A. C. H. Huan, J. W. Chai, J. S. Pan, and C. K. Ong,
“Photoemission study of energy-band alignment for RuOx/HfO2/Si system”, APPLIED
PHYSICS LETTERS, 85 (25), 6155-6157 (2004).
5. Q. Li, S. J. Wang, P. C. Lim, J. W. Chai, A. C. H. Huan, and C. K. Ong, “The
decomposition mechanism of SiO2 with the deposition of oxygen-deficient M(Hf or
Zr)Ox films”, THIN SOLID FILMS, 462, 106-109 (2004).
6. S. J. Wang, A. C. H. Huan, Y. L. Foo, J. W. Chai, J. S. Pan, Q. Li, Y. F. Dong, Y. P.
Feng, and C. K. Ong, “Energy-band alignments at ZrO2/Si, SiGe, and Ge interfaces”
APPLIED PHYSICS LETTERS, 85 (19), 4418-4420 (2004).

xii


List of Publications

7. L. Yan, L. B. Kong, Q. Li, and C. K. Ong, “Amorphous (CeO2)0.67(Al2O3)0.33 high-k
gate

dielectric

thin

films

on

silicon”, SEMICONDUCTOR

SCIENCE

AND

TECHNOLOGY, 18, L39-L41 (2003).
8. S. J. Wang, P. C. Lim, A. C. H. Huan， C. L. Liu, J. W. Chai, S. Y. Chow, J. S. Pan, Q.
Li, and C. K. Ong, “Reaction of SiO2 with hafnium oxide in low oxygen pressure”,
APPLIED PHYSICS LETTERS, 82 (13), 2047-2049 (2003).

xiii


Chapter 1

Chapter 1 Introduction

1.1 Introduction
The semiconductor industry has made rapid technological development over past
forty years, which has enormous impact on our society and the global economy. The
success of the semiconductor industry relies on the continuous improvement of
performance and the cost reduction of integrated circuits, which is mainly achieved by
the shrinking of the device dimensions. Throughout the semiconductor industry, the
metal-oxide-semiconductor field effect transistor (MOSFET) is the most important device
for integrated circuits such as microprocessors and semiconductor memories, because of
its high performance, high speed, low static power, low fabrication cost and small size.
The rapid shrinking of dimension of the transistor makes exponential increase in the
number of transistors integrated on a chip and 25~30% cost reduction per year. The
scaling of transistors follows the famous Moore’s law over forty years, which predicts
that the number of components per chip doubles every eighteen months.1 Key elements
enabling the scaling of transistors are the use of thermally grown silicon dioxide (SiO2) as

gate dielectric and poly-silicon as gate electrode.
The thermally grown SiO2, which is so far used as gate dielectric employed to isolate
the transistor gate from the Si channel in MOS device, indeed offers remarkable physical
and resultant electrical properties in MOS processing. The amorphous SiO2 can be
1


Chapter 1

thermally grown on silicon and naturally forms a very stable interface with a low density
of intrinsic interface defects. The band gap of SiO2 is quite large (~9 eV), which offers
superior

electrical

isolation

properties.

In

addition,

SiO2

presents

excellent

thermodynamically and chemical stability, which is required by the annealing steps at

high temperatures (up to 1000ºC) in the fabrication process of transistors. In short, the
existence of the superb quality of thermally grown SiO2 offers the possibility of device
scaling and allowed the fabrication of properly working MOSFET’s with SiO2 gate
dielectric layers as thin as 1.5 nm.
However, as will be discussed in the following sections, further scaling of the SiO2
gate layer thickness below 1.5 nm is problematic.2,3 The first problem arising is that the
gate leakage current due to direct tunneling of electrons through the SiO2 will be high
(exceeding 1 A/cm2 at 1 V) when the thickness of the SiO2 layer is becoming so thin,
which will increase the circuit power dissipation to a unacceptable value.4 Therefore, an
alternative dielectric with high dielectric constant, high-k dielectric material, employed to
achieve the equivalent capacitance density with relatively thicker physical thickness is
required for the replacement of SiO2 for the high performance logic application and low
operating power logic applications in coming generations.5 Nevertheless, the excellent
electrical properties of SO2 present a significant challenge for any alternative gate
dielectric candidate without doubt.
Along with the replacement of SiO2 with the alternative gate dielectric, the dualdoped poly-silicon which is currently used as gate is desired to be replaced by the
metallic gate electrodes. The use of stable metallic gate electrodes is expected to solve the
issues of poly-silicon depletion effect and boron penetration as the further scaling of

2


Chapter 1

devices. In addition, since the instability of poly-silicon is expected on most high-k
dielectric materials, the use of stable metallic gate electrodes is required to solve the
integration problems when the gate dielectric material is replaced by high-k dielectric
materials.
In the following sections, a review of the scaling limits for SiO2 and current research
works on high dielectric constant dielectric materials and metal gate electrodes are given.

1.2 An overview of device scaling
Scaling of MOS device is the heart of growth of the semiconductor industry. The
industry’s demand for greater circuit functionality and performance at lower cost requires
a higher density of transistors on a wafer, which has mainly achieved by shrinking of the
transistor feature size. Reducing the length and width of channel can result in the increase
of the density of devices on the chip, while reducing the oxide thickness can improve the
device speed by increasing the drive current of the transistor.
The improved performance associated with the scaling of logic device dimensions can
be seen by considering a simple model for the drive current of a MOSFET.6 The drive
current can be written (gradual channel approximation) as

ID =

V
W
μCinv (VG − VT − D )VD
2
L

(1.1)

where W is the width of the transistor channel, L is the length of the transistor channel, µ
is the channel carrier mobility, Cinv is the capacitance density associated with the gate
dielectric when the underlying channel is in the inversion state, VG and VD are the

3


Chapter 1

voltages applied to the transistor gate and drain, respectively, and the threshold voltage is
given by VT.
Assuming constant mobility, a reduction in the channel length and/or an increase in
the gate dielectric capacitance is required to increase ID, which can be translated into
higher speed, greater circuit functionality and performance at lower cost.
For the gate capacitance, consider a parallel plate capacitance (ignoring quantum
mechanical and depletion effects from a Si substrate and gate),

C=

κε 0 A
t

(1.2)

where κ is the dielectric constant of the gate material (also refer to the relative
permittivity in this literature, for SiO2, κ = 3.9), ε0 is the permittivity of free space (ε0 =
8.85×10-3 fF/um), A is the area of the capacitance, and t is the thickness of the dielectric.
Obviously, a reduction in the thickness of gate dielectric is required in order to increase
the gate dielectric capacitance to improve the drive current.
Various scaling rules have been proposed including constant field scaling, constant
voltage scaling, quasi-constant voltage scaling and generalized scaling. In the commonly
used constant field scaling, the transistor’s linear dimensions as well as the operating
voltage are all scaled down by a factor of S (S<1), then the gate delay will reduce by a
factor of S and the power per transistor will reduce by S3.7
Over past several decades, device dimensions have shrunk drastically and will
continue according to the prediction of the International Technology Roadmap for
Semiconductors (ITRS) to maintain the growth rate of the semiconductor industry. In the
state-of-art technologies, the thickness of SiO2 layer is around 1.5 nm which is

approaching to the physical limitation of SiO2.

4


Chapter 1

1.3 Limitations for gate oxide (SiO2) scaling
Since the birth of the MOS device, the amorphous, thermally grown SiO2 employed
to isolate the transistor gate from the Si channel as a gate dielectric. SiO2 provides several
key advantages including thermodynamically and electrically stable, high quality Si-SiO2
interface as well as superior electrical isolation properties. To achieve higher device
performance, thinner gate dielectric is required, especially in the deep sub-micron regime.
The remarkable physical and electronic properties of SiO2 allow the rapid shrinking of
gate dielectric’s thickness with the increasing performance of devices. While thermal
SiO2 of 70 nm in thickness in 1977, today’s MOSFETs in production have gate oxides of
~1.5 nm. Since a mono-layer of SiO2 is about 3.5~4.0 Å, an oxide film of 1.5 nm consists
of only a few mono-layers of atoms. Muller et al. has clearly demonstrated that the
existence of a physical limit for SiO2 around 1.0-1.2 nm. It is found that the full band gap
of SiO2 is obtained only after 2 monolayers of SiO2.8 When the interface bond length is
included, this indicates that the thickness of 0.7-0.8 nm is required. These results set an
absolute physical thickness limit of SiO2 at 0.7 nm.9 One can imagine the difficulties of
continuing scaling in this ultra-thin regime. Besides the physical limitation mentioned,
continued scaling of SiO2 layer thickness is limited by several issues, including gate
leakage current, boron penetration, interfacial structure and reliability. The limitations for
gate oxide scaling will be discussed in this section.

1.3.1 Direct tunneling leakage current
The conductance of an insulating thin film is assumed to be zero in an ideal MOS
5

Chapter 1

structure. However, when electric filed or temperature is sufficient high, carrier
conductance occurs in the real insulators resulting in the tunneling process from gate
dielectric to Si channel.
While SiO2 provides us with the remarkable properties as the gate dielectric, the gate
leakage current increases exponentially as the oxide thickness scaled down. Figure 1.1
shows the gate current density as a function of gate voltage for MOS capacitors with
different SiO2 gate dielectric thickness. The unacceptable high leakage current arises
obviously with decreasing SiO2 thickness below 3.5 nm.10,11 The thermal oxide of
thickness less than 1.5 nm has a gate leakage current density more than 1 A/cm2 at 1 V.
The high leakage current will cause problems of excessive power consumption and
abnormal device characteristics. Depending on the applications, a leakage current density
of 1 A/cm2 is regarded as the maximum tolerable gate leakage current density value from
the power consumption viewpoint. However, further down scaling increases the leakage
current densities (>1 A/cm2) and renders the devices inoperative, setting a fundamental
constraint on gate oxide scaling.
As a matter of fact, the quantum mechanical direct-tunneling process dominates the
flow of charge carriers in the ultrathin SiO2 gate layers thickness typically below 3 nm,
which results in a large increase of the leakage current. Figure 1.2 presents the quantum
mechanical tunneling mechanism, the so-called direct tunneling process. In this
mechanism, the tunneling charge carriers directly flow through the trapezoidal energy
barrier.12 The direct tunneling is a very strong function of the width of the barrier electron
tunnels through (oxide thickness in MOS devices) and has smaller dependence on the
gate voltage (Vg). It can not be easily suppressed or eliminated and is believed to be the

6

Chapter 1

ultimate limitation on gate oxide scaling for MOS technology.13

Figure 1.1 Gate current density as a function of gate voltage for MOS capacitors with
different SiO2 gate dielectric thickness.10,11

e

Direct Tunneling

Si/SiO2/poly-Si
Figure 1.2 Schematic energy band diagram of direct tunneling of electron from the Si
substrate to the gate in a turned on n-MOSFET (Si/SiO2/poly-Si gate structure).

7


Chapter 1

1.3.2 Boron penetration
There are other limiting factors regarding to SiO2 gate oxide scaling. Most of the
advanced CMOS process uses dual gate technology, in which p+ poly-silicon gate
electrode is used in the p-channel MOSFET and n+ poly-silicon gate electrode is used in
the n-channel MOSFET for its surface channel operation. In the p-channel MOSFET, the

p+ poly-silicon gate is fabricated by implanting B or BF2 species followed by the
activation of dopants. In general, a relatively thick SiO2 can be a barrier for the B
penetration. However, the boron easily diffuses through oxide during thermal cycles

when the oxide thickness is sub-20 Å. When the boron penetration occurs, the device
suffers shift in threshold voltage, increase in the sub-threshold leakage current, reduction
in the channel mobility as well as oxide reliability degradation with the increasing of
charge trapping.14-16 The phenomena of boron penetration becomes more severe while a
thinner oxide and a higher density of active dopants are required for the continued scaling
of MOS devices.

1.3.3 Uniformity and reliability
In addition to the high leakage current and boron penetration issues with the scaling
of SiO2 thickness, an equally important issue is uniformity and reliability aspects of oxide.
While the thickness of oxide is down to 2 nm, it is a formidable task for manufacturing
such a thin dielectric with good uniformity across the wafer. In addition to that, the oxide
reliability which is defined by the defect related breakdown becomes a major problem.
Degraeve et al. first reported a fundamental mechanism for oxide breakdown in the

8


Chapter 1

ultrathin SiO2 regime as a percolation model, which points out that the oxide breakdown
comes out from a complete path built up by many defects within the SiO2 layer after a
certain amount of stress.17,18 Both charge-to-breakdown (Qbd) and time-to-breakdown
(Tbd) data show that the thinner oxide has higher breakdown field strengths inside. It is
clear that SiO2 is approaching its physical intrinsic limitations.
Despite many excellent properties of SiO2, it must be replaced because of the several
limitations as discussed above. The concerns regarding high leakage currents, boron
penetration and reliability of ultrathin SiO2, as early as 10 years ago, have led to
incorporate nitrogen in to SiO2 (such as oxynitrides and oxide/nitride stacks) as near-term
gate dielectric alternatives. Indeed, the addition of N to SiO2 greatly reduces the leakage

current and boron penetration with better reliability. However, the scaling with
oxynitrides and oxide/nitride stacks appears to be limited to teq = ~13 Å by the effects of
gate leakage, reliability and mobility degradation.19
It is necessary to replace the traditional SiO2 with a physically thicker layer of oxides
of higher dielectric constant (k). Intensive research is underway to develop oxides into
new high quality electronic materials.

1.4 Alternative high-k gate dielectrics candidates and
materials properties considerations
The industry’s demand for greater integrated circuit functionality and performance at
lower cost requires a higher density of transistors on a wafer. However, further scaling of

9


Chapter 1

gate dielectric of SiO2 thickness meets the fundamental limitations, which is not easy to
be suppressed by merely improving oxide’s process technology.
From an electrical point of view, considering the MOS structure as a parallel plate
capacitor (refer to equation 1.2), an alternative way of increasing the capacitance is to use
a dielectric with a higher relative dielectric constant (k) than SiO2 instead of decreasing
the thickness of SiO2. For example, a dielectric with a relative permittivity of 16 affords a
physical thickness of 40 Å to achieve the equivalent capacitance of teq = 10 Å. Continued
scaling of CMOS device is demanding a gate dielectric with a higher permittivity (k) than
that of SiO2 to achieve lower electrical thickness (or higher gate capacitance) with a
larger physical thickness.
To find a suitable high-k material for gate dielectric applications is clearly essential.
The choice of materials for this application requires two sets of properties. One set
encompasses fundamental materials properties that include permittivity, film morphology,

barrier height, and stability in direct contact with Si. The other set includes interface
quality, gate compatibility, process compatibility and reliability. Only the candidate
reaching both of these criteria can be the future gate dielectric.
The first requirement of high-k material is that the oxide should have k over 10 (k for
SiO2 is 3.9 and Silicon Nitride is around 7). In general, the atomic (or ionic) radius
increases with the increasing of the atomic number of the metal, leading to a higher
dielectric constant.20 And for high-k materials, the dielectric constant value and band gap
generally exhibit an inverse relationship. From the empirical relationship between energy
band gap (Eg) and the dielectric constant (ε) established by Duffy for simple elemental
materials or binary compounds:21

10


Chapter 1

⎡ 3 ⎤
E g = 20⎢
⎣ε + 2 ⎥
⎦

2

(1.3)

This equation indicates that a material having large dielectric constant tends to have a
narrower band gap. Although Duffy’s equation can not describe the dielectric constant of
thin films accurately, it dose show the trend that energy band gap decreases with the
increase of the dielectric constant. Therefore, in selecting a gate dielectric, the trade off
should be made between dielectric constant and band gap. Table 1.1 summarized the

dielectric constants and energy band gaps of various dielectric materials.22

Table 1.1 The dielectric constants and energy band gaps of various dielectric materials.
k

Eg (eV)

SiO2

3.9

8.9

Si3N4

7

5.1

Al2O3

9

8.7

Y2O3

15

5.6

La2O3

30

4.3

Ta2O5

26

4.5

TiO2

80

3.5

HfO2

25

5.7

ZrO2

25

5.8-7.8

Electrical properties of the high-k gate dielectrics are also a critical point to consider
for use in CMOS devices. Generally, a large band gap (Eg) corresponds to a large
conduction-band offset (ΔEc). The high-k dielectric must act as an insulator which
requires that the barrier height at each band must be over 1 eV in order to inhibit
11


Chapter 1

conduction by Schottky emission of electrons or holes from Si into the oxide bands. So
the required permittivity must be balanced against the band gap for the tunneling process.
In practice, the conduction-band offset is usually smaller than the valence-band offset
which requires the choice of dielectric to those with band gaps over 5 eV. The
calculations by Robertson and Chen including many high-k dielectrics show that ΔEc is
~2.3-2.8 eV for Al2O3 and Y2O3, and ΔEc is ~1.5 eV for ZrO2 and ZrSiO4 as shown in Fig.
1.3.18,23

Figure 1.3 Band offset calculations for a number of potential high-k gate dielectric
materials.23
In most cases, the interface with Si plays an important role in determining the overall
electrical properties of MOS devices. Intensive studies of high-k materials show that they
easily react with Si and form an undesirable interfacial layer. It is important to understand

12