Alternative gate dielectrics and application in nanocrystal memory

ALTERNATIVE GATE DIELECTRICS
AND
APPLICATION IN NANOCRYSTAL MEMORY









NG TSU HAU
(B.Eng.(Hons.)and M.Eng., NUS)









A THESIS SUBMITTED

FOR THE DEGREE OF DOCTOR OF PHILOSOPHY IN
ENGINEERING

DEPARTMENT OF ELECTRICAL AND COMPUTER

ENGINEERING

NATIONAL UNIVERSITY OF SINGAPORE

2005


Acknowledgement

I would like to thank my thesis supervisor, Associate Professor Chim Wai Kin
and Associate Professor Choi Wee Kiong, for giving me the opportunity to undertake this
interesting research topic and I am also very grateful for their guidance throughout my
candidature.

I would like to thank Yan Ny, Wei Yip and Mr. Joo Moon Sig for their assistance
rendered during the fabrication of the devices in Silicon Nano Device Laboratory
(SNDL). I am also thankful to Mr. Walter Lim, Lee Wee, Vincent Ho and Eric for their
discussions and assistance while working in Microelectronics laboratory. I would like to
thank Dr. Wang Shi Jie as well as Li Qin for some of the collaborative work.

In Center for Integrated Circuits Failure Analysis and Reliability (CICFAR), I
would like to thank Mrs Ho Chiow Mooi and Thiam Peng for their prompt supply of
equipment and Lei Yong for the occasional discussions. Appreciation also goes to Chee
Keong, Zheng Jianxin, Dr. Wong Wai Kin, Yong Yu, Osterberg Mans Jhan Bertil, Tiet
Eng, Xin Hua, Li Qi, Gu Hua, Soon Leng, Soon Huat, Kuan Song, Chow Khim as well as
many others who have made my stay in NUS an enriching experience.

I would like to thank all my ex-colleagues in Advanced Micro Devices (AMD),
especially Dr. Mai Zhi Hong, for the friendship as well as their strong encouragement for
my embarkation on this challenge.

i


Title: Alternative Gate Dielectrics and Application in Nanocrystal Memory

TABLE OF CONTENTS
Pages
Acknowledgement i
Table of Contents ii
Summary vii
List of Tables viii
List of Figures ix

Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Research Objectives 4
1.4 Organization of Thesis 5
References 7

Chapter 2 Literature Review on High Dielectric Constant 9
Materials and Nanocrystal Memory
2.1 Literature Review on High Dielectric Constant (high-κ) Materials 9
2.1.1 Limitations of Silicon Dioxide (SiO
2
) as Gate Dielectric Material 9
2.1.2 Employment of High Dielectric Constant Material as a Solution 12
to Limitations of Silicon Dioxide (SiO
2
)

2.1.3 Criteria for Selection of Alternative Gate Dielectrics and 14
Potential Candidates
2.2 Introduction to Current Nonvolatile Memory Devices and their 17
Limitations
ii


2.2.1 Basic Programming Mechanisms in Non-Volatile Memory 19
Devices
2.2.1.1 Programming by Fowler-Nordheim (F-N) Tunneling 19
2.2.1.2 Programming by Hot-carrier Injection (HCI) 21
2.2.2 Basic Erasing Mechanisms Non-Volatile Memory Devices 23
2.1.2.1 Erasing by UV radiation 24
2.1.2.2 Erasing by F-N Tunneling 24
2.3 Candidates to Address the Limitations of FLOTOX/Flash Memory 26
Devices
2.3.1 MNOS Memory 26
2.3.2 SONOS Memory 27
2.3.3 Nanocrystal Memory Devices 30
2.3.2.1 Methods to Fabricate Nanocrystal Memory Devices 31
2.3.4 Other Emerging Memory Devices 35
2.4 Approaches to Improve the Performance of Nanocrystal Memory 37
2.4.1 Tunnel Oxide Thickness Reduction and its Related Issues 37
2.4.1.1 Approach to Address Limitations of Thin Tunnel Oxide 38
2.4.2 Electric Field Coupling Enhancement 39
2.4.2.1 Capping Layer Thickness Reduction 39
2.4.2.2 High-κ Material as Alternative Capping Material 39
2.5 Summary 40
References 42

Chapter 3 Fabrication and Characterization of High-Dielectric 51
Constant Materials for Potential Applications in
Nanocrystal Memory Devices
3.1 Fabrication and Characterization of Zirconium Dioxide (ZrO
2
) 51
3.1.1 Device Fabrication 51
3.1.2 Device Characterization 52
i
ii


3.1.2.1 Structural Characterization 52
3.1.2.2 Electrical Characterization 54
3.1.2.3 Quantum-Mechanical Simulation of C-V curves 57
3.1.3 Charge Transport Mechanisms 62
3.2 Fabrication and Characterization of Hafnium Dioxide 68
3.2.1 Fabrication of HfO
2
Film 68
3.2.2 XPS Characterization of HfO
2
Film 69
3.2.3 Electrical Characterization of the HfO
2
Film 70
3.3 Investigation of Crystallization Temperature of Hafnium Dioxide and 71
Hafnium Aluminum Oxide
3.4 Summary 74
References 75

Chapter 4 Nanocrystal Memory Devices with High Dielectric Constant 79
Material as Tunnel Dielectric
4.1 Fabrication and Characterization of Nanocrystal Memory with Hafnium 79
Dioxide as Tunnel Dielectric (EOT = 4.8nm)
4.1.1 Charge Storage Studies 81
4.1.2 Charging and Discharging Time Studies 84
4.1.3 Charge Retention Studies 85
4.2 Further Scaling of Hafnium Dioxide Tunnel Dielectric to EOT of 87
1.9nm and Performance Characterization
4.2.1 Structural Characterization 88
4.2.2 Charge Storage 91
4.2.3 Charge Retention Studies 93
4.3 Summary 94
References 95

i
v


Chapter 5 High Dielectric Constant Material as Capping 97
Layer for Improved Electric Field Coupling in
Nanocrystal Memory Devices

5.1 Experimental Details 97
5.2 Comparison of Performance for Devices with Different Types of 98
Capping Layer
5.2.1 Charge Storage Analysis 98
5.2.2 Charge Retention Capability Studies 105
5.3 Conductance Measurement 109

5.3.1 Motivation for Applying Conductance Measurement to the 109
Study of Nanocrystal Devices
5.3.2 Theory and Model of Conductance Measurement 110
5.3.3 Correlation between Conductance Peak Location and Flatband 117
Voltage
5.3.4 Conductance Measurement on Nanocrystal Capacitor 120
Devices with Different Types of Capping Layer
5.3.5 Estimation of Nanocrystal Density Based on 125
Conductance-Voltage (G-V) Data
5.4 Summary 129
References 131

Chapter 6 Investigation of Charge Storage Mechanism in Germanium 133
Nanocrystals Using Nanocrystal Transistor Devices
6.1 Fabrication Procedure of Nanocrystal Memory Transistor 134
6.2 Electrical Characterization of Nanocrystal Memory Transistor 135
6.2.1 Transient Characteristics of the Transistor Based Nanocrystal 139
Memory Structures
6.2.2 Endurance Characteristics 141
6.2.2.1 Write/Erase Endurance Testing 142
6.2.2.2 Charge Retention Testing 143
6.3 Charge Storage and Discharge Mechanisms in Nanocrystal Flash 145
v


Memories
6.3.1 Review of Previous Work on Extraction of Trap Energy Level 146
6.3.2 Extraction of Trap Energy Level from Germanium 152
Nanocrystal Transistors
6.3.3 Possible Origin of the Extracted Trap Level 155

6.4 Alternative Method for Extraction of Trap Energy Level 156
6.5 Trap Level Enginnering 160
6.6 Summary 162
References 164

Chapter 7: Conclusion 167
7.1 Summary 167
7.2 Technology Perspective 170
7.3 Recommendation for Future Work 171
References 176
List of Publications 181




vi


Summary
Nanocrystal memory has attracted much attention because it has better scalability
than the conventional floating gate Flash memory. In this work, the performance of
germanium (Ge) nanocrystal memory structures, employing high dielectric constant
(high-κ) materials to replace the tunnel oxide and capping oxide (control oxide) layers,
was investigated. It was found that faster charging rate and better charge retention
performance could be obtained with a high-κ tunnel dielectric layer of equivalent oxide
thickness (EOT) to that of silicon dioxide. Even at an EOT of 1.9 nm, the high-κ layer is
still physically thick enough to prevent Ge penetration into the substrate during high
temperature annealing. If Ge penetration were to occur, Ge nanocrystals will not be able
to form and the device will not show any charge storage effect. The replacement of the
capping oxide layer with a high-κ material of similar physical thickness as that of a

silicon dioxide capping layer will result in better gate electric field coupling. The effect of
gate electric field coupling on the conductance-voltage (G-V) characteristics of different
trilayer nanocrystal memory structures was also investigated. It was found that the
distinctive G-V characteristics due to nanocrystals could be separated and identified from
the interface traps provided the memory structure has sufficiently high electric field
coupling from the gate applied voltage. A method for calculating the density of
nanocrystals based on the G-V data was also discussed. Finally, investigation of trap
energy levels in Ge nanocrystal memory structures and their effect on the device charging
and discharging kinetics were also carried out by monitoring the transient drain current
characteristics.
vii


List of Tables
Pages
Table 2.1 List of projected transistor parameter requirements for future
devices.

10
Table 2.2 Characteristics and properties of some potential high-κ
dielectric material. SiO
2
is also listed for comparison

15
Table 2.3 A summary of the various nanocrystal fabrication techniques.

33
Table 4.1 The configurations of the trilayer structures used for
comparison of device performance.

80
Table 4.2 The configurations of the trilayer structures (with tunnel
dielectric thickness further reduced) used for comparison of
device performance.

90
Table 5.1 The configurations of the trilayer structures (with different
capping material/thickness) used for comparison of device
performance.

98
Table 5.2 A summary of the structures of the fabricated devices and
comparison of their charge storage capability.

102
Table 5.3 Description of the devices used for G-V study. 121

viii


List of Figures
Pages
Figure 2.1 Extrapolated gate oxide scaling trend for recent CMOS
technologies.

11
Figure 2.2 Schematic figure of a FLOTOX EEPROM cell.

18

Figure 2.3 Energy band diagram of a floating gate memory during
programming by F-N tunneling.

19
Figure 2.4 Schematic diagram showing uniform F-N tunneling of
electrons from the substrate to the floating gate during
programming of a Flash memory.


20
Figure 2.5 Energy band diagram of a floating gate memory during
programming by hot-electron injection.

22
Figure 2.6 Schematic diagram showing hot-electron injection mechanism
for programming in a NVM.

23
Figure 2.7 Band diagram describing the erasure of stored charge by UV
radiation.

24
Figure 2.8 Energy band diagram of a floating gate memory during
erasing by F-N tunneling.

25
Figure 2.9 Schematic diagrams showing two methods to erase a Flash
EEPROM: (a) uniform F-N tunneling erase and (b) drain-side
tunneling erase.

25
Figure 2.10 Schematic diagram of a MNOS memory structure 27
Figure 2.11 Schematic diagram of a SONOS memory structure.

28
Figure 2.12 Capacitive model of the gate dielectric stack for SONOS-type
device. CG denotes the control gate, “cap” denotes the
capping (control) oxide layer, CS denotes the charge storage
layer and tun_ox denotes the tunnel oxide.

29
Figure 2.13 Schematic diagram of a nanocrystal memory structure. 30
ix


Figure 2.14 Schematic diagram of a Ovonic Unified Memory (OUM)
device.

35
Figure 3.1 TEM images of the fabricated Al/ZrO
2
/n-Si MIS devices at
(a) a low leakage site and (b) a high leakage site.

53
Figure 3.2 Structural characteristics of the fabricated Al/ZrO
2
/n-Si MIS
devices: (a) The XRD spectra of the ZrO
2

film for wafer
substrate temperatures of 300
o
C and 400
o
C during sputtering.
The (b) Zr3d and (c) O1s XPS spectra of the ZrO
2
film for
wafer substrate temperatures of 350
o
C and 400
o
C during
reactive sputtering.

54
Figure 3.3 Electrical characteristics of the Al/ZrO
2
/n-Si MIS devices: (a)
C-V and (b) I-V characteristics for high leakage and low
leakage devices.

55
Figure 3.4 Quantum-mechanical C-V modeling (solid and dotted lines)
of typical (a) low leakage and (b) high leakage devices
compared with experimental measurements (open circles)

57
Figure 3.5 Plot showing the electric fields in both the bulk ZrO

2
and
interfacial layer at the various gate voltages.

63
Figure 3.6 Band diagrams describing the current conduction processes in
Metal-Insulator-Semiconductor devices. (a) shows the
Schottky emission mechanism and (b) shows the F-P
emission mechanism.

65
Figure 3.7 The measured and calculated (fitted) J
g
-F characteristics, for
values of F in the (a) interfacial layer and (b) bulk ZrO
2
of a
typical low leakage Al/ZrO
2
/n-Si MIS device in the low gate
bias region.

66
Figure 3.8 TEM picture of the high-κ (HfO
2
) film. 69
Figure 3.9 (a) Hf4f and (b) O1s XPS spectra of the deposited and
annealed HfO
2
film.

70
Figure 3.10 (a) C-V and (b) I-V characteristics of a typical MIS device
with HfO
2
as the insulator layer.

71
x



Figure 3.11 XRD spectra of pure HfO
2
after annealing at 600
o
C and
1000
o
C and HfO
2
doped with Al after annealing at 800
o
C and
1000
o
C. The crystallization temperature of HfO
2
could be
raised to 1000

o
C when it is doped with Al.

73
Figure 4.1 Cross-sectional HRTEM image of the nanocrystal memory
device HK4-8.

81
Figure 4.2 C-V characteristics of (a) Device HK4-8 and (b) Device
RTO5 showing clock-wise hysteresis. The gate voltage sweep
range was gradually increased from -2V<V
g
<2V to
-16<V
g
<16V.

82
Figure 4.3 A plot summarizing the charge storage capability with respect
to the gate voltage sweep range for Device RTO5 and Device
HK4_8.

83
Figure 4.4 (a) C-V characteristics of device HK4-8. The gate voltage
sweep range was gradually increased till the occurrence of
device breakdown (beyond the -26<V
g
<26V sweep range).
(b) Concentration of negative and positive trapped charges
versus gate bias for device HK4-8.

84
Figure 4.5

Study of Charging and discharging rate of the two devices.
(a) shows the charging characteristics of the devices when a
gate voltage of 12V is applied (b) shows the discharging
characteristics when the gate voltage is abruptly switched to
-12V after charging.

85
Figure 4.6 Retention characteristics of trilayer insulator structure
nanocrystal memory devices for different types of tunnel
dielectric. Both HfO
2
and SiO
2
tunnel dielectric have the
same equivalent-oxide-thickness of 5nm. The middle and cap
layer thickness of both devices are the same.

87
Figure 4.7 Cross-sectional TEM image of (a) device RTO2-5 and (b)
device HK1-9. Note the absence of Ge nanocrytals and the
uneven RTO-Si interface caused by the Ge penetration in
device RTO2-5.

88
xi

Figure 4.8 SIMS result (of device HK1-9) showing that Ge does not
penetrate and diffuse significantly into the silicon substrate.
The HfO
2
layer provides a good blocking platform for the
formation of Ge nanocrystals.

90
Figure 4.9 High frequency C-V characteristics of (a) device HK1-9 and
(b) device RTO5. The quasi-neutral C-V curves for the
respective devices were obtained by restricting the gate bias
to a very narrow range to minimize charging up of the Ge
nanocrystals.

91
Figure 4.10 Retention characteristics of devices RTO5 and HK1-9: (a)
Comparison of retention time versus discharge bias of both
devices and (b) Some representative normalized C-t curves
during discharge of devices RTO5 and HK1-9 at a constant
discharge voltage of either 0 V or –3 V as indicated.

93
Figure 5.1 Forward/reverse C-V characteristics of the three devices for
various sweep ranges. C-V Characteristics of (a) Device A
(device with 20nm SiO
2
capping layer), (b) Device B (device
with 20nm HfAlO capping layer) and (c) Device C (device

with 10nm HfAlO capping layer). The capacitor area is
4x10
-4
cm
2
for the three devices. A holding time of 240s is
applied before the commencement of each gate voltage
sweep.

99
Figure 5.2 Plot of flatband voltage shift with respect to the gate voltage
sweep range for Device A and Device B. The area of the
device is 4x10
-4
cm
2
. V
FB
and V
FBQN
denote the flatband
voltages of the charged and uncharged (quasi-neutral) device,
respectively.

101
Figure 5.3 Plot of charge storage with respect to the gate voltage sweep
range for Device A and Device B.

102
Figure 5.4 Plot of charge storage with respect to the gate voltage sweep

range for Device A and Device B as well as devices
fabricated in our earlier work (Device HK4-8 and Device
HK1-9).

104
xii



Figure 5.5 Charge retention characteristics of Device A (device with
20nm SiO
2
capping layer) and Device B (device with 20nm
HfAlO capping layer). Discharge characteristics of (a)
Device A and (b) Device B.

105
Figure 5.6 Plot of retention time over the discharge voltage range for
Device A and Device B.

106
Figure 5.7 Schematic diagram describing the polarization effect in the
high-κ capping layer during charging. (a) shows the
polarization of the high-κ material when +5V is applied to the
gate during charging. (b) shows the positive charge in the
dipole of the polarized high-κ material preventing some
electrons (stored in the nanocrystals) from tunneling back to
the Si substrate easily, when the gate voltage is abruptly
switched to -5V during discharging. The nanocrystals that are
still stored with electrons are represented by the shaded

nanocrystals in (b).

108
Figure 5.8 Energy band diagram showing the interface traps (a) at
equilibrium and (b) in the positive half cycle of the AC signal
applied at the gate electrode.

111
Figure 5.9 Energy band diagram showing the interface traps (a) at the
positive half cycle of the AC signal and (b) immediately
followed by negative half of the AC signal.

112
Figure 5.10 Schematic diagram explaining the derivation of the
conductance parameters. (a) shows the experimental setup
for a typical LCR meter to acquire the capacitance and
conductance data and (b) shows the schematic for obtaining
the parameters for Nicollian’s conductance model.

113
Figure 5.11 Schematic diagrams illustrating the procedure for correction
of series resistance. (a) shows the original schematic
representation whereas (b) shows the simplified diagram
when the MOS capacitor is biased into the strong
accumulation region.

114
xiii

Figure 5.12 Typical C-V and G-V characteristics obtained by sweeping
gate voltage back and forth between -5V and 1V. The peak
position in the G-V characteristics is around the flatband
condition [5].

117
Figure 5.13 High frequency C-V and G-V characteristics of the trilayer
structure nanocrystal memory device B. (a) Forward and
reverse sweeps C-V curves showing counter-clockwise
hysteresis with the gate voltage (V
g
) sweep increasing from –2
V < V
g
< 2 V to -10 V < V
g
< 10 V. (b) The corresponding
G-V characteristics during the respective gate voltage sweep.

118
Figure 5.14 Plot of the gate voltage corresponding to the conductance
peak (V
PEAK
) and flatband voltage V
FB
(from C-V plot) versus
the gate voltage sweep range.

119

Figure 5.15 Schematic diagram showing the components for the extracted
parallel conductance. (a) shows the extracted parallel
conductance, G
p
, which is contributed by (b) the nanocrystal
conductance G
nc
branch, and the interface trap G
it
branch.

120
Figure 5.16 Parallel conductance characteristics, (G
p
/ω)/A on a log scale
plotted against gate voltage during forward (increasing) gate
voltage sweep after biasing at a gate voltage of -5 V for 240 s,
for the three devices: Device Control (without nanocrystals),
Nanocrystal memory device A (with 20-nm thick SiO
2
cap
layer) and Nanocrystal memory device B (with 20-nm thick
HfAlO cap layer). Note that the 50 kHz and 100 kHz
(G
p
/ω)/A data for device A are smaller than 10
-9
F cm
2
and are

not shown on the plot.

122
Figure 5.17 Frequency dependent parallel conductance characteristics,
(G
p
/ω)/A plotted on a linear scale against gate voltage, of
nanocrystal memory device A (with 20-nm thick SiO
2
cap
layer): (a) During forward (increasing) gate voltage sweep
after biasing at a gate voltage of -5 V for 240 s, and (b)
During reverse (decreasing) gate voltage sweep after biasing
at a gate voltage of 5 V for 240 s.

124
xiv



Figure 5.18 Schematic diagram of the conductance model for a typical
nanocrystal memory device structure. When the effect of
nanocrystals is more dominant than that of interface traps, the
model on the left could be further simplified to that on the
right.

126
Figure 5.19 Schematic diagram illustrating the approach for the
calculation of nanocrystal density.

127
Figure 6.1 Schematic diagram of the process flow for Ge nanocrystal
memory transistor device fabrication.

135
Figure 6.2 Schematic cross-sectional structure of fabricated device and
HRTEM image of the HfAlO/nc-Ge/SiO
2
transistor memory
structure.

136
Figure 6.3 Electrical characteristics of the transistor memory device: (a)
I
d
-V
d
and (b) I
d
-V
g
characteristics. The threshold voltage is
about 2.7V.

137
Figure 6.4

I
d
-V

g
characteristics of the nanocrystal transistor memory
device obtained by first sweeping the gate voltage positively
in the forward direction followed by a reverse sweep
direction. The hysteresis loop formed by each pair of
forward/reverse curves is indicative of the charge storage
capability of the device.

138
Figure 6.5

A plot of the threshold voltage shift with respect to the total
time duration for accumulated number of pulses. It takes
about 59 pulses of 10V to result in a threshold voltage shift of
1V.

141
Figure 6.6 Data endurance characteristics. ±10V, 100ms pulses are
applied for write/erase cycling of the nanocrystal transistor
memory device. Write and erase conditions were (10V,
100ms) and (–10V, 100ms), respectively.

142
xv



Figure 6.7 Various I
d
versus V

g
characteristics of the transistor memory
device at the specified time durations after application of a
write pulse of 10V for 200ms.

143
Figure 6.8 Room temperature charge retention characteristics of the
nanocrystal transistor memory after Write and Erase pulses of
(8V, 9V and 10V for 200ms) and (-8V, -9V and -10V for
200ms), respectively.

144
Figure 6.9 Model of deep level charge storage and discharging
mechanisms.

147
Figure 6.10 Pictorial explanation of the formation of the transient drain
current during the discharging process. A step increase in the
drain current is resulted when an electron is de-trapped from a
nanocrystal into the Si substrate at time t=t
i
. The drain
current transient curve could be represented by a summation
of these step functions over the elapsed time throughout the
discharging process.

148
Figure 6.11 Drain current (I
D
) transient at the read voltage (V

R
) of 3 V
after writing at 4V. Symbols represent measured data and the
lines are fitted data.

150
Figure 6.12 Inverse of the discharging time constant divided by squared
temperature (T) at various read voltage and temperature T.

151
Figure 6.13 The drain current transient during the application of the read
voltage at 4V, after the application of a write voltage of 8V
for 60s.

152
Figure 6.14 Inverse of the discharging time constant divided by squared
temperature (T) versus the inverse of T for germanium
nanocrystal memory transistors.

154
Figure 6.15 Drain current difference during discharging divided by
squared temperature (T) versus the inverse of T.

159
Figure 6.16 Temperature dependence of retention time for nc-Ge
capacitors with SiO
2
capping layer and HfAlO capping layer.

162

xvi

1
Chapter 1: Introduction

1.1 Background
The floating gate (FG) memory device is the most widely used design in
nonvolatile semiconductor memory (NVSM) implementation. However, there are
numerous difficulties in the scaling down of the FG NVSM device, especially decreasing
the tunnel oxide thickness to meet conflicting operational requirements. On one hand, the
tunnel oxide has to be thin to allow low-voltage, fast program and erase. On the other
hand, the tunnel oxide has to be thick to provide superior isolation under charge retention
condition in order to maintain information integrity of up to 10 years. As a result of these
contradicting demands, Flash memory manufacturers have settled on a compromise for
tunnel oxide thickness with values in the range 9 to 11 nm [1].
Storing charge on a single node (i.e. the FG node) makes the conventional Flash
memory structure particularly prone to failure of the FG isolation (i.e., tunnel oxide). One
weak spot in the tunnel oxide is sufficient to create a fatal discharge path, compromising
long-term nonvolatility. One way to overcome this is to rely on distributed charge storage
with charge storage nodes isolated from each other. The most popular types are
polysilicon-oxide-nitride-oxide-silicon (SONOS) or nanocrystal memories. The main
disadvantage for SONOS memory devices is that the traps are distributed randomly in the
nitride charge storage layer [2]-[3]. Nanocrystal NVM offers greater control of the charge
storage spatial location, especially if a templated self assembly method is used to order
the nanocrystals [4].


2

In a nanocrystal NVM device, the charge is not stored on a continuous FG poly-Si
layer, but instead on a layer of discrete, mutually isolated, crystalline nanocrystals or
dots, typically made of semiconductor material [5]–[59]. Each dot will typically store
only a single charge; collectively the charges stored in these dots control the
channel-conductivity of the memory transistor. Compared to FG NVM, nanocrystal
charge-storage offers several advantages; the main one being the potential to use a
thinner tunnel oxide without sacrificing nonvolatility. Hence this will lead to lower
operating voltages and higher program and erase speeds. Due to the distributed nature of
charge storage, the charge storage device is more robust and fault tolerant to charge loss.
This will also lead to improved endurance write/erase performance as compared to FG
NVM.

1.2 Motivation
A nanocrystal memory device typically consists of three layers of gate material
deposited on the Si-substrate. These layers are namely, the tunnel oxide layer, the
germanium (Ge) nanocrystal (charge storage) layer and the capping oxide layer.
Although a thin tunnel oxide is highly-desirable for fast programming speed, one inherent
issue would be the penetration of Ge through the thin tunnel oxide into the silicon (Si)
substrate during high temperature annealing to form the Ge nanocrystals, resulting in a
complete loss of charge storage capability [10]. This penetration issue imposes a lower
bound (~5nm) to the scaling of the tunnel dielectric layer [11].
In this project, we intend to address the Ge penetration issue as well as to further
reduce the tunnel dielectric electrical thickness by using an alternative material with a

3
higher permittivity (κ) value. The high-κ material is able to provide a sufficiently thick
physical layer to prevent the Ge from penetrating through the tunnel dielectric while at
the same time, providing a much lower equivalent oxide thickness (EOT) for device
operation.
In order to obtain a fast programming speed, the electric field across the tunnel

oxide needs to be high so that charge carriers can tunnel rapidly from the Si substrate into
the Ge nanocrystals. This high electric field could be achieved by simply applying a high
voltage at the gate electrode but this approach is counter to low voltage operation.
Application of a high gate voltage is also likely to induce unnecessary degradation on the
tunnel oxide during Fowler-Nordheim tunneling of the charge carriers. Alternatively, the
high electric field across the tunnel oxide could be achieved by decreasing the Ge layer
thickness (i.e., nanocrystal size) or the capping oxide thickness. As there is a limit to
decreasing the Ge layer thickness, a more viable approach would hence be to decrease the
capping oxide thickness. Similar to the tunnel dielectric layer, there also exists a lower
bound to the scaling of the capping oxide thickness as the Ge could out-diffuse from the
middle Ge layer into the environment during the high temperature annealing to form the
Ge nanocrystals if the capping oxide is too thin. It would be interesting to determine the
lower bound limit for the SiO
2
cap layer thickness to ensure proper device functioning as
well as to further reduce this layer electrically by replacing it with a high-κ material. A
high-κ capping oxide layer would also result in better electric field coupling of the gate
voltage to the tunnel oxide.

4
1.3 Research Objectives
The aim of this research is to explore the possibility of replacing the silicon
dioxide (SiO
2
) components (tunnel oxide layer and capping layer) in a trilayer gate
structure nanocrystal memory device with a high-κ material. The performance of the
device with the high-κ layers will be compared with the control device with conventional
SiO
2
layers. To obtain a better understanding of the role of each replaced layer and its

effect on device performance, the individual layers will be changed one at a time and its
characteristics studied.
During the initial phase of this project, the suitability of several high-κ materials
(e.g., zirconium dioxide (ZrO
2
), hafnium dioxide (HfO
2
) and hafnium aluminum oxide
(HfAlO)) as a replacement material for SiO
2
will first be investigated before deciding on
a suitable material. Charge storage capability, charging and discharging speeds as well as
charge retention studies will be carried out and compared on nanocrystal capacitor
memory devices with 5nm (EOT) of high-κ tunnel dielectric and on device with the same
thickness (5nm) of conventional RTO.
As the conventional RTO thickness has a lower limit at 5nm, below which Ge
penetration would result in complete loss of charge storage capability, we attempt to
address this penetration issue and also further reduce this 5nm EOT limit by replacing the
conventional RTO with a suitable high-κ material.
As the down-scaling of the capping layer (physical and electrical thickness) is
beneficial to the programming/erasing speed of the device, the possibility of reducing the
thickness of 50nm SiO
2
cap layer [8] -[11], as well as replacing this layer with a suitable
high-κ material would also be investigated.

5
Electrical characterizations such as capacitance–voltage (C-V), current-voltage
(I-V) and charge retention time studies will be performed on these devices. The more
sensitive conductance-voltage (G-V) measurement method will also be used to

characterize the devices to obtain further insights into the nanocrystal memory device
operation. A methodology for extracting the nanocrystal density based on the G-V data
will be discussed.
Upon the fabrication of the nanocrystal memory capacitors, a full-scale
nanocrystal memory transistor with high-κ as the tunnel dielectric material will be
fabricated and characterized. An experiment for extraction of the nanocrystal trap energy
level (E-trap) based on the study of drain current (during the discharging of trapped
charge) with respect to temperature will be carried out [12]. An alternative method for
extraction of E-trap levels will be proposed and discussed. Finally, the possibility of
engineering the E-trap levels in the Ge nanocrystals by varying the surrounding matrix
will be investigated.

1.4 Organization of Thesis
The thesis is arranged in a way to address the objectives set out for this research.
Chapter 2 is devoted to cover the key findings in the literature survey on high-κ materials
as well as provide an overview of the theory of FG flash memory and nanocrystal
memory structures. Chapter 3 describes the work carried out on fabrication and
characterization of several high-κ materials, namely ZrO
2
, HfO
2
and HfAlO, to identify
suitable high-κ materials for the nanocrystal memory. Chapter 4 examines the
performance of the nanocrystal memory device with high-κ HfO
2
and HfAlO materials as

6
the tunnel dielectric material. Chapter 5 studies the possibility of employing the high-κ
HfAlO material as the capping layer for enhanced electric field coupling. The results of

conductance-voltage (G-V) measurements performed on the nanocrystal memory
capacitor devices will be shown in this chapter. A method for estimating the nanocrystal
density based on the G-V data will also be discussed. Chapter 6 describes the electrical
characterization of the transistor-based nanocrystal memory structures with high-κ
HfAlO material as the tunnel dielectric. The extraction of the nanocrystal trap energy
level based on the study of drain current (during the discharging of trapped charge) with
respect to temperature will be presented in this chapter. An alternative method to extract
the energy trap level will be compared and discussed.

7
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