Design of a wide input supply range buck boost converter

DESIGN OF A WIDE INPUT SUPPLY RANGE
BUCK-

(B.Eng (Hons), NUS)

&

2009


ACKNOWLEDGEMENTS
The author would like to express his gratitude to project supervisor, A/Prof Xu Yong Ping
for his invaluable advice and guidance during the course of the author’s work.

i


TABLE OF CONTENTS
i
SUMMARY

1
1.1
Future Trend
1.2
Alternate Sustainable Energy Sources
1.3
Linear Low-Dropout Regulator versus Switch-Mode Power Supplies
1.3.1
Linear Low-Dropout Regulator
1.3.2

Switch-Mode DC-DC Power Supplies

Ch ap t er 2

B u c k -B o o s t Co n v er t er To p o l o g i es

1
2
3
3
6

9

2.1
Conventional Inverting Buck-Boost Converter
2.1.1
Continuous Conduction Mode
2.1.2
Discontinuous Conduction Mode
2.2
4-Switches Non-Inverting Buck-Boost Converter
2.2.1
Continuous Conduction Mode
2.2.2
Discontinuous Conduction Mode
2.3
Modified 4-Switches Non-Inverting Buck-Boost Converter
2.3.1
Buck Mode Operation

2.3.1.1
Buck Configuration - Continuous Conduction Mode
2.3.1.2
Buck Configuration - Discontinuous Conduction Mode
2.3.2
Boost Mode Operation
2.3.2.1
Boost Configuration - Continuous Conduction Mode
2.3.2.2
Boost Configuration -Discontinuous Conduction Mode
2.3.3
Buck-Boost Mode Operation
2.4
Inverting Cuk Buck-Boost Converter
2.4.1
Cuk Buck-Boost Converter Operations
2.5
Recent Publications and Developments
2.6
Overall Architecture of Proposed Buck-Boost Converter

9
10
13
16
17
20
22
23
24

25
27
28
28
30
31
32
34
36

3.1
Traditional Bandgap Reference
3.1.1
Negative Temperature Coefficient
3.1.2
Positive Temperature Coefficient
3.2
Bandgap Reference Design Specifications
3.3
Bandgap Reference Design implementation

42
42
43
46
47


3.3.1
Bandgap Reference Operational Amplifier Design

3.3.2
Bandgap Reference Top
3.4
Bandgap Reference Simulation Results
3.4.1
Bandgap 250mV Variation with Temperature
3.4.2
Bandgap 660mV Variation with Temperature
3.4.3
Bandgap 250mV Variation with Temperature & Process Corner/ Mismatch
3.4.4
Bandgap 660mV Variation with Temperature & Process Corner/ Mismatch
3.4.5
Bandgap Reference Frequency Response
3.4.6
Bandgap 660mV Variation with Substrate Voltage
3.4.7
Bandgap Profile during Supply Startup
3.4.8
Bandgap Reference Line Transient Response
3.5
Bandgap Reference Simulated Performance (Summarized)

49
51
53
53
55
56
59

62
64
65
67
68

4.1
4.2
4.3
4.4
4.5
4.6
4.7

Startup Control Circuitries Design Considerations
Proposed Design for Startup Control System
Adaptive Start-Up On-Time Generator Design
Current-Starved Start-Up Ring Oscillator Design
Startup Adaptive On-Time Generator Simulation Results
Startup Current-Starved Ring Oscillator Simulation Results
Startup Ring Oscillator Simulated Performance (Summarized)

69
70
72
76
79
84
87

5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.8

Internal Power Management System
Internal Regulator 1 Design Considerations
Internal Regulator 1 Intermediate Buffer Design
Internal Regulator 1 Error Amplifier Design
Internal LDO Regulator 1 Stability Analysis
Internal Regulator 1 Reference Generator Design
Internal Regulator 1 Simulation Results
Internal Regulator 1 Output VSS_V33_EXT Variation with Substrate Input
Internal LDO Regulator 1 Frequency Response
Internal Regulator 1 Line Transient Response
Internal Regulator 1 Power Supply Rejection Ratio (PSRR)
Internal Regulator 1 Transient Response
Internal LDO Regulator 1 Simulated Performance (Summarized)

88
93

97
99
100
103
106
106
107
110
112
112
114

6.1
6.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4

Internal Regulator 2 Design Considerations
Internal Low-Dropout Regulator 2 Input Reference
Internal Low-Dropout Regulator 2 Design
Internal Low-Dropout Regulator 2 Simulation Results
Internal Low-Dropout Regulator 2 Frequency Response
Internal Low-Dropout Regulator 2 Output Variation with VPSUB
Internal Low-Dropout Regulator 2 Line Transient Response
Internal Regulator 2 and Power NMOS Driver Transient Response

115
116
117
121
121
123
123
125


6.5

Internal LDO Regulator 2 Simulated Performance (Summarized)

126

7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.5

External LDO Regulator Design Considerations
External LDO Regulator Intermediate Buffer Design
External LDO Regulator Stability Analysis
External LDO Regulator Simulation Results

External Regulator Frequency Response
External LDO Regulator Output Variation with V33
External LDO Regulator Line Transient Response
External LDO Regulator Load Transient Response
External LDO Regulator Simulated Performance (Summarized)

127
128
131
134
134
139
140
143
145

8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9

Regulatory Control Scheme Design Considerations
Regulatory Control System Design
Regulatory Comparator Design Considerations
Regulatory Current-Starved Ring Oscillator Design

Regulatory Regenerative Comparator Design
Regulatory Current-Starved Ring Oscillator Simulation Results
Regulatory Regenerative Latch Comparator Simulation Results
Regulatory Control System Simulation Results
Regulatory System Sub-blocks Simulated Performance (Summarized)

147
148
150
151
154
157
160
161
163

9.1
9.2
9.3
9.4
9.5
9.6

Buck-Boost Converter Synchronous Operations
Anti-Backflow Current Control System Design Considerations
Anti-Backflow Current Control System Design
Anti-Backflow Current Control Comparator Design
Anti-Backflow Current Control On-Time Generator Design
Anti-Backflow Current Control Comparator Simulation Results

164
166
168
170
172
176

10.1
10.2
10.3
10.4
10.5
10.6

Austria Microsystems 0.35µm High-Voltage Process
Pin Allocation
Chip Top Layout
Buck-Boost Converter Startup Transient Response
Buck-Boost Converter Steady-State Response
Summary

181
184
184
186
188
189

11.1
11.2

Buck-Boost Converter Performance Comparison
Novel Buck-Boost Converter Design

190
193


A.1
A.2
A.3
A.4
A.5
A.6
A.6.1
A.6.2
A.7

Adaptive NMOS Power Transistor On-Time
Simple Adaptive On-Time Generator
Proposed Adaptive On-Time Generator Design
Proposed Adaptive On-Time Generator Amplifier Design
Proposed Adaptive On-Time Generator Comparator Design
Adaptive On-Time Generator Simulation Results
Voltage-to-Current (V-I) Converter AC Loop Response
Adaptive On-Time Generator Transient Response
Adaptive On-Time Generator Simulated Performance (Summarized)

B.1
Current Reference Design

B.2
Current Reference Simulation Results
B.2.1
Current Bias Generator Loop Frequency Response
B.2.2
Bias Current Supply Dependence

200
200
203
205
207
208
208
212
217

218
220
220
222

VSS_V33_EXT
V33 to VSS_V33_EXT Level Shifter Design

C.1
C.2

Level Shifter Simulation Results

224
226

D.1
D.2
D.3
D.3.1
D.3.2
D.3.3
D.4

Test Setup
Test Method
Test Results
Buck-Boost Converter Startup
Buck-Boost Converter Regulation
Buck-Boost Converter Line Transient Response
Discussions & Suggestions

229
230
231
232
233
235
238


SUMMARY
Buck-boost converters allow the flexibility of stepping-up and stepping-down the input

supply to generate a regulated output, thus making it very attractive for applications with
wide input supply range. Currently, off-the-shelf buck-boost converters require a
minimum operating voltage of 1.8V. As a result, the operating conditions in which these
applications are functional are severely limited. Recently, boost converters which can
operate with a minimum supply voltage of 0.3V are introduced and they are designed for
applications utilizing solar cells as an energy source. However, boost converters are only
capable of stepping-up the input supply. In this project, the concepts implemented for
these boost converters are modified and extended for use in buck-boost converter
implemented using the conventional inverting topology. The converter is designed for
low-power applications and it caters to a maximum load of 25mA. Special startup
circuitries are designed to ensure that the startup inductor current peak is controlled,
without damaging the device and to allow startup operations with minimal input voltage.
In addition, a novel internal power management system is implemented and it allows for
continual steady-state operations even as input drops to 0.3V. The converter operates in
Pulse Frequency Modulation (PFM) mode during steady-state. Synchronous rectification
operations are supported for the buck-boost converter through the implementation of a
novel anti-backflow current system which greatly reduces the quiescent current
consumption. The converter is designed in AMS High-Voltage 0.35 m process. The
dimension of the layout implementation is 2.519mm by 2.371mm. Simulation results
have shown that the converter consumes only 10.77 A and is able to startup with input
supply of 0.75V typically. In addition, the converter is able to remain in steady-state
operations even as input drops to 0.30V. With an input of 5.0V and an external load of
25mA, the designed converter possesses a conversion efficiency of 88.3%.

ii


LIST OF TABLES
Table 1-1: DC-DC converters summarized performance

8

Table 2-1: Buck-boost converter topologies summarized characteristics

35

Table 2-2: Buck-boost converter circuit blocks roles & functionalities (Summarized)

41

Table 3-1: Bandgap reference summarized simulated performance

68

Table 4-1: Startup current-starved ring oscillator summarized simulated performance

87

Table 5-1: Internal LDO regulator 1 summarized simulated performance

114

Table 6-1: Internal LDO regulator 2 summarized simulated performance

126

Table 7-1: External LDO regulator summarized simulated performance

146

Table 8-1: Regulatory control system sub-blocks summarized simulated performance

163

Table 10-1: Power management IC pin allocation and definitions

185

Table A-1: Adaptive on-time generator summarized simulated performance

217

iii


LIST OF FIGURES
Figure 1-1: Linear low-dropout regulator block diagram

3

Figure 1-2: Energy harvested from piezoelectric shoes on storage capacitor [2]

5

Figure 1-3: DC voltage generated by piezoelectric harvester with different wind speed [3]

5

Figure 2-1: Conventional Inverting Buck-Boost Converter [9]

9

Figure 2-2: Ideal CCM operation of inverting buck-boost converter (VS=5.0V, Vout=2.5V)

12

Figure 2-3: Ideal CCM operation of inverting buck-boost converter (VS=1.0V, Vout=2.5V)

13

Figure 2-4: Ideal DCM operation of inverting buck-boost converter (VS=5.0V, Vout=2.5V)

15

Figure 2-5: Ideal DCM operation of inverting buck-boost converter (VS=1.0V, Vout=2.5V)

15

Figure 2-6: 4-Switches Non-Inverting Buck-Boost Converter [9]

16

Figure 2-7: Ideal CCM operation of 4-switches converter (VS=3.3V, Vout=2.5V)

18

Figure 2-8: Ideal CCM operation of 4-switches converter (VS=2.5V, Vout=2.5V)

19

Figure 2-9: Ideal CCM operation of 4-switches converter (VS=1.0V, Vout=2.5V)

19

Figure 2-10: Ideal DCM operation of 4-switches converter (VS=3.3V, Vout=2.5V)

21

Figure 2-11: Ideal DCM operation of 4-switches converter (VS=2.5V, Vout=2.5V)

21

Figure 2-12: Ideal DCM operation of 4-switches converter (VS=1.0V, Vout=2.5V)

22

Figure 2-13: 4-switches non-inverting buck-boost converter in buck configuration [9]

23

Figure 2-14: Ideal CCM operation of modified 4-switches converter (VS=3.3V, Vout=2.5V)

25

Figure 2-15: Ideal DCM operation of modified 4-switches converter (VS=3.3V, Vout=2.5V)

26

Figure 2-16: 4-switches non-inverting buck-boost converter in boost configuration [9]

27

Figure 2-17: Ideal CCM operation of modified 4-switches converter (VS=1.0V, Vout=2.5V)

29

Figure 2-18: Ideal DCM operation of modified 4-switches converter (VS=1.0V, Vout=2.5V)

30

Figure 2-19: Inverting Cuk Buck-Boost Converter [9]

32

Figure 2-20: Proposed Inverting Buck-Boost Converter Block Diagram

37

Figure 3-1: Traditional bandgap reference circuit implementation

44

Figure 3-2: Schematic of low-supply voltage bandgap core circuit [17]

47

Figure 3-3: Schematic of operational amplifier in bandgap core circuit

50

Figure 3-4: Schematic of bandgap reference top inclusive of buffer

52

Figure 3-5: Bandgap reference variation with temperature (V33=1.5V, Typical)

53

Figure 3-6: Bandgap reference variation with temperature (V33=1.2V, Typical)

54

Figure 3-7: Bandgap reference variation with temperature (V33=2.0V, Typical)

55

Figure 3-8: Bandgap reference variation with temperature (V33=3.3V, Typical)

56

Figure 3-9: Bandgap reference variation with temperature (V33=1.2V, Corners)

57

Figure 3-10: Bandgap reference temperature coefficients before trim (V33=1.2V)

58

iv

Figure 3-11: Bandgap reference temperature coefficients after trim (V33=1.2V)

58

Figure 3-12: Bandgap reference output after trim (V33=1.2V)

59

Figure 3-13: Bandgap reference variation with temperature (V33=3.3V, Corners)

60

Figure 3-14: Bandgap reference temperature coefficients before trim (V33=3.3V)

60

Figure 3-15: Bandgap reference temperature coefficients after trim (V33=3.3V)

61

Figure 3-16: Bandgap reference output after trim (V33=3.3V)

61

Figure 3-17: Bandgap 250mV loop gain frequency response (V33=1.2V, Typical)

62

Figure 3-18: Bandgap 250mV loop gain frequency response (V33=1.5V, Typical)

63

Figure 3-19: Bandgap 660mV loop gain frequency response (V33=3.3V, Typical)

63

Figure 3-20: Bandgap reference variation with substrate (V33=2.0V, Typical)

64

Figure 3-21: Bandgap reference variation with substrate (V33=3.3V, Typical)

65

Figure 3-22: Bandgap reference 250mV startup (V33 ~ 0V to 1.2V in 1ms, Typical)

66

Figure 3-23: Bandgap reference 660mV startup (V33 ~ 0V to 3.3V in 1ms, Typical)

66

Figure 3-24: Bandgap line transient (V33 ~ 1.2V to 1.5V in 1µs, Typical)

67

Figure 3-25: Bandgap line transient (V33 ~ 3.225V to 3.375V in 30µs, Typical)

68

Figure 4-1: Startup control system block diagram

71

Figure 4-2: Simple startup adaptive on-time generator schematic

74

Figure 4-3: Startup Current-Starved Ring Oscillator Schematic

77

Figure 4-4: Startup adaptive on-time & Current limit generated (Typical, VPSUB=-1.5V)

79

Figure 4-5: Startup adaptive on-time & Current limit generated (Corners, VPSUB=-1.5V)

80

Figure 4-6: Startup adaptive on-time & Current limit generated (Typical, VPSUB=-3.0V)

81

Figure 4-7: Startup adaptive on-time & Current limit generated (Typical, VPSUB=-5.0V)

82

Figure 4-8: Startup adaptive on-time & Current limit generated (Typical, VPSUB=-10.0V)

82

Figure 4-9: Startup adaptive on-time & Current limit generated (Corners, VPSUB=-10.0V)

83

Figure 4-10: Startup adaptive current limit generated against VPSUB (Typical)

83

Figure 4-11: Startup ring oscillator output transient response (Corners, VPSUB=-1.0V)

84

Figure 4-12: Startup ring oscillator transient response (Corners, VPSUB=-1.5V)

85

Figure 4-13: Startup ring oscillator transient response (Corners, VPSUB=-3.0V)

85

Figure 4-14: Startup ring oscillator transient response (Corners, VPSUB=-5.0V)

86

Figure 4-15: Startup ring oscillator transient response (Corners, VPSUB=-10.0V)

86

Figure 5-1: Internal Power Management Scheme A

89

Figure 5-2: Internal Power Management Scheme B

91

Figure 5-3: Architecture of LDO regulator with intermediate buffer stage [31]

96

Figure 5-4: Simple source-follower implementation of the intermediate buffer [31]

97

Figure 5-5: Source-follower with shunt feedback implementation of the buffer

98

v


Figure 5-6: Folded-cascode error amplifier in architecture of LDO regulator [31]

100

Figure 5-7: Internal low-dropout regulator 1 with reference generator schematic

105

Figure 5-8: DC variation of VSS_V33_EXT and the reference generator output with VPSUB

106

Figure 5-9: Internal LDO 1 regulation loop response (V33=3.3V, VPSUB=-5.0V, Typical)

107

Figure 5-10: Internal LDO 1 regulation loop response (V33=3.3V, VPSUB=-5.0V, W.C)

108

Figure 5-11: Internal LDO 1 regulation loop response (V33=3.3V, VPSUB=-5.0V, Corner)

109

Figure 5-12: Internal LDO 1 regulation loop response (V33=3.3V, VPSUB=-0.30V, Corner) 109
Figure 5-13: Internal LDO 1 regulation loop response (V33=3.3V,VPSUB=-10.0V, Corner) 110
Figure 5-14: Internal LDO regulator 1 line transient response (V33=3.3V, Typical)

111

Figure 5-15: Internal LDO regulator 1 line transient response (V33=3.3V, Corners)

111

Figure 5-16: Internal LDO regulator 1 PSRR (V33=3.3V, VPSUB=-5.0V, Corners)

112

Figure 5-17: Internal LDO 1 output transient response (VPSUB=-5.0V, Corners)

113

Figure 5-18: Internal LDO 1 low to high output response (VPSUB=-5.0V, Corners)

113

Figure 6-1: Internal LDO reference and regulator 2 schematic

118

Figure 6-2: Structure of low-dropout regulator utilizing PCFC scheme [36]

120

Figure 6-3: Internal LDO 2 regulation loop frequency response (VPSUB=-5.0V, Typical)

122

Figure 6-4: Internal LDO 2 regulation loop frequency response (VPSUB=-5.0V, Corner)

122

Figure 6-5: Internal LDO 2 regulation loop frequency response (PreDrvN=0V, Typical)

123

Figure 6-6: Internal LDO 2 output variation with VPSUB (No Load, Corners)

124

Figure 6-7: Internal LDO 2 reference and output line transient (VPSUB=-5.0V, Typical)

124

Figure 6-8: Internal LDO 2 reference and output line transient (VPSUB=-5.0V, Corners)

125

Figure 6-9: Internal LDO 2 and power NMOS driver transient (VPSUB=-5.0V, Typical)

125

Figure 7-1: Direct implementation of NMOS source-follower with shunt feedback

130

Figure 7-2: Folded-cascode implementation of source-follower with shunt feedback

131

Figure 7-3: External low dropout regulator schematic

133

Figure 7-4: External LDO regulation loop response (V33=1.2V, ILoad=0mA, Typical)

134

Figure 7-5: External LDO regulation loop response (V33=1.2V, ILoad=2mA, Typical)

135

Figure 7-6: External LDO regulation loop response (V33=1.2V, ILoad=0mA, Corners)

136

Figure 7-7: External LDO regulation loop response (V33=1.2V, ILoad=2mA, Corners)

136

Figure 7-8: External LDO regulation loop response (V33=3.3V, ILoad=0mA, Typical)

137

Figure 7-9: External LDO regulation loop response (V33=3.3V, ILoad=2mA, Typical)

138

Figure 7-10: External LDO regulation loop response (V33=3.3V, ILoad=0mA, Corners)

138

Figure 7-11: External LDO regulation loop response (V33=3.3V, ILoad=2mA, Corners)

139

Figure 7-12: DC variation of external LDO output with V33 when converter is disabled

140

Figure 7-13: External LDO regulator line transient response (V33=1.2V to 1.5V, Typical) 141

vi


Figure 7-14: External LDO regulator line transient response (V33=1.5V to 1.2V, Typical) 141
Figure 7-15: External LDO regulator line transient response (V33=3.0V to 3.3V, Typical) 142
Figure 7-16: External LDO regulator line transient response (V33=3.3V to 3.0V, Typical) 142
Figure 7-17: External LDO load transient response (V33=1.2V, ILoad=0mA to 2mA, Typ)

143

Figure 7-18: External LDO load transient response (V33=1.2V, ILoad=2mA to 0mA, Typ)

144

Figure 7-19: External LDO load transient response (V33=3.3V, ILoad=0mA to 2mA, Typ)

144

Figure 7-20: External LDO load transient response (V33=3.3V, ILoad=2mA to 0mA, Typ)

145

Figure 8-1: Regulatory system current-starved ring oscillator schematic

152

Figure 8-2: Regulatory system regenerative latch comparator schematic

156

Figure 8-3: Regulatory ring oscillator transient response (Typical, V33=3.3V)

157

Figure 8-4: Regulatory ring oscillator transient response (Typical, V33=2.0V)

158

Figure 8-5: Regulatory ring oscillator transient response (Corners, V33=3.3V)

159

Figure 8-6: Regulatory ring oscillator transient response (Corners, V33=2.0V)

159

Figure 8-7: Regulatory comparator preamp magnitude response (Corners, V33=3.3V)

160

Figure 8-8: Regulatory comparator preamp magnitude response (Corners, V33=3.0V)

161

Figure 8-9: Regulatory control transient response (Typical, V33=3.2875V to 3.3125V)

162

Figure 8-10: Regulatory control transient response (Typical, V33=3.3125V to 3.2875V)

162

Figure 9-1: Inverting buck-boost converter voltage & current profiles during operations

164

Figure 9-2: Inverting buck-boost converter waveforms for early and late turn-off

165

Figure 9-3: Anti-backflow current control comparator with input clamps schematic

171

Figure 9-4: Anti-backflow current control on-time generator schematic

173

Figure 9-5: Anti-backflow comparator transient response (Typical, V33=2.2V)

177

Figure 9-6: Anti-backflow comparator transient response (Corners, V33=2.2V)

178

Figure 9-7: Anti-backflow comparator zoomed transient response (Corners, V33=2.2V)

178

Figure 9-8: Anti-backflow comparator transient response (Typical, V33=3.3V)

179

Figure 9-9: Anti-backflow comparator transient response (Corners, V33=3.3V)

179

Figure 9-10: Anti-backflow comp zoomed transient response (Corners, V33=3.3V)

180

Figure 10-1: Cross sectional view of standard CMOS process NMOS

181

Figure 10-2: Buck-boost converter transistor type choice for each block

183

Figure 10-3: Power management IC top level layout

186

Figure 10-4: Buck-boost converter startup transient response (VPSUB=-5.0V, Typical)

187

Figure 10-5: Buck-boost converter startup transient response (VPSUB=-0.75V, Typical)

187

Figure 10-6: Buck-boost converter steady-state response (VPSUB=-5.0V, ILoad=25mA)

188

Figure A-1: Basic waveforms observed during operations of buck-boost converter

198

Figure A-2: Simple implementation of adaptive on-time generator [12]

200

vii


Figure A-3: Proposed adaptive on-time generator block diagram

204

Figure A-4: Adaptive on-time generator (regulatory control) schematic

206

Figure A-5: V-I Converter AC Loop Response (V33=3.3V, VPSUB=-5.0V, RBIAS=4.7MΩ)

209

Figure A-6: V-I Converter AC Loop Response (V33=2.2V, VPSUB=-5.0V, RBIAS=4.7MΩ)

209

Figure A-7: V-I Converter AC Loop Response (V33=3.3V, VPSUB=-0.30V, RBIAS=15MΩ)

210

Figure A-8: V-I Converter AC Loop Response (V33=2.2V, VPSUB=-0.30V, RBIAS=15MΩ)

211

Figure A-9: V-I AC Response (V33=3.3V, VPSUB=-0.30V, RBIAS=15MΩ, Corners)

211

Figure A-10: V-I AC Response (V33=2.2V, VPSUB=-0.30V, RBIAS=15MΩ, Corners)

212

Figure A-11: Adaptive Ton transient response (VPSUB=-5.0V, RBIAS=4.7MΩ, Corners)

213

Figure A-12: Adaptive Ton transient response (VPSUB=-0.30V, RBIAS=4.7MΩ, Corners)

213

Figure A-13: Adaptive Ton transient response (VPSUB=-10.0V, RBIAS=4.7MΩ, Corners)

214

Figure A-14: Adaptive on-time variation with VPSUB (V33=3.3V, RBIAS=4.7MΩ, Typical)

215

Figure A-15: Adaptive on-time variation with VPSUB (V33=3.3V, RBIAS=4.7MΩ, Fast)

216

Figure A-16: Adaptive on-time variation with VPSUB (V33=3.3V, RBIAS=4.7MΩ, Slow)

216

Figure B-1: Current bias generator and current mirrors schematic

219

Figure B-2: Current bias generator loop frequency response (Typical, V33=1.2V)

221

Figure B-3: Current bias generator loop frequency response (Typical, V33=3.3V)

221

Figure B-4: Voltage and Current Reference Supply Dependence (Typical, VPSUB=0.0V)

222

Figure B-5: Voltage and Current Reference Supply Dependence (Typical, VPSUB=-5.0V) 223
Figure C-1: V33 to VSS_V33_EXT level shifter schematic

225

Figure C-2: V33 to VSS_V33_EXT level shifter low-to-high transient profile (Typ, V33=3.3V)

227

Figure C-3: V33 to VSS_V33_EXT level shifter high-to-low transient profile (Typ, V33=3.3V)

227

Figure C-4: V33 to VSS_V33_EXT level shifter low-to-high transient profile (Typ, V33=2.0V)

228

Figure C-5: V33 to VSS_V33_EXT level shifter high-to-low transient profile (Typ, V33=2.0V) 228
Figure D-1: Bench evaluation setup and connections schematic

230

Figure D-2: Buck-boost converter bench evaluation - startup profile (VPSUB = -0.76V)

232

Figure D-3: Buck-boost converter bench evaluation - startup profile (VPSUB = -2.0V)

233

Figure D-4: Buck-boost converter bench evaluation - regulatory profile (VPSUB = -0.76V) 234
Figure D-5: Buck-boost converter bench evaluation - regulatory profile (VPSUB = -3.50V) 235
Figure D-6: Buck-boost bench evaluation – line transient (VPSUB ~ -0.30 to -1.30V)

236

Figure D-7: Buck-boost bench evaluation – line transient (VPSUB ~ -1.30 to -0.30V)

236

Figure D-8: Buck-boost bench evaluation – line transient (VPSUB ~ -1.0 to -2.0V)

237

Figure D-9: Buck-boost bench evaluation – line transient (VPSUB ~ -2.0 to -1.0V)

237

viii


-

CChhaapptteerr 11

Introduction
In recent years, the increasing demand for ultra low power portable devices, and the
growing requirements of more sophisticated functionalities embedded into these devices
had resulted in designers having to manage the power consumption of the underlying
chips more efficiently. Efficient power management techniques are much needed so as
to lengthen the battery life, without having to introduce batteries with higher capacities
which often incur higher manufacturing cost and result in a heavier device.

The rising energy cost and also the increasing awareness of environmental issues have
resulted in product developers to examine the possible use of sustainable energy
sources in applications. In fact, consumer electronic products such as solar chargers
which are based on “green” energy sources can already be found in the market.
However, in order for the traditional batteries to be effectively replaced by these
sustainable energy sources, the power conversion efficiency of these sources has to be
improved tremendously. Besides that, due to the differences in the characteristics of
these sources as compared to batteries, power management ICs which are more
efficient and are able to extract more power from these sources have to be developed.

Chip manufacturers are looking into this growing market with much enthusiasm and are
already in the process of developing ICs for these applications. Early this year,

1


-

Freescale Semiconductor has developed an integrated mixed signal chip that can boost
the output from a single solar cell into a usable power source [1]. Previously, in order to
harness green energy from solar cells, multiple cells need to be stacked in series, due to
the low voltage output from a single cell. This implies that in order to obtain a 3V output,

which is required to power conventional electronic products, 8 solar cells have to be
stacked in series. This results in not only higher cost of the product but also reduced
portability and reliability of the end product. Freescale Semiconductor claimed that the
boost converter is able to start from 0.32V and boost the output to 4V, by making use of
the low threshold MOS from its 130 nm Smartmos-10 process. Hence, with further
advancement in the power management techniques, one can foresee that the use of
sustainable energy sources in consumer electronics will be made more attractive.

Besides solar energy sources, researchers had examined other sustainable energy
sources. Way back in 1998, researchers from the MIT Media Lab had presented a selfpowered system [2] which had been built around a pair of shoes. The shoes can be used
to generate electrical power while walking. The electrical power generated allowed the
bearer to transmit a 12-bit RFID code while walking. Wind energy has also been used to
power autonomous wind speed sensors. In [3], a piezoelectric based wind energy
harvester was designed such that electrical power is generated to power a RF
transmitter. Information such as wind speed can then be remotely transmitted back to
base using this self-powered system. Although devices powered by sustainable energy
sources seem attractive, the availability of electrical power harvested is largely
dependent on the unpredictable environmental conditions. Hence, researchers and
product designers are looking into ways to store the energy harvested effectively so that
2


-

the storage can be tapped upon during unfavorable conditions. Alternatively, systems
running on dual or multiple energy sources can be designed. However, the different
characteristics, i.e. differences in supply voltage ranges etc., of the energy sources have
to be considered in designing the power management unit.

-

-

-

1-1: Linear low-dropout regulator block diagram

Figure 1-1 shows a general block diagram of a linear regulator. It consists of a bandgap
reference generator and an error amplifier used to regulate the output voltage by
controlling the pass transistor. The design is simple and depending on the specifications
for the regulated voltage, an output filtering capacitor may or may not be required.
Hence, minimal external components are required in the implementation. A more indepth analysis of the linear regulator will be given later. However, there are two main
drawbacks in using the linear regulator. Firstly, the output regulated voltage can only be

3


-

a stepped down voltage of the input supply. Hence, limiting its application in systems
with low input supply voltage, for example solar cells applications. Furthermore, the
linear regulator suffers from low conversion efficiency. In cases when the difference in
the input and output voltage is large or when the load current is significant, the power
loss in the pass element will be significant, thereby degrading its overall efficiency to a
large extent. For instance, in the case when the input supply voltage is 12V, the output
regulated voltage at 3.3V and the load current is 10mA, the power loss in the pass
transistor is 870mW. Assuming that the error amplifier and reference voltage consumes
a negligible amount of current, the overall efficiency of the linear regulator is only 27.5%.
In conclusion, the linear regulator is best suited in low current applications with small
differences between input and output regulated voltages.

Figure 1-2 shows the voltage profile of the output storage capacitor as energy is
harvested from the piezoelectric generator mounted on the shoes, rectified and stored in
the capacitor [2]. In this case, the researchers had implemented the system such that
when the voltage on output capacitor reaches 12V, the energy will be made available to
a linear regulator which generates a 5V output voltage to power the transmitter. This
requirement limits the rate in which data can be transmitted as a person will need to take
several steps in the shoes before enough energy is harvested and stored in the storage
capacitor.

Figure 1-3 shows the DC voltage generated by the piezoelectric-based wind energy
harvester [3] with different wind speed. It can be observed that the voltage generated
has a wide range and it can reach up to 8.8V as the wind speed reaches 6.7m/s. Again,

4


-

a linear regulator is used to generate a stable output voltage to power the system, hence
resulting in a non-operational system during low wind speed conditions.

1-2: Energy harvested from piezoelectric shoes on storage capacitor [2]

1-3: DC voltage generated by piezoelectric harvester with different wind speed [3]
5


-

The piezoelectric based energy harvesters have typically very low efficiency in
harvesting energy from the environment. Hence any energy harvested is precious. In
both systems, the overall system efficiency is degraded further by the choice of a linear
regulator to generate a stable supply as a large voltage drop (hence significant power
loss) can be observed across the pass element in some operating conditions.

However in applications such as [4], where a wireless biological monitoring system is
implemented, the linear regulator will limit its operations. In [4], a free-moving mouse
inside a cage is used for prototype monitoring system design. By employing an inductive
coupling network, a prototype implant device can wirelessly receive an input RF power
from an array of external coils. The received AC voltage is further rectified by a halfwave rectifier to supply DC current. Taking into consideration, the different possible
tilting angles and positions of the mouse, the rectified DC voltage measured ranges from
1.0V to 6.9V in the experiment. In this case, if the bio-implant system requires a 3.0V
operating supply voltage, a linear regulator will not be suitable to provide the regulated
voltage. Instead, a switch-mode dc-dc power converter with both step-up and step-down
capability is required for the application.

-

-

Switch-mode DC-DC power supplies typically have higher conversion efficiency as
compared to linear regulators in most operating conditions. There are numerous types of
switch-mode dc-dc converters, namely buck, boost and buck-boost converters. The
buck-boost converter is best suited for applications involving a wide input supply range,
since it is able to both step-up and step-down the input and provide a stable output
supply. Hence, by implementing a buck-boost converter in place of the linear regulators
6

-

used in the designs, operating conditions for both systems can be further extended, i.e.
the person wearing the energy harvesting shoes will be able to transmit data back to
base more frequently.

Majority of the buck-boost dc-dc converters developed generate a non-inverting
regulated output supply and are designed with a battery input in mind. This offers great
convenience to hardware developers, as the same input supply can be used to power
other subsystems on board. However these buck-boost converters can at most operate
at a minimum supply voltage of 1.8V, i.e. the wind energy harvester can only transmit
data when wind speed is faster than approximately 5m/s. Table 1-1 summarizes a few
dc-dc converters and their performance. It can be observed from the table that only the
boost converter can operate with a low supply voltage of 0.7V and chip manufacturers
have lowered the minimum supply required for the boost converters considerably over
the past few years. These boost converters are designed for ultra-low supply
applications such as those utilizing solar cells. On the other hand, the minimum
operating voltages for buck-boost converters remain relatively high with respect to that of
the boost architecture and they required at least 1.8V to operate. Hence these buckboost converters are not optimized to operate in a system powered by sustainable
energy sources. Furthermore sustainable energy sources have typically different
characteristics as compared to the battery supplies used in all portable devices. In most
cases, the outputs from the sustainable energy sources cannot be used directly to power
the system as they need to be further regulated. Therefore a buck-boost converter which
generates an inverting output may not pose too much of inconvenience to the system
designers.

7


-

In this project, a buck-boost converter catering to sustainable energy sources,
particularly for piezoelectric wind energy harvester will be designed. This buck-boost
converter is aimed to operate with a lower supply voltage, closer to the range achieved
in boost converters recently. Also, since applications utilizing sustainable energy sources
typically consume little power, the proposed chip will be designed to cater to a maximum
load of 25mA. Different architectures of the buck-boost converters will be examined in
the next chapter and the one which is most suited for this application will be probed
further. Subsequent chapters will cover the design of the sub-blocks in the startup and
regulatory control systems required in the proposed chip. Finally, in the last chapter, the
simulated performance of the buck-boost converter will be discussed.

[5]

[6]

- [7]

[8]

Type

Buck-Boost

Buck-Boost

Buck-Boost

Boost

Inverting/
Non-inverting

Non-Inverting

Non-Inverting

Non-Inverting

Non-Inverting

Minimum VDD

2.5V

1.8V

2.7V

0.7V

Maximum VDD

3.2V

5.5V

10.0V

5.5V

Quiescent Current

Not Specified

16µA

86µA

5µA

Max Load Current

800mA

260mA

500mA

100mA

1-1: DC-DC converters summarized performance

8


-

CChhaapptteerr 22

Buck-Boost Converter Topologies
The buck-boost converter provides a solution to applications with wide input power
supply ranges by stepping up or down the input supply to generate a regulated supply
voltage. There are many buck-boost converter topologies [9], [10], [11] which have been
developed over the years. Each of these topologies has been designed to meet the
requirements for the different applications. In this chapter, some of these topologies will
be presented and their basic operations concepts will be discussed. Based on the
discussions and evaluations on the topologies presented, the one which best suits the
requirements of the proposed chip and applications will be chosen for implementation

-

2-1: Conventional Inverting Buck-Boost Converter [9]
9


One of the simplest buck-boost topology is that of the conventional inverting buck-boost
converter which is shown in figure 2-1. The setup is simple and requires the same
number of external components as a buck or a boost converter. It involves an inductor, a
capacitor, a MOS switch and a diode, which in actual implementation is replaced by a
MOS switch, so as to reduce the conduction loss. However, a major setback of this
topology, as its name implies, is that it provides an inverted output supply voltage. It can
be observed from figure 2-1 that the input voltage source is inverted so that the output
regulated voltage is positive. This implies that no other circuitries in the system will be
able to use the input voltage directly.

The basic operations of the conventional inverting buck-boost converter can be divided
into 2 modes, i.e. Continuous Conduction Mode (CCM) and Discontinuous Conduction
Mode (DCM), which is determined by the continuity of the inductor current.

Under steady state condition, i.e. when the output regulated voltage, Vout has settled
down to its desired level for a given load, when the switching transistor is turned on for a
duration ton,

Vdiode = −VS

(2.1)

The diode is reversed biased for a given positive output regulated voltage Vout and the
inductor increases linearly from IL,1 to IL,2 in time ton such that

VS = L

I L,2 − I L,1
ton

ton =

=

L∆I L
VS

L∆I L
ton

(2.2)

(2.3)

When the switching transistor is subsequently switched off at time t = ton for a duration of

T - ton, where T is the switching period, the voltage at Vdiode reverses in polarity so as to
keep the inductor current flowing. Hence if VS is positive, Vdiode will become positive
during this period, thereby forward biasing the diode and transferring the energy stored
in the inductor coil during ton, to the load. During this period, the inductor current falls
linearly from IL,2 to IL,1, since in steady state condition

− Vout = − L

I L,2 − I L,1
T − ton

=−

L∆I L
T − ton

(2.4)

Defining turn-on period ton to be DT, where D is the controlled duty ratio. Manipulating
equations (2.2) and (2.4), the output regulated voltage can be expressed as

Vout =

D
VS
1− D

(2.5)

Hence for a given input supply voltage VS, the turn-on duration of the switching transistor
can be controlled so as to obtain the desired output voltage. For example if the input
supply voltage is at 5V, D can be controlled to be 0.3333 so as to obtain an output
voltage of 2.5V. In this case, the converter is operating in the buck-mode, stepping down
the input voltage. It should be noted that the above derivations are made using the
assumptions that the converter is operating in ideal conditions and there is no power
losses. Hence the duty cycle D obtained in practical implementations will differ from that
obtained from (2.5).

Using an inductor of 4.7µH and output capacitor of 4.7µF (Note that the inductance and
capacitance values used for the ideal simulations performed in this chapter will be the
same, unless otherwise stated), the profiles observed at the various nodes of an ideal,


open-loop inverting buck-boost converter operating in the buck mode under CCM
operations (VS = 5.0V and Vout = 2.5V) are obtained as shown in figure 2-2.

V(

)

I(

I(

V(

)

)

)

V(

)

)

2-2: Ideal CCM operation of inverting buck-boost converter (VS=5.0V, Vout=2.5V)
Similarly, using equation (2.5), an input supply voltage VS of 1.0V can be boosted up to
an output voltage Vout of 2.5V by controlling D to be 0.714. Figure 2-3 shows the
simulation results when the ideal open-loop inverting buck-boost converter operates in
boost mode under CCM operations (VS = 1.0V and Vout = 2.5V). Using equations (2.2)
and (2.4) and assuming that the converter is lossless (ideal), the peak-to-peak inductor
current IL and peak-to-peak output ripple voltage can be derived

VS DT
L

(2.6)

I load DT
Co

(2.7)

∆I L =

∆Vout =