Design of self tuning frequency synthesizer

DESIGN OF A SELF-TUNING
FREQUENCY SYNTHESIZER

WEE TUE FATT DAVID
(B.ENG. (FIRST CLASS), UNSW)

A THESIS SUBMITTED
FOR THE DEGREE OF MASTER OF ENGINEERING
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
NATIONAL UNIVERSITY OF SINGAPORE
2005


Name: Wee Tue Fatt David
Degree: Master of Engineering
Department: Electrical and Computer Engineering
Thesis Title: Design of a Self-Tuning Frequency Synthesizer

Summary

This thesis describes the design and implementation of a self-tuning frequency
synthesizer. The aim is to design a frequency synthesizer that is able to self-tune when
there is a process, temperature and voltage variation. This allows the designers to
design a low gain frequency synthesizer system, which produces a low phase noise
without process variation constraint. The simulation results and the experimental
results are presented in this report. The frequency synthesizer is fabricated in a 0.25
µm six level metal Silicon Germanium (SiGe) process. With a supply voltage of 2.5 V,
the test results show that the frequency synthesizer is able to calibrate itself even
though there is a frequency drift of around 250 MHz in the Voltage Controlled
Oscillator (VCO). The measured phase noise of the frequency synthesizer is -81.50
dBc at 10 kHz offset.

Keywords:
Frequency Synthesizer, Self-Tuning, Transceiver, LC Oscillator, Phase Lock Loop
(PLL).

i


Acknowledgements

I would like to use this opportunity to thank my supervisor, Professor Xu Yong Ping
for his guidance and advises during the period of my research work. In addition, I
would also like to thank him for accepting my proposed idea for this thesis.

Next, I would like to express my appreciation to my manager, Mr. Chee Piew Yoong
and colleagues in the Institute for Infocomm Research (I2R) for their valuable advices
and technical discussion during the period of the project.

Finally yet importantly, I would like to thank my family members for their
encouragement and support during this period.

ii


Table of Contents

List of Figures ................................................................................................................. v
List of Tables ...............................................................................................................viii
1.

2.

3.

Introduction............................................................................................................. 1
1.1.

Background and Motivation ........................................................................... 1

1.2.

Aims and Scope .............................................................................................. 4

1.3.

Organization of Thesis .................................................................................... 6

Frequency Synthesizer ............................................................................................ 7
2.1.

Basic Concept of the Frequency synthesizer .................................................. 7

2.2.

Phase Detector Characteristics........................................................................ 8

2.3.

VCO Characteristics ..................................................................................... 10

2.4.

Linear Model of the Frequency Synthesizer................................................. 12

2.4.1.

Dynamic Response of Frequency Synthesizer...................................... 12

2.4.2.

Static Phase Error.................................................................................. 16

2.5.

Noise Analysis of the Frequency Synthesizer System.................................. 18

2.6.

Relationships of Design Parameters ............................................................. 21

Design of Frequency Synthesizer ......................................................................... 23
3.1.

System Architecture...................................................................................... 23

3.2.

Self tuning Circuit Design ............................................................................ 27

3.2.1.

Frequency Synthesizer Tuning Range .................................................. 27

3.2.2.

Self-Tuning Concept ............................................................................. 31

3.3.

Simulation Result.......................................................................................... 34
iii


4.

5.

Circuit Level Design ............................................................................................. 39
4.1.

Phase Frequency Detector............................................................................. 39

4.2.

Charge Pump................................................................................................. 41

4.3.

Voltage Controlled Oscillator ....................................................................... 45

4.4.

Self-Tuning Circuit ....................................................................................... 58

4.5.

Divider .......................................................................................................... 59

4.6.

System Simulation Results ........................................................................... 65

4.7.

Layout Design and Considerations ............................................................... 68

4.8.

Floor Plan of the Frequency Synthesizer ...................................................... 70

Measurement Result.............................................................................................. 71
5.1.

Measurement Setup....................................................................................... 71

5.2.

Measurement Result...................................................................................... 72

5.2.1.

VCO Tuning Voltage Characteristic..................................................... 73

5.2.2.

Frequency Synthesizer Phase Noise Performance ................................ 77

5.2.3.

Measured Result of Self-Tuning Circuit............................................... 81

5.3.
6.

Discussion of Result ..................................................................................... 83

Conclusions........................................................................................................... 84
6.1.

Conclusion .................................................................................................... 84

6.2.

Future Work .................................................................................................. 85

References..................................................................................................................... 87
Appendix A................................................................................................................... 91
Appendix B ................................................................................................................... 93

iv

List of Figures

Figure 1-1 Frequency Synthesizer Design Factors ......................................................... 3
Figure 2-1 Basic Frequency synthesizer ......................................................................... 8
Figure 2-2 Characteristic of an ideal phase detector....................................................... 9
Figure 2-3 Model of Phase Detector............................................................................... 9
Figure 2-4 Characteristics of an ideal VCO.................................................................. 10
Figure 2-5 Model of VCO............................................................................................. 11
Figure 2-6 Linear Model of Frequency Synthesizer ..................................................... 12
Figure 2-7 Open loop and Closed loop response of Frequency Synthesizer ................ 14
Figure 2-8 Single-pole RC loop filter ........................................................................... 14
Figure 2-9 Frequency Response of 2nd order Frequency Synthesizer (ζ = 0.707) ....... 16
Figure 2-10 Linear model of Frequency Synthesizer with added noise sources .......... 19
Figure 3-1 Local Oscillator System Diagram ............................................................... 23
Figure 3-2 Typical Direct Up and Down Conversion Topology in Transceiver .......... 24
Figure 3-3 Frequency of Operation for Mode 1 Device [17]........................................ 25
Figure 3-4 System Architecture of Frequency Synthesizer .......................................... 26
Figure 3-5 Typical Tuning Range Curve of Oscillator................................................. 29
Figure 3-6 Tuning Voltage of Proposed System........................................................... 32
Figure 3-7 Flow Chart of Tuning Circuit...................................................................... 33
Figure 3-8 Block Diagram of Tuning Circuit ............................................................... 33
Figure 3-9 Third Order Low Pass Filter ....................................................................... 34
v


Figure 3-10 Gain and Phase Margin of Frequency Synthesizer ................................... 37
Figure 3-11 System Phase Noise Simulation................................................................ 38
Figure 4-1 Schematic Diagram of Phase Frequency Detector...................................... 40

Figure 4-2 PFD State Diagram ..................................................................................... 40
Figure 4-3 PFD Simulation Result................................................................................ 41
Figure 4-4 Schematic of Charge Pump ......................................................................... 43
Figure 4-5 Charge Pump Current Mismatch Simulation Result................................... 44
Figure 4-6 Expanded View of the Current Mismatch Simulation Result..................... 44
Figure 4-7 Schematic of LC Oscillator ......................................................................... 47
Figure 4-8 Oscillator Small Signal Equivalent Circuit ................................................. 48
Figure 4-9 VCO Tuning Range (Typical Process Corner) ........................................... 54
Figure 4-10 Post Layout VCO Tuning Range (Typical Process Corner) ..................... 56
Figure 4-11 VCO Phase Noise...................................................................................... 57
Figure 4-12 Schematic of Self-tuning Controller ......................................................... 59
Figure 4-13 Divider Block Diagram ............................................................................. 60
Figure 4-14 ECL D-Flip Flop ....................................................................................... 61
Figure 4-15 Master/Slave ECL D Flip Flop ................................................................. 61
Figure 4-16 Divider by Three Counter ......................................................................... 63
Figure 4-17 Simulation result of Divider Output.......................................................... 64
Figure 4-18 Output of Divider (44MHz) ...................................................................... 65
Figure 4-19 Control Voltage of Frequency Synthesizer (Based on VCO and LPF) .... 67
Figure 4-20 Control Voltage of Frequency Synthesizer ............................................... 68
Figure 4-21 Proposed Layout Plan ............................................................................... 69
vi


Figure 4-22 Die Micrograph ......................................................................................... 70
Figure 5-1 Test board Setup.......................................................................................... 72
Figure 5-2 Measured VCO Tuning Characteristics ...................................................... 75
Figure 5-3 VCO Tuning Voltage Characteristics ......................................................... 77
Figure 5-4 Lock Detect Signal ...................................................................................... 78
Figure 5-5 Control voltage, VCNTRL Signal Response .............................................. 79
Figure 5-6 Measured Frequency Synthesizer Output Spectrum at 4.224 GHz............. 79

Figure 5-7 Self-Tuning Transient Response ................................................................. 82
Figure Appendix B-1 VCO Tuning Range (Slow Process Corner) .............................. 93
Figure Appendix B-2 VCO Tuning Range (Fast Process Corner) ............................... 93
Figure Appendix B-3 Post Layout VCO Tuning Range (Slow Process Corner).......... 94
Figure Appendix B-4 Post Layout VCO Tuning Range (Fast Process Corner) ........... 94
Figure Appendix B-5 Spectrum Analyzer’s Phase Noise Configuration ..................... 95
Figure Appendix B-6 Measured Frequency Synthesizer Phase Noise @ 10 kHz ........ 95
Figure Appendix B-7 Measured Frequency Synthesizer Phase Noise @ 100 kHz ...... 96
Figure Appendix B-8 Measured Frequency Synthesizer Phase Noise @ 1 MHz ........ 96
Figure Appendix B-9 Measured Frequency Synthesizer Phase Noise @ 10 MHz ...... 97

vii


List of Tables

Table 2-1 Cause and Effect of Increased KPD ............................................................... 22
Table 3-1 Technical Specification of Frequency Synthesizer ...................................... 25
Table 3-2 Different Standard Absolute and Relative Tuning Range ............................ 28
Table 3-3 Frequency Spread due to Process variation.................................................. 30
Table 3-4 System Phase Noise for different KVCO Setting............................................ 35
Table 3-5 Filter Parameter for Different KVCO Setting ................................................. 36
Table 3-6 Frequency Synthesizer Parameters............................................................... 36
Table 3-7 System Phase Noise Result .......................................................................... 37
Table 4-1 Current Mismatch Data ................................................................................ 45
Table 4-2 Effect of VCO Frequency on Process Skew Parameter ............................... 49
Table 4-3 Overlap Frequency (Schematic Simulation Result) ..................................... 50
Table 4-4 KVCO Gain for Different Setting (Schematic Simulation Result) ................. 51
Table 4-5 Overlap Frequency (Post Layout Simulation Result)................................... 52
Table 4-6 KVCO Gain for Different Setting (Post Layout Simulation Result) .............. 52

Table 4-7 VCO Schematic Simulation Result .............................................................. 53
Table 4-8 VCO Post Layout Simulation Result............................................................ 55
Table 4-9 VCO Phase Noise ......................................................................................... 57
Table 4-10 State Table of a Divider-by-Three counter................................................. 62
Table 4-11 Flip-Flop Input Table ................................................................................. 62
Table 5-1 VCO Tuning Voltage Measurement Result ................................................. 73
viii


Table 5-2 Measurement Overlap Frequency................................................................. 74
Table 5-3 KVCO Gain for Different Setting (Measurement Result)............................ 74
Table 5-4 Summarized Result between Simulation and Measurement ........................ 76
Table 5-5 Overlap Frequency Comparison................................................................... 76
Table 5-6 KVCO Gain Comparison ................................................................................ 76
Table 5-7 Measured Frequency Synthesizer Noise Performance ................................. 80
Table 5-8 Phase Noise Comparison.............................................................................. 81
Table 5-9 Measured Crystal Oscillator Phase Noise Performance ............................... 81
Table 5-10 Frequency Synthesizer Desired Frequency Band of operation .................. 82

ix


CHAPTER 1: Introduction

1. Introduction

1.1.

Background and Motivation

The Frequency synthesizer is one of the most important building blocks in integrated
communication systems as it is used to provide an accurate frequency source for
up/down conversion, modulation and demodulation in any transceiver system. It can
also be used to provide clock conversion, clock generation and timing references in
integrated systems. Frequency synthesizer design remains one of the most challenging
designs in Radio Frequency (RF) systems because it must meet very stringent
requirements [1]. In recent years, there are growing requirements to integrate the entire
transceiver systems on a single silicon chip [2]-[4]. This is due to the advancement of
Complementary Metal Oxide Semiconductor (CMOS) semiconductor technology in
the past decade. This advancement in sub micron technology allows manufacturers to
integrate the entire transceiver systems on a single silicon chip, which leads to a rapid
growth in the communication.

The higher scales of integration have created new constraints and tighten the design
requirements for circuit designers, who are designing frequency synthesizer. Figure
1-1 shows the factors that designers have to take into consideration when designing
frequency synthesizers. Although these factors listed in Figure 1-1 influence the
design, circuit designer do not have control in factors like technology, communication
1


CHAPTER 1: Introduction
specifications and supply voltage. The choice of technology uses greatly depends on
factors like cost of the product, performance objectives, production capacity, time to
market and other commercial strategies rather than on the circuit design. On the other
hand, standard for voice and data applications like Global System for Mobile
Communication (GSM), Digital European Cordless Telephone (DECT), Personal
Communication Services (PCS), 802.11 Wireless Local Area Network (WLAN),
Bluetooth and so on will predefined the communication specification and supply
voltage. From the standard, the system engineer will specifies the design specification

like frequency, tuning range, phase noise, and so on for the frequency synthesizer.
Although these three factors are not within the control of the designers, they have great
influence on the design process. This is especially so for technology factor, as supply
voltage is closely inter-related with advancement of technology. With each scaling of
technology node1, the power supply of the system has to be scaled down as well [5].
The scaling down of the supply voltage would therefore reduce the dynamic range of
voltage that can be used in the design. This will increases the complexity of the
frequency synthesizer design in low voltage domain.

In addition, circuit designers have to consider additional parameters like supply
voltage variation, temperature and process variation. Circuit designers have to ensure
that the frequency synthesizer is able to work according to the specifications that are
defined by the system engineer. In order to ensure that the frequency synthesizer is

1

Technology node is use to describe generations of semiconductor processing technology by

international Technology Roadmap for Semiconductors (ITRS)

2


CHAPTER 1: Introduction
able to meet the specification, circuit designers would therefore have to modify or
simulate a circuit several times before a satisfactory result can be achieved. This
process is time consuming. This is especially true for process variation, which depends
on the foundry process. The foundry will normally provide the limits of the process at
which the wafer will be rejected. In another word, these limits do not provide much
insight in circuit design as they simply demonstrate a lack of robustness in the process

[6]. Even though, there is many efforts being spend in the foundry to improve the yield
of the process. This process variation issue will always haunt circuit designer. Thus,
designers need to run many simulations to make sure every circuit are working within
the limitation of the process and this took a huge amount of simulation time.
Sometime, the circuit fails to meet the specification due to process variation.

Figure 1-1 Frequency Synthesizer Design Factors

A major challenge for circuit designers is to find ways to design the frequency
synthesizer with tightening constraints and ever-increasing stringent requirement for
3


CHAPTER 1: Introduction
communication system. Since circuit designers do not have control on the supply
voltage, specification of communication system and technology, designers have to
focus on supply voltage variation, temperature and process variation factors and find
ways in the circuit design to minimize the effect of these three factors in fulfilling the
requirement of the specification. One good example is the gain of the oscillator uses in
the design of the frequency synthesizer as it has great impact on the noise performance
of the frequency synthesizer. Furthermore, with reducing dynamic range, gain of the
Voltage Controlled Oscillator (VCO) will increase due to the fact the VCO must cover
the same range of the frequency in the same communication system. This would
increases the phase noise of the frequency synthesizer, which will have a major impact
on the specification of the communication system, as phase noise is one of the most
important factors in defining the specification of the frequency synthesizer. The
challenge for circuit designers is to take care of the various factors and come out with
an innovative design that can meet specification of the communication system.

1.2.

Aims and Scope

Since noise from charge pump and loop amplifier is amplified by the VCO gain around
the loop bandwidth. VCO gain is usually large because of limited control voltage range
and large frequency range required by the application. In addition, designer need to
design the VCO gain to be larger than the intend application due to the fact of
constraint posed by voltage, temperature and process variation. Normally, the gain of

4


CHAPTER 1: Introduction
the VCO will normally impose the limit of the noise performance of the frequency
synthesizer.

This research focuses on the design technique to reduce phase noise and improve the
system noise performance of the frequency synthesizer. The design technique reduces
the effect of the VCO dependence on factors like process variation, temperature and
supply voltage variation. This would allow a designer to concentrate on the design of
the frequency synthesizer based on the communication specification instead

The effect of reduced supply voltage, process, temperature and voltage variation on the
gain of the VCO on the design of the frequency synthesizer are investigated in this
thesis and a solution to reduce the dependence on these factors is presented as well. To
verify the effectiveness of the design technique, a self-tuning frequency synthesizer
was designed and fabricated in a 0.25 µm IBM SiGe process [7]. Although the process
allows the use of bipolar devices, only CMOS devices are used to design the entire
frequency synthesizer, as this is the project requirement. The frequency synthesizer is
able to self-tune the output frequency of the VCO to the desired frequency when the

system starts up. This allows the designer to design a low gain VCO, which results in
better noise performance. The major achievement of this work is that designer does not
have to over design the gain of the VCO to cover for reduced tuning voltage, process
variation and operation condition but just concentrate on the specification of the VCO
based on communication specification. Thus, the phase noise will be better compared
to a system that has to consider these factors. In other words, the phase noise will be
lower compared to a system that has to consider these factors. A self-tuning block has
5


CHAPTER 1: Introduction
been implemented to the traditional Frequency Synthesizer to reduce the VCO gain
effect to improve the ease of designing VCO based on communication specification
rather than include the effect of process, voltage and temperature variation in the
design of the VCO.

1.3.

Organization of Thesis

This thesis is organized into six chapters. In this chapter, the background and aim of
this thesis is presented. In Chapter 2, the basic concept and the characteristics of the
frequency synthesizer will be discussed. In Chapter 3, the idea and design of the
frequency synthesizer for this thesis will be presented. In Chapter 4, the circuit level
design of the major blocks in the frequency synthesizer will be presented. There will
be a discussion on the simulation result and problems faced during the implementation
of the frequency synthesizer. In Chapter 5, the test results of the frequency synthesizer
are presented. Finally, the conclusion of the thesis will be presented in Chapter 6.

6

CHAPTER 2: Frequency Synthesizer

2. Frequency Synthesizer

Modern communication systems use frequency synthesizers for quite a number of
purposes, namely to recover the clock from digital data signals, synthesize frequencies
for receiver tuning, recover the carrier signal from satellite transmission signals, and
perform frequency and phase modulation. In this chapter, an overview and analysis of
the frequency synthesizer will be discussed. In addition, the basic concept of the
frequency synthesizer will be presented and equations for the various building blocks
will be derived. After that, the dynamic response of the frequency synthesizer is
introduced and the parameters that affect the design of frequency synthesizer are
presented. Finally, the noise analysis of the frequency synthesizer is being studied.

2.1.

Basic Concept of the Frequency synthesizer

PLL based frequency synthesizer has a frequency divider in the feedback loop. The
basic frequency synthesizer system is shown in Figure 2-1. It consists of a phase
detector, low pass filter, voltage controller oscillator and a divider [8]. A frequency
synthesizer is a feedback system with its main purpose to ensure the output signal, θout,
tracks the input signal, θi. The input and output signal of the system can be in
frequency or phase. The system is considered locked when the output signal is equal to
the input signal over a period of time.

7

CHAPTER 2: Frequency Synthesizer

Figure 2-1 Basic Frequency synthesizer
The purpose of the phase detector is to compare the phase of the divided output signal,
θo, with the phase of the input signal, θi. The phase detector will develop a voltage
proportional to the phase difference. This voltage, VD is applied to a low pass filter,
which will determine the bandwidth of the system as well as to reduce the high
frequencies phase error. The voltage at the low pass filter, VLPF is applied to the
voltage-controlled oscillator to adjust the oscillator frequency. Through the feedback
system, the system will ensure both the phase and the frequency of the oscillator are
locked to the phase and frequency of the input signal.

2.2.

Phase Detector Characteristics

An ideal phase detector produces an output voltage proportional to the difference
between the phases of two input signals, which are periodic [9]. The typical phase
detector characteristic is shown in Figure 2-2. It is assumed that when ∆θ is equal to
zero, the phase of the output signal, θo, is equal to the phase of the input signal, θi.

8


CHAPTER 2: Frequency Synthesizer
VOUT
VOUT

Figure 2-2 Characteristic of an ideal phase detector

With the above assumption, the phase error, ∆θ, (specified in radians) is defined as
∆θ = θ i − θ o

(2-1)

The gain of the phase detector, KPD (specified in Volts/radians) is expressed as
K PD ≡ d VOUT / d∆θ

(2-2)

In the linear region, the phase detector voltage, VOUT (specified in Volts) is modeled
by
VOUT = K PD ∆θ

(2-3)

that is represented by the model representation shown in Figure 2-3.

VOUT

Figure 2-3 Model of Phase Detector

9


CHAPTER 2: Frequency Synthesizer

2.3.

VCO Characteristics

An ideal VCO will generate a periodic output signal whose frequency is a linear
function of a control voltage, VC. The frequency of the VCO will increase or decrease
depending on the control voltage, VC. A typical characteristic of a VCO is shown in
Figure 2-4.

ωo

ω

fr

VC

Figure 2-4 Characteristics of an ideal VCO
It can be noticed from the VCO characteristics that the VCO will still generate a
periodic signal even though the control voltage, VC is equal to zero. This frequency is
called the free running frequency, ωfr of the VCO. This indicates that the VCO
frequency does not need to approach zero for practical range of VC. The output
frequency of the VCO, ωo, (specified in radian/s) is expressed as
ωo = K VCO VC + ω fr

(2-4)

where KVCO (specified in radians/s/V) is the gain of the VCO.

10


CHAPTER 2: Frequency Synthesizer

From equation (2-4), it can be noticed that changes in the output frequency are a
function of the control voltage, VC that is applied to the VCO. This relationship is very
important when modeling the relationship between the VCO’s input control voltage
and the phase of its output signal [10]-[11]. The VCO model that is going to be
presented is a small signal model, which relates changes about an operation point. As
the free running frequency, ωfr does not changes with the control voltage, as it is a nonchanging bias term [10], the term ωfr can be ignored in the modeling of the VCO, thus
the output frequency, ωo is expressed as
ωo = K VCO VC

(2-5)

dθ
dt

(2-6)

Since ω =

The phase of the VCO can be obtained by integrating VCO’s output frequency [13]
θ o ( t ) = ∫ ω o ( t )dt

(2-7)

If Laplace transform is performed on (2-7), equation (2-7) is expressed as

θ o (s) =

ω o (s) K VCO
=
VC (s)

s
s

(2-8)

where s is jω.
which is represented by the model representation shown in Figure 2-5.
θ o (s)

Figure 2-5 Model of VCO

11


CHAPTER 2: Frequency Synthesizer

2.4.

Linear Model of the Frequency Synthesizer

The description and basic concept of the phase detector and VCO have been covered in
previous two sections. As a result of the derivation of the linear models of the phase
detector and VCO in the previous section, the linear model of the frequency
synthesizer will be illustrated in this section under the assumption that ∆θ and ωo stay
in the linear range of the phase detector and VCO [14]. When the loop is locked, the
phase of the divided output signal θo accurately tracks the phase of the reference signal
θi. The linear model of frequency synthesizer is shown in Figure 2-6.

VOUT

Figure 2-6 Linear Model of Frequency Synthesizer
With the help of the linear model, the dynamic response and the static phase error will
be presented in the next two sections.

2.4.1. Dynamic Response of Frequency Synthesizer

With reference to Figure 2-6, the open loop and closed loop transfer function of the
frequency can be derived. With the derived transfer function, the dynamic response of

12


CHAPTER 2: Frequency Synthesizer
the frequency synthesizer can be studied and this facilitates the design of the frequency
synthesizer in this thesis.

The divided output phase of the frequency synthesizer is expressed as

θ o (s) =

∆θ K PD F(s)K VCO
sN

(2-9)

In addition, the phase transfer function or closed loop response is expressed as

H(s) =

θ o (s)

KF(s)
=
θ i (s) S + KF(s)

where K =

(2-10)

K PD K VCO
N

The open loop transfer function of the frequency synthesizer is expressed as

H OL (s) =

θ o (s) KF(s)
=
θ i (s)
s

(2-11)

The open loop and closed loop response of the frequency synthesizer when |F(s)| =1 is
plotted in Figure 2-7. The frequency synthesizer bandwidth is defined as the frequency
when the open-loop gain drops to unity and it is determined by the open loop gain, K.

13


CHAPTER 2: Frequency Synthesizer

H (s )

s

Figure 2-7 Open loop and Closed loop response of Frequency Synthesizer

It can be noticed that the 3dB point of the closed loop response of frequency
synthesizer depends on the open loop gain K as well. The above case describes the
closed loop response of the frequency synthesizer when |F(s)| =1. Now, a single pole
RC loop filter, which is shown in Figure 2-8 is added to the closed loop system.

R

VIN

VOUT
C

Figure 2-8 Single-pole RC loop filter

14


CHAPTER 2: Frequency Synthesizer
The transfer function of the loop filter is expressed as followed:

F(s) =

ω LPF
1

=
1 + sRC s + ω LPF

where ω LPF =

(2-12)

1
RC

The closed loop transfer function of the frequency synthesizer becomes

H(s) =

Kω LPF
s + sω LPF + Kω LPF

(2-13)

2

By adding the single pole filter, the frequency synthesizer system becomes a secondorder system. In circuit and control theory, it is common practice to write the
denominator of the transfer function in s 2 + 2ζω n s + ω 2n form, where ζ is the damping
factor and ωn is the natural frequency of the system [13]. Thus, Equation (2-13) is
expressed as followed:
ω 2n
H(s) = 2
s + 2ξω n s + ω 2n

(2-14)

where

ω n = ω LPF K

ξ=

(2-15)

1 ω LPF
2
K

(2-16)

From the above equations, it can be seen that ωn is the geometric mean of the -3dB
bandwidth of the LPF and the loop gain, K. In addition, the damping factor, ζ is
inversely proportional to the square root of the loop gain. The frequency response of

15