FPGA BASED DESIGN AND IMPLEMENTATION FOR OPTICAL TRANSPORT NETWORKS

VIETNAM NATIONAL UNIVERSITY - HO CHI MINH CITY
UNIVERSITY OF SCIENCE

HA VAN KHA LY

FPGA-BASED DESIGN AND IMPLEMENTATION
FOR OPTICAL TRANSPORT NETWORKS

Master Thesis in Electronic Engineering
(Specification in Microelectronics & IC Design)

SUPERVISOR: Dr. BUI HUU PHU

HCM CITY, 2010

ii


ACKNOWLEDGEMENT

I gratefully acknowledge the following individuals for helping me to complete
my thesis report.
First of all, I would like to take this opportunity to express my deepest
gratitude to my supervisor, Dr. Bui Huu Phu, for his guidance, help and support the
theory and concept of fiber optical system design and encouragement throughout
the period of completing my project.
Thanks to all of my lecturers in HCM University of Science such as Prof. Dr.
Dang Luong Mo, Prof. Dr. Nguyen Huu Phuong, Prof. Dr. Dinh Si Hien, Dr. Bui
Trong Tu and Dr. Huynh Huu Thuan for their knowledge of the microelectronic, IC
design and their patiences during my master course. I have learned a lot from them.
I would like to thank to my brother, Dr. Ha Hoang Kha, for all his help me

through my thesis, especially in providing me the IEEE papers and the related
softwares.
I acknowledge the kindly supports from Arrive Technologies Viet Nam. The
thesis might be impossibe without the supports from the company. Particularly, I
also would like to thank Mr. Do Dinh Duc for his kind assistant, suggestion on
explaining FPGA implementation, and for providing an excellent atmosphere at
Arrive technologies Lab, and guidance especially in using AT FPGA board version
1.0 development board and configuration of the related software.
Finally, I sincerely thank to all my friends and all those whoever has helped
me either directly or indirectly in the completion of my final year project and thesis.

1


ABSTRACT
The thesis presents an approach to system design and implementation for
optical transport networks. The design of the system based on the Field
Programmable Gate Array (FPGA) and Gigabit optical network is discussed.
Gigabit optical network interfaces provide fixed functionality and are optimized for
sending and receiving large packets. All modules are designed using Verilog
Hardware Description Language (HDL) and implemented using AT FPGA board
version 1.0. The board is connected to computer and Quartus II Version 8.0 is used
to design, compile and implement for the hardware. All processing is executed in
AT FPGA version 1.0 board and only requires the input data to the hardware
throughout interfaces. To test and analyse results, input and output data are
displayed to computer, and the results are compared using HyperTerminal or Telnet
command. Softwares and tools used in this project include Verilog HDL Design
Entry Altera Quartus II 8.0. Some software tools are used to assist the design
process and downloading process into Altera FPGA chip Stratix II EP2S180, while
AT FPGA board version 1.0 is used to implement the designed module. The

experimental results at Gigabit Ethernet receiving interface indicate that the optical
interface can receive all packet sizes and store them in SDRAM at Gigabit Ethernet
line rate.

2


TABLE OF CONTENTS
ABSTRACT .............................................................................................. 2

CHAPTER 1 : INTRODUCTION ............................................................................ 9
1.1
1.2
1.3
1.4

Introduction .............................................................................................. 9
Project objectives .................................................................................. 11
Project scope ......................................................................................... 11
Thesis outline ........................................................................................ 12

CHAPTER 2 : FPGA AND HDL CHIP DESIGN ............................................... 14
2.1
2.2
2.3
2.4

Introduction ............................................................................................ 14
FPGA architecture overview ............................................................... 15
Stratix II FPGA ...................................................................................... 17

Hardware description language .......................................................... 21
2.4.1 Introduction .............................................................................. 21
2.4.2 Verilog HDL Structure ............................................................ 22

CHAPTER 3 : PRINCIPLES AND APPLICATIONS OF OPTICAL
COMMUNICATIONS ................................................................... 30
3.1
3.2
3.3

Optical fiber communication technology ........................................... 30
System overview, trends and advances ........................................... 34
Standard and devices requirements .................................................. 37
3.3.1 Standard ................................................................................... 37
3.3.2 Devices requirements ............................................................ 41

CHAPTER 4 : FPGA-BASED DESIGN AND IMPLEMENTATION............... 47
4.1
4.2
4.3

4.4

Overview of the design ........................................................................ 47
Software design .................................................................................... 51
Hardware design ................................................................................... 52
4.3.1 High speed 8B/10B Encoder and Decoder Design ........... 66
4.3.2 Details of the Encoding Process .......................................... 67
4.3.3 FIFO Functionality .................................................................. 72
Download the design into hardware .................................................. 78

CHAPTER 5 : SIMULATION RESULTS AND EXPERIMENTAL TESTS ON
FPGA CHIPS ................................................................................ 80
5.1
5.2

5.3

Introduction ............................................................................................ 80
Individual component test .................................................................... 80
5.2.1 8B/10B encoder and decoder implemetation and
simulation results .................................................................... 80
5.2.2 FIFO Implemetation and simulation results ........................ 86
5.2.3 System compilation ................................................................ 93
5.2.4 Breadboard prototype test ..................................................... 94
System level testing for transmitter and receiver............................. 97
5.3.1 Optical link test ........................................................................ 97
5.3.2 Gigabit Ethernet test .............................................................. 97

CHAPTER 6 : CONCLUSION AND FUTURE WORK ................................. 100
6.1
6.2

Conclusion ........................................................................................... 100
Future work .......................................................................................... 101

REFERENCES ..................................................................................................... 102

3

List of Figures
Figure 2.1: Structure of an FPGA...................................................................................... 15
Figure 2.2: SRAM-controlled Programmable Switches. .................................................... 16
Figure 2.3 : Actel Antifuse Structure. ................................................................................ 17
Figure 2.4: Top view Stratix II. .......................................................................................... 18
Figure 2.5: Stratix II Block Diagram. ................................................................................. 19
Figure 2.6: 1,020-PIN FPGA Package Outline.................................................................. 20
Figure 2.7: Verilog ............................................................................................................. 21
Figure 3.1: Optical transmitter and receiver. ..................................................................... 31
Figure 3.2: Fiber to the X (FTTX) ...................................................................................... 33
Figure 3.3: Enterprise LAN Topology ................................................................................ 33
Figure 3.4: Today’s networks ............................................................................................ 34
Figure 3.5: Total Traffic Bandwidth Increases................................................................... 35
Figure 3.6: Convergence of Ethernet and Optical transports ............................................ 35
Figure 3.7: Overview of optical transport networks ........................................................... 36
Figure 3.8: Relationship of IEEE 802.3 layering model to OSI reference model .............. 39
Figure 3.9: SPLC-20-4-X-BX............................................................................................. 41
Figure 3.10: Diagram of host board connector block pin numbers and names................. 42
Figure 3.11: Block diagram of SFP ................................................................................... 44
Figure 3.12: Single-mode fiber and multimode fiber ......................................................... 45
Figure 3.13: HDMP-1636A/46A/T1636A transceiver ........................................................ 46
Figure 4.1: Design flow using Quartus II ........................................................................... 48
Figure 4.2: Design flow ..................................................................................................... 48
Figure 4.3: Full IC Design Flow ......................................................................................... 51
Figure 4.4: Quartus II Software Basic Design Flow .......................................................... 52
Figure 4.5: Stratix II block diagram ................................................................................... 54
Figure 4.6: Top-level block diagram of the system ........................................................... 55
Figure 4.7: FPGA Stratix II ................................................................................................ 56
Figure 4.8: Block diagram of Gigabit Ethernet .................................................................. 57

Figure 4.9: Block diagram of MAC .................................................................................... 57
Figure 4.10: MAC control frame format ............................................................................. 58
Figure 4.11: Format of frame preamble ............................................................................ 59
Figure 4.12: Shift register generating CRC-8 .................................................................... 60
Figure 4.13: Functional block diagram .............................................................................. 65
Figure 4.14: The 8B/10B Encoder and decoder in a system stransmission ..................... 66
Figure 4.15: The 8B/10B coding scheme .......................................................................... 67
Figure 4.16: State machine of running disparity............................................................... 71

4


Figure 4.17: First-in, first-out functionality gives a FIFO register file a specific directionality
................................................................................................................................... 72
Figure 4.18: A typical block diagram of a synchronous FIFO .......................................... 74
Figure 4.19: The illustrative examples of FIFO occupancy. ............................................. 75
Figure 4.20: A typical block diagram of a asynchronous FIFO ......................................... 76
Figure 4.21: FIFO state machine transition diagram. ........................................................ 77
Figure 4.22: FPGA daughter board .................................................................................. 78
Figure 4.23: AT FPGA mother board and daughter board ................................................ 79
Figure 4.24: The Gigabit Ethernet fibre optical connection ............................................... 79
Figure 5.1: Encoder Block Diagram .................................................................................. 81
Figure 5.2: Decoder Block Diagram .................................................................................. 81
Figure 5.3: Schemetic Symbol of an 8B10B Encoder ....................................................... 82
Figure 5.4: Schemetic Symbol of an 8B10B Decoder ....................................................... 83
Figure 5.5: Encoder 8B10B Timing Diagrams................................................................... 85
Figure 5.6: Decoder 8B10B Timing Diagrams .................................................................. 85
Figure 5.7: Schemetic Symbol of an Asynchronous FIFO ................................................ 87
Figure 5.8: Initial write operations to an FIFO. .................................................................. 91
Figure 5.9: Read and Write Operations to an Almost Full FIFO ....................................... 92

Figure 5.10: Read and Write Operations to an almost empty FIFO .................................. 93
Figure 5.11: Full compilation was successful report ......................................................... 93
Figure 5.12: Linux System login ........................................................................................ 94
Figure 5.13: Load FPGA and show status ........................................................................ 94
Figure 5.14: Data receive after sending messages........................................................... 95
Figure 5.15: Show data in buffer ....................................................................................... 95
Figure 5.16: Clear data in buffer ....................................................................................... 96
Figure 5.17: The connection was tested. .......................................................................... 96
Figure 5.18: The disconnection was tested....................................................................... 96
Figure 5.19: System connection test with telnet................................................................ 97
Figure 5.20: Wireshark Preferences ................................................................................. 98
Figure 5.21: Wireshark Options ........................................................................................ 98
Figure 5.22: Command window ........................................................................................ 99
Figure 5.23: The sent packet and the received packet ..................................................... 99

5


List of Tables
Table 2.1: Stratix II FPGA EP2S180 features ................................................................... 18
Table 3.1: Ethernet Communication Standards ................................................................ 37
Table 3.2: Common Fiber Optic Attachment options for standard 802.3z ........................ 38
Table 3.3: Diagram of Host Board Connector Block Pin Numbers and Names ................ 43
Table 4.1: 3-bit to 4-bit Encoding Values .......................................................................... 69
Table 4.2: 5-bit to 6-bit Encoding Values .......................................................................... 69
Table 4.3: 8B/10B encoding/decoding mapping table....................................................... 70

6

Abbreviation
AES

Advanced Encryption Standard

APON

ATM Passive Optical Network

ALM

Adaptive Logic Module

ALU

Arithmetic Logic Unit

APD

Avalanche Photodiode

ASIC

Application Specific Integrated Circuit

BPON

Broadband Passive Optical Network

CAD

Computer-Aided Design

CDR

Clock Data Recovery

CMOS

Complementary Metal-Oxide-Semiconductor

CPLD

Complex Programmable Logic Device

DSL

Digital Subcriber Line

DTE

Data Terminal Equipment

EDA

Electronic Design Automation

EPON

Ethernet based Passive Optical Network

FIFO

First-In First-Out

FIR

Finite Impulse Response

FPGA

Field Programmable Gate Array

FTTH

Fiber To The Home

GMII

Gigabit Media Independent Interface

G-PON

Gigabits Passive Optical Network

HDL

Hardware Description Language

I/O

Input/Output

IC

Integrated Circuit

IEC

Very-Large-Scale Integration

IEEE

Institute Of Electrical And Electronics Engineers

ISI

Intersymbol Interference

ITU-T

International Telecommunication Union - Telecommunication

LAN

Local Area Network

7

LD

Laser Diode

LED

Light Emitting Diode

LLC

Logical Link Control

MAC

Media Access Control

MBd

Megabaud

MDI

Medium Dependent Interface

MMF

Multi-Mode Fibers

OSI

Open Systems Interconnection

PAL

Programmable Array Logic

PCS

Physical Coding Sublayer

PHY

Gigabit Physical Layer

PIN

Positive-Intrinsic-Negative

PLLs

Phase-Locked Loops

PMA

Physical Medium Attachment

PMD

Physical Medium Dependent

PON

Passive Optical Network

QDR

Quad Data Rate

RAM

Random Access Memory

RS

Reconciliation Sublayer

RTL

Register Transfer Level

SDRAM

Synchronous Dynamic Random Access Memory

SERDES

Serialize/Deserialize (Serdes)

SFP

Small Form Factor Pluggable

SMF

Multi-Mode Fibers

STM

Synchronous Transport Module

VLSI

Very-Large-Scale Integration

VOD

Video On Demand

8


CHAPTER 1: INTRODUCTION

T

his chapter introduces the motivation and objectives of this thesis about
the optical transport implementation based on Field Programmable Gate

Array. Description on the available hardware for implementation is presented. The
problem statement of the project will also be carried out in this thesis. The outline

of the thesis is provided.

1.1 Introduction
Recently, there has been a great demand of the high-speed data transmission
due to the emerging applications in digital communications such as high quality
audio, video transmission [5], [12]. The development of technology which can
support the high data rate transmission of various applications is of considerable
interest. Among the advanced transmission technologies, the optical fiber systems
are the suitable choice due to their potential advantages. The optical transport
networks enable to transmit more information than conventional cable networks. In
addition, the advances of signal processing techniques allow to implement the
hardware for the high-speed data transmission efficiently.
There are several methods to implement the system. One of the methods to
implement the system is using FPGAs (Field Programmable Gate Arrays). FPGAs
are the fastest, smallest, and shortest way to implement into hardware. This method
is flexibility of design process and the shorter time to market for the chip design [4],
[18].
The disadvantages of using this hardware are it needs memory and other
peripheral chips to support the operation. Besides that, it uses the most power usage
and memory space, and would be the slowest in terms of time to produce the output
compared to other hardwares.

9


FPGA is an example of VLSI circuit which consists of a “sea of NAND gates”
whereby the function are customer provided in a “wire list”. This hardware is
programmable and the designer has full control over the actual design
implementation without the need and delay for any physical IC fabrication facility.
An FPGA combines the speed, power, and density attributes of an ASIC with the

programmability of a general purpose processor will give advantages to the optical
transport system.
An FPGA could be reprogrammed for new functions by a base station to meet
future needs particularly when new design is going to fabricate into chip. This will
be the best choice for optical transport implementation since it gives flexibility to
the program design besides the low cost hardware component compared to others.
As the performance of optical networks increases, optical network interface
will have a significant impact on a system performance. Interfaces are optimized for
sending and receiving large packets. Recent studies have shown that the controller
in the optical network interface must be able to buffer larger number of incoming
smaller packets. If the controller does not provide adequate resources, the result will
be lost packets and reduced performance. The other reason for this problem is that
current devices do not provide enough processing power to implement basic packet
processing tasks efficiently as the frame rate increases for small packet traffic. New
network services like FTTH (Fiber to the home) may be significantly more complex
than existing services [12]. To address these issues, an intelligent, configurable
network interface is an effective solution. A reconfigurable optical network gigabit
Ethernet interface allows rapid prototyping of new system architectures for network
interfaces. An FPGA with an embedded processor is a natural fit with this
requirement.

10


1.2 Project objectives
The objective of this thesis is the design and implementation of the hardware
platform for the FPGA-based optical network transport with the Gigabit Ethernet
interface. This system is designed as an open research platform, with a range of
configuration options and possibilities for extension in both software and hardware
dimensions.

The aim for this project is to design an optical transport network, mapping
8bits–10 bits encoder/decoder to serial to parallel and parallel to serial converter
and FIFO buffers to MAC core, using Verilog HDL. These designs were developed
using Verilog HDL programming language in the design entry software. The design
is then implemented in the Stratix II EP2S180F1020C5 FPGA chip, and AT FPGA
version 1.0 development board.
Several tools involved in the process of completing the design in real
hardware which can be divided into two categories, software tools and hardware
tools. The softwares which include in this project are using CAD tools software,
Verilog HDL module generator Altera Quartus II 8.0 and Modelsim, while the
hardware use is Altera Stratix II board of ATVN FPGA version 1.0.
1.3 Project scope
The work of the project will be focused on the design of the processing block.
One example is 8 bits-10 bits encoder decoder and FIFO buffers. This project will
concentrate on using the Gigabit Ethernet MAC Controller that supports data
transfer speeds 1Gbps in the fiber optical transport networks and implement it on
FPGA. The Gigabit Ethernet MAC controller is an open core which was designed
by using Verilog HDL code.
To ensure that the program can be implemented, the number of gates used in
the design must be small or at least less than the hardware can support. All design

11


need to be verified to ensure that no error in Verilog HDL programming before
being downloading to hardware.
The second scope is to implement the design into FPGA hardware
development board. This process is implemented if all designs are correctly verified
and simulated using particular software. Implementation includes hardware
programming on FPGA or downloading hardware design into FPGA and software

programming.
Besides that, the design does not include Power-PC processor and control
signal which control the data processing in SERDES module. The control signal is
use to select the process executed for each computation process during Verilog
HDL design. As a result, the design is applicable for hardware implementation in
the FPGA development board.
Finally, System testing performed also include in the scope of the project.
Testing is intended as the input interface for user as well as to control data
processing performed by the hardware. Appropriate software is used to compare the
computation performed by the FPGA hardware with the software. These
computation values should be verified and tested to ensure the correctness of the
developed module Testing required in understanding the operation of the
networking process.
1.4 Thesis outline
The thesis is organized into six chapters, namely introduction, FPGA and
HDL chip design, principles and applications of optical communications, design
and implementation, results and analysis, conclusion and future works.
 Chapter 1 discusses the general idea of the project which covers the
introduction, project objective, and scope of the project.

12


 Chapter 2 presents the background information for this research and related
literature review shows. The overview of the FPGA architecture, and FPGA
devices, basic concepts about design and hardware description language.
 Chapter

3

describes

the

principles

and

applications

of

optical

communications, optical fiber communication technology, system overview,
trends and advances, fiber-optic transmission-systems design, device
requirements and standard.
 Chapter 4 explains regarding the hardware design and software design
process involved in the project. This part basically discussed on the works
involved to download the modules into FPGA board.
 Chapter 5 Analysis for individual components is provided and shows the
results obtained from the FPGA hardware. The results obtained are captured
and shown in the figures. Testing for system level will be carried out in this
chapter
 Chapter 6 Conclusions are drawn and future work is suggested in.

13


CHAPTER 2: FPGA AND HDL CHIP DESIGN

T

he development of types of sophisticated field-programmable devices
has made the designing digital hardware industry change dramatically

over the past few years. This chapter introduces the overview of fieldprogrammable devices. I will present the relevant terminology and introduce the
architectures of the most important commercially available chips. Then, I will
provide a brief introduction about the hardware description languages.
2.1 Introduction
Field Programmable Gate Arrays (FPGAs) have played an important role in
the development of the electronics industry. FPGAs can be applied in different
aspects of computing problems thanks to rapidly improving semiconductor
manufacturing technology which is ranged from sub-micron to deep sub-micron
processes and equally innovative CAD tools. Thus, FPGAs provide the facility to
implement systems with a set of primitive computational elements interconnected
through flexible interconnects. As compared to build a device with exact
computational units and hardwired dataflow to solve a single problem, to build a
FPGA solution offers more advantages of supporting a wide range of tasks [18].
Field Programmable Gate Arrays are called this because rather than having a
structure similar to a PAL (Programmable Array Logic) or other programmable
device, they are structured very much like a gate array ASIC (Application Specific
Integrated Circuit). This makes FPGAs very nice for use in prototyping ASICs, or
in places where and ASIC will eventually be used. For example, an FPGA may be
used in a design that needs to get to market quickly regardless of cost. Later an
ASIC can be used in place of the FPGA when the production volume increases, in
order to reduce cost [4], [17].

14

2.2 FPGA architecture overview
Each FPGA vendor has its own FPGA architecture, but in general terms they
are all a variation of that shown in Figure 2.1. The architecture consists of
configurable logic blocks, configurable I/O blocks, and programmable interconnect.
Also, there will be clock circuitry for driving the clock signals to each logic block,
and additional logic resources such as ALUs, memory, and decoders may be
available. The two basic types of programmable elements for an FPGA are Static
RAM and anti-fuses.
The FPGA architecture is composed of basic functional blocks, which are
connected together by a structure of programmable interconnections and have I/O
capabilities to distribute signal [4], [17].

Figure 2.1: Structure of an FPGA.

15


There are two basic categories of FPGAs on the market today: SRAM-based
FPGAs and anti-fuse based FPGAs. In the first category, Xilinx and Altera are the
leading manufacturers in terms of number of users, with the major competitor being
AT&T. For antifuse-based products, Actel, Quicklogic and Cypress, and Xilinx
offer competing products.
An example of usage of SRAM-controlled switches is illustrated in Figure 2.2,
showing two applications of SRAM cells: to control the gate nodes of passtransistor switches and to control the select lines of multiplexers that drive logic
block inputs. The figure gives an example of the connection of one logic block
(represented by the AND-gate in the upper left corner) to another through two passtransistor switches, and then a multiplexer, all controlled by SRAM cells. Whether
an FPGA uses pass-transistors or multiplexers or both depends on the particular
product.

Figure 2.2: SRAM-controlled Programmable Switches.

16


The other type of programmable switch used in FPGAs is the antifuse.
Antifuses are originally open-circuits and take on low resistance only when
programmed. Antifuses are suitable for FPGAs because they can be built using
modified CMOS technology. As an example, Actel’s antifuse structure, known as
PLICE is depicted in Figure 2.3. The figure shows that an antifuse is positioned
between two interconnect wires and physically consists of three sandwiched layers:
the top and bottom layers are conductors, and the middle layer is an insulator. When
unprogrammed, the insulator isolates the top and bottom layers, but when
programmed the insulator changes to become a low-resistance link. PLICE uses
Poly-Si and n+ diffusion as conductors

Figure 2.3 : Actel Antifuse Structure.
2.3 Stratix II FPGA
The Stratix® II FPGA family is based on a 1.2-V, 90-nm, all-layer copper
SRAM process and features a new logic structure that maximizes performance, and
enables device densities approaching 180,000 equivalent logic elements (LEs).
Stratix II devices offer up to 9 Mbits of on-chip, TriMatrix™ memory for
demanding, memory intensive applications and have up to 96 DSP blocks with up
to 384 (18-bit × 18-bit) multipliers for efficient implementation of high
performance filters and other DSP functions. Various high-speed external memory
interfaces are supported, including double data rate (DDR) SDRAM and DDR2
SDRAM, RLDRAM II, quad data rate (QDR) II SRAM, and single data rate (SDR)
SDRAM. Stratix II devices support various I/O standards along with support for 1gigabit per second (Gbps) source synchronous signaling. Stratix II devices offer a
17

complete clock management solution with internal clock frequency of up to 550
MHz and up to 12 phase-locked loops (PLLs). Stratix II devices which have a top
view in Figure 2.4 are also the industry’s first FPGAs with the ability to decrypt a
configuration bitstream using the Advanced Encryption Standard (AES) algorithm
to protect designs.

Figure 2.4: Top view Stratix II.
Table 2.1: Stratix II FPGA EP2S180 features

Feature

EP2S180

ALMS

71,760

Adaptive look-up tables (ALUTs)

143,520

Equivalent Les

179,400

M512 RAM blocks

930

M4K RAM blcoks

768

M-RAM blocks

9

Total RAM bits

9,383,040

DSP blocks

96

18-bit x 18-bit multipliers

384

Enhanced PLLs

4

Fast PLLs

8
742

Maximum user I/O pins

Package type

1020-pin Fineline BGA

Voltage

1.2-V internal, 3.3-V I/O

18


Figure 2.5: Stratix II Block Diagram.

The Stratix II EP2S180 features are listed in Table 2.1. More specially, the Stratix II
family offers the following features:
-

15,600 to 179,400 equivalent LEs

-

New and innovative adaptive logic module (ALM), the basic building block
of the Stratix II architecture, maximizes performance and resource usage
efficiency

-

Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing
logic resources

-

TriMatrix memory consisting of three RAM block sizes to implement true
dual-port memory and first-in first-out (FIFO) buffers

19


-

High-speed DSP blocks provide dedicated implementation of multipliers (at
up to 450 MHz), multiply-accumulate functions, and finite impulse response
(FIR) filters

-

Up to 16 global clocks with 24 clocking resources per device region

-

Clock control blocks support dynamic clock network enable/disable, which
allows clock networks to power down to reduce power consumption in user
mode

-

Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide
spread spectrum, programmable bandwidth, clock switchover, real-time PLL
reconfiguration, and advanced multiplication and phase shifting

Figure 2.6: 1,020-PIN FPGA Package Outline

20


2.4 Hardware description language
2.4.1 Introduction
In electronics, a hardware description language (HDL) is referred to as a
class of computer languages which can be used to describe of electronic circuits. It
can support to describe circuit's operation, its design, and tests to verify its
operation by simulations. To design integrated circuits, one can use the Verilog
HDL or VHDL which is one of the two most common Hardware Description
Languages (HDL). In the design cycle, with the help of HDL the design can be
simulated to investigate and correct errors or to check the experimental
architectures. The most advantages of using HDL are that designs are usually more
readable and they are technology-independent, easy to check performance results
[11].
Verilog can be used to describe designs at four levels of abstraction:
-

Algorithmic level (much like C code with if, case and loop statements).

-

Register transfer level (RTL uses registers connected by Boolean equations).

-

Gate level (interconnected AND, NOR etc.).

-

Switch level (the switches are MOS transistors inside gates).

Figure 2.7: Verilog

21


2.4.2 Verilog HDL Structure
In Verilog, circuit components are designed inside a module [11]. Modules
can contain both structural and behavioral statements. Structural statements
represent circuit components like logic gates, counters, and microprocessors.
Behavioral level statements are programming statements that have no direct
mapping to circuit components like loops, if-then statements, and stimulus vectors
which are used to exercise a circuit. A design is described in Verilog using the
concept of a module. A module starts with the keyword module followed by an
optional module name and an optional port list. The key word endmodule ends a
module. A module can be conceptualised as consisting of two parts, the port
declarations and the module body. The port declarations represent the external
interface to the module. The module body represents the internal description of the
module - its behaviour, its structure, or a mixture of both
Example
`timescale 1ns / 1ps
module some_logic_component (c, a, b);
// declare port signals
output c;
input a, b;
// declare internal wire
wire d;

//instantiate structural logic gates
and a1(d, a, b); //d is output, a and b are inputs
not n1(c, d);

//c is output, d is input

endmodule
The language also defines constructs that can be used to control the input and output
of simulation. More recently Verilog is used as an input for synthesis programs
which will generate a gate-level description (a netlist) for the circuit. Some Verilog
constructs are not synthesizable.

22


Comments can be specified in two ways:
(//). All text between these characters and the end of the line will be ignored
by the Verilog compiler.
/* and */. Using comments on more than one line.

Data Types
Value Set Verilog consists of only four basic values.
0 (logic zero, or false condition)
1 (logic one, or true condition)
x (unknown logic value)
z (high impedance state)

x and z have limited use for synthesis.

Wire A wire represents a physical wire in a circuit and is used to connect gates or

modules. The value of a wire can be read, but not assigned to, in a function or
block. A wire does not store its value but must be driven by a continuous
assignment statement or by connecting it to the output of a gate or module.
Example
wire c // simple wire
wand d;
assign d = a; // value of d is the logical AND of
assign d = b; // a and b
wire [9:0] A; // a cable (vector) of 10 wires.
Reg A reg (register) is a data object that holds its value from one procedural
assignment to the next. It is used only in functions and procedural blocks.
Syntax

reg [msb:lsb] reg_variable_list;

Example
reg a; // single 1-bit register variable
reg [7:0] tom; // an 8-bit vector; a bank of 8 registers.
Input, Output, Inout: These keywords declare input, output and bidirectional ports
of a module or task. Input and inout ports are of type wire. An output port can be
configured to be of type wire, reg, wand, wor or tri. The default is wire.
23


Syntax
input [msb:lsb] input_port_list;
output [msb:lsb] output_port_list;
inout [msb:lsb] inout_port_list;
Example
module sample(b, e, c, a);

input a; // An input which defaults to wire.
output b, e; // Two outputs which default to wire
output [1:0] c; /* A two-it output. One must declare its type in
a separate statement. */
reg [1:0] c; // The above c port is declared as reg.
Parameter: A parameter defines a constant that can be set when you instantiate a
module. This allows customization of a module during instantiation.
Syntax:

parameter par = value;

Example
parameter n = 4;
Operators
Arithmetic Operators
+ (addition)
- (subtraction)
* (multiplication)
/ (division)
% (modulus)
Relational Operators
< (less than)
<= (less than or equal to)
> (greater than)
>= (greater than or equal to)
== (equal to)
!= (not equal to)

24