Vi điều khiển và ứng dụng Hardware

Hardware
DsPIC
TS Nguyễn Hồng Quang


Objectives

2


Categories

3


DsPIC 16 bit microcontroller

4


Sizes

5


System Management Features
Fuse enabled Watchdog Timer with its own RC
oscillator
Programmable Time out: 2 ms - 16 sec

Power On Reset with a programmable delay 0, 4,

16, 64ms
Brown-out Reset with programmable levels
Low Vdd Detect Interrupt with programmable


Memory
 Flash: 64, 128 and 256K O
 Larger RAM: 8K, 16K and 30KB
 DMA (Direct Memory Access) Controller
 Upward compatible with dsPIC30F
 Upward compatible with PIC24

emory Access) Controller

7


Target Operating Parameters
· Target Op Speed:

40 MIPS *

· Target Vdd:

3.0 to 3.6V

· Target Temp:

-40º C to 85º C

* Op Speed over entire Vdd and Temp Range

8


Interrupt vector
 Total of 118 available interrupts.
 Like dsPIC30, all interrupts may be

individually enabled and assigned to
one of seven priority levels.
 Interrupts can be directed to vector
through an Alternate interrupt
vector table.
 Program address hex 200 on
dspic33 devices rather than hex 100
as on dsPIC30 devices.

9


Math error

10


Math error
 The OVA and OVB bits indicate an overflow

condition in either accumulator a or b, The

OVA bit will only be cleared when the user
clears the MATHERR trap status flag.
 The COVA and COVB bits indicate an
catastrophic overflow condition
 The SFTERR bit indicates an error while
executing a shift instruction.
 The DIVERR indicates an attempt to divide by
0.

11


dsPIC33F DMA Controller

 dsPIC33 includes Direct Memory Access (DMA) controller

for efficient data movement. The devices include eight
DMA channels.
12


Notes on DMA
 A DMA channel can move words or

13

bytes. I can mode blocks of up to 1024
data elements. When the channel
completes moving a block, it can
generate an interrupt to signal the

software that the block is ready for
processing.
 dual port DMA SRAM. This allows both
the DMA and CPU to access a portion of
the total data RAM, simultaneously.
dsPIC33 devices typically contain a 2K
byte dual port RAM buffer area.


DMA-Ready Peripherals

14


dsPIC33F Flash Memory

15


dSPIC33 in circuit serial
programming
 the dSPIC33 support in circuit serial

programming, called ICSP.
 The interface to the device is done with
2 pins for clock and data and a reset pin.
 It also enables field upgrades to the
system using a small connector.
Programming times in ICSP is similar to
those for factory programming

16


Run Time Self Programming OR
Self Programming
 Device can program its own FLASH memory
 Ideal for “calibration” or “parameterization” in

final test O
 Ideal for “Remote code update”

17


Data EEPROM
 The dsPIC30 has on board high

endurance data EEPROM memory.
 The dsPIC33 devices do not. However,
the flash memory is useable as EEPROM
memory. Programming the flash does
not require any external high voltage or
control. The flash can withstand 1000
write / erase cycles.
 For very high endurance requirements,
external serial EEPROM offers a simple, cost
effective solution
18

dsPIC30 I/O Levels

19


dsPIC 33F I/O level

20


UART feature

21


I2C feature
To allow the I2C module to respond to a range of slave
addresses, the module has a new I2C address
detection mask
A “1” in the mask register ignores the corresponding
address bit
 Example: I2CADD=0b0011010011
I2CAMSK=0b0000110000
ϖ Module will respond to addresses

22


System Integration Features

 On-chip PLL
 On-chip precision RC oscillator
 7.328 MHz +/- 2%

 Low Power modes:
 IDLE
 SLEEP

 Watchdog Timer

23


Clock
 On-chip PLL
 On-chip precision RC oscillator
 7.328 MHz +/- 2%

 Low Power modes:
 IDLE
 DOZE
 SLEEP

 Watchdog Timer

24


Clock sources
Low Pwr RC 512KHz

Fast RC 8.0 MHz
EC Clock

OSCI

XTL,XT,HS
Primary
Xtal OSC

PLL
4x,
8x,
16x
or bypass

Clock Divide
By
1, 4, 16, 64

System
Clock

OSCO
SOSCI
SOSCO

32KHz
Timer1 Xtal
OSC

Primary Oscillator for Crystals
32 kHz for Real Time Clock

 Includes 2 Internal RC

Oscillators
Clock divide can optionally slow
clock to conserve power