Vi điều khiển và ứng dụng Interrupt

Chuyên đề II
Vi điều khiển và ứng dụng
Interrupt and A/D


Bảng Vector ngắt

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Chi tiết

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Bảng chi tiết

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INT and AINT
Interrupt Vector Table starting at location
0x000004. up to 54 sources of interrupt.
Interrupt Service Routine (ISR).
Alternate Vector Table
Access to the AIVT is provided by the ALTIVT
control bit (INTCON2<15>).
If the ALTIVT bit is set, all interrupt will use
the alternate vectors instead of the default
vectors.

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Ví dụ

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Ưu tiên ngắt
 7 user assigned priority levels
 Natural priority resolves conflicts
 User-assigned priority can override natural

priority
 CPU Status Register, known as SRL, has 3
status bits for priority

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Ngắt trong ngắt
 An ISR may be interrupted by a higher

priority interrupt
 Nesting can be disabled by setting NSTDIS
bit in INTCON1 register
 Temporarily raising CPU interrupt priority to
7 in ISR can also disable nesting

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Traps
 Oscillator Failure Trap (level 14 - hard trap)

Address Error Trap (level 13 - hard trap)
 Instruction fetch from illegal program space
Data fetch from unimplemented data space
Unaligned word access from data space
 Stack Error Trap (level 12 - soft trap)
Stack overflow or underflow



 Math Error Trap (level 11 - soft trap)
Divide by Zero
 Unsaturated Accumulator Overflow (A or B) l
Catastrophic Accumulator Overflow (either) l
Accumulator Shift Overflow


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Trap

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Interrupt Disable “DISI”

Instruction

 DISI disables level 1 - 6 interrupts for

“N+1”
instruction cycles
 Supports a maximum of 16384 cycles
 DISI #5 ; disable for 6 cycles

 DISI expires when DISICNT decrements to 0

DISICNT can be written to modify DISI time
 DISICNT can be cleared to cancel
instruction

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Interrupt Control and
Status Registers
 INTCON1, INTCON2 Registers
 IFSx: Interrupt Flag Status Registers
 IECx: Interrupt Enable Control

Registers
 IPCx: Interrupt Priority Control
Registers
 SR: CPU Status Register

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Ví dụ

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Interrupt Config

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Các bước khởi tạo ngắt
 Set the priority bits in the appropriate IPC

register
 Clear the interrupt flag in the appropriate IFS
register
 Set the interrupt enable bit in the appropriate
IEC register
 Configure the peripheral interrupt source
Enable the peripheral interrupt source  

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Ví dụ
 void __attribute__ (( interrupt)) _T1Interrupt ( void)

{

// interrupt service routine code here...
} // _InterruptVector
void _ISR _T1Interrupt (void)
{
// remember to clear the interrupt flag before exit
_T1IF = 0;
} // _InterruptVector

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Chi tiết INTCON1, INTCON2

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Interrupt flag status register IFS0

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IFS1

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Interrupt enable control register
0 - IEC0

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Interrupt priorities

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