Digital Synthesizers And Transmitters For Software Radio _ www.bit.ly/taiho123

DIGITAL SYNTHESIZERS AND TRANSMITTERS
FOR SOFTWARE RADIO


Digital Synthesizers and Transmitters
for Software Radio
by

JOUKO VANKKA
Helsinki University of Technology,
Finland


A C.I.P. Catalogue record for this book is available from the Library of Congress.

ISBN-10 1-4020-3194-7 (HB) Springer Dordrecht, Berlin, Heidelberg, New York
ISBN-10 1-4020-3195-5 (e-book) Springer Dordrecht, Berlin, Heidelberg, New York
ISBN-13 978-1-4020-3194-6 (HB) Springer Dordrecht, Berlin, Heidelberg, New York
ISBN-13 978-1-4020-3195-3 (e-book) Springer Dordrecht, Berlin, Heidelberg, New York

Published by Springer,
P.O. Box 17, 3300 AA Dordrecht, The Netherlands.

Printed on acid-free paper

All Rights Reserved
© 2005 Springer
No part of this work may be reproduced, stored in a retrieval system, or transmitted
in any form or by any means, electronic, mechanical, photocopying, microfilming, recording
or otherwise, without written permission from the Publisher, with the exception

of any material supplied specifically for the purpose of being entered
and executed on a computer system, for exclusive use by the purchaser of the work.
Printed in the Netherlands.


Contents

PREFACE...................................................................................XVII
LIST OF ABBREVIATIONS ...................................................XXIII
1.

TRANSMITTERS ................................................................1

1.1

Direct Conversion Transmitters ............................................................1

1.2

Dual-Conversion Transmitter ................................................................3

1.3

Transmitters Based on VCO Modulation .............................................3

1.4

Offset-PLL Architecture.........................................................................6

1.5

Envelope Elimination and Restoration (EER)......................................6

1.6

Polar-Loop Transmitter .........................................................................9

1.7

Linear Amplification with Nonlinear Components (LINC) ..............10

1.8

Combined Analogue Locked Loop Universal Modulator (CALLUM)
14

1.9

Linear Amplification Employing Sampling Techniques (LIST) .......15


Contents

vi
1.10

Transmitters Based on Bandpass Delta Sigma Modulator ...........17

REFERENCES.............................................................................19
2.

POWER AMPLIFIER LINEARIZATION .....................25

2.1

Feedforward...........................................................................................25

2.2

Cartesian Modulation Feedback..........................................................29

2.3
Predistortion ..........................................................................................31
2.3.1 Analog Predistortion..............................................................................33
2.3.2 Mapping Predistortion ...........................................................................35
2.3.3 Complex Gain Predistortion ..................................................................36
2.3.4 Polar Predistortion.................................................................................38
2.3.5 RF-Predistortion Based on Vector Modulation .....................................39
2.3.6 Data Predistorters ..................................................................................41

REFERENCES.............................................................................41
3.
DIGITAL COMPENSATION METHODS FOR
ANALOG I/Q MODULATOR ERRORS.......................................49
3.1
Quadrature Modulator Errors Compensation ...................................52
3.1.1 Symmetric Compensation
m
Method ........................................................53
3.1.2 Partial Correction of Mixer Nonlinearity in Quadrature Modulators ....55

3.1.3 Asymmetric Compensation Method......................................................56
3.1.4 Digital Precompensation Method without Training Signal ...................57

REFERENCES.............................................................................58
4.

DIRECT DIGITAL SYNTHESIZERS ............................61

4.1

Conventional Direct Digital Synthesizer .............................................61

4.2

Pulse Output DDS .................................................................................63

4.3

DDS Architecture for Modulation Capability ....................................65

4.4

QAM Modulator....................................................................................65


Contents

vii

REFERENCES.............................................................................69

5.

RECURSIVE OSCILLATORS.........................................73

5.1

Direct-Form Oscillator .........................................................................73

5.2

Coupled-Form Complex Oscillator .....................................................76

REFERENCES.............................................................................79
6.

CORDIC ALGORITHM ...................................................81

6.1

Scaling of In and Qn ...............................................................................84

6.2
Quantization Errors in CORDIC Algorithm......................................85
6.2.1 Approximation Error .............................................................................85
6.2.2 Rounding Error of Inverse Tangents .....................................................86
6.2.3 Rounding Error of In and Qn ..................................................................87
6.3

Redundant Implementations of CORDIC Rotator ............................87

6.4
Hybrid CORDIC ...................................................................................88
6.4.1 Mixed-Hybrid CORDIC Algorithm ......................................................89
6.4.2 Partitioned-Hybrid CORDIC Algorithm ...............................................90

REFERENCES.............................................................................92
7.

SOURCES OF NOISE AND SPURS IN DDS .................97

7.1

Phase Truncation Related Spurious Effects........................................97

7.2

Finite Precision of Sine Samples Stored in LUT...............................103

7.3

Distribution of Spurs...........................................................................105

7.4

Phase Noise of DDS Output................................................................108

7.5

Post-Filter Errors ................................................................................110

REFERENCES...........................................................................110


Contents

viii

8.
SPUR REDUCTION TECHNIQUES IN SINE OUTPUT
DIRECT DIGITAL SYNTHESIZER ...........................................113
8.1

Nicholas Modified Accumulator ........................................................114

8.2
Non-Subtractive Dither.......................................................................116
8.2.1 Non-Subtractive Phase Dither .............................................................116
8.2.2 First-Order Analysis ............................................................................117
8.2.3 Non-Subtractive Amplitude Dither .....................................................121
8.3
Subtractive Dither ...............................................................................122
8.3.1 High-Pass Filtered Phase Dither..........................................................123
8.3.2 High-Pass Filtered Amplitude Dither ..................................................123
8.4
Tunable Error Feedback in DDS .......................................................124
8.4.1 Phase EF..............................................................................................125
8.4.1.1 Phase EF for Cosine DDS ........................................................126
8.4.1.2 Phase EF for Quadrature DDS .................................................128
8.4.2 Amplitude EF ......................................................................................129
8.4.2.1 Amplitude EF for Cosine DDS ................................................131

8.4.2.2 Amplitude EF for Quadrature DDS .........................................132
8.5

Implementations..................................................................................134

8.6

Measurement Results..........................................................................134

8.7

Conclusions ..........................................................................................135

REFERENCES...........................................................................135
9.

BLOCKS OF DIRECT DIGITAL SYNTHESIZERS ..139

9.1

Phase Accumulator .............................................................................139

9.2
Phase to Amplitude Converter...........................................................143
9.2.1 Non-Linear D/A Converter..................................................................145
9.2.2 Exploitation of Sine Function Symmetry ............................................145
9.2.3 Compression of Quarter-Wave Sine Function.....................................147
9.2.3.1 Difference Algorithm ...............................................................147
9.2.3.2 Splitting into Coarse and Fine LUTs........................................149
9.2.3.3 Angle Decomposition...............................................................150

9.2.3.4 Modified Sunderland Architecture...........................................152


Contents

ix

9.2.3.5 Nicholas Architecture...............................................................153
9.2.3.6 Polynomial Approximations ....................................................155
9.2.3.6.1 Piecewise Linear Interpolation..........................................156
9.2.3.6.2 High Order Piecewise Interpolation..................................158
9.2.3.6.3 Taylor Series Approximation............................................160
9.2.3.6.4 Chebyshev Approximation ...............................................161
9.2.3.6.5 Legendre Approximation ..................................................163
9.2.3.7 Using CORDIC Algorithm as a Sine Wave Generator ............164
9.2.4 Simulation ...........................................................................................167
9.2.5 Summary of Memory Compression and Algorithmic Techniques ......167
9.3

Filter .....................................................................................................168

REFERENCES...........................................................................169
10.

CURRENT STEERING D/A CONVERTERS..............177

10.1

D/A Converter Specifications.........................................................177

10.2
Static Non-Linearities.....................................................................178
10.2.1 Random Errors
r
..................................................................................179
10.2.2 Systematic Errors ..............................................................................181
10.2.3 Calibration .........................................................................................183
10.3

Finite Output Impedance ...............................................................183

10.4

Other Systematic Errors ................................................................185

10.5
Dynamic Errors...............................................................................186
10.5.1 Ideal D/A Converter ..........................................................................187
10.5.2 Dynamic Performance Metrics..........................................................188
10.5.3 Dynamic Limitations .........................................................................189
10.6
Inaccurate Timing of Control Signals...........................................191
10.6.1 D/A Converter Finite Slew Rate........................................................193
10.7
Different Current Steering D/A Converters Architectures.........194
10.7.1 Binary Architecture ...........................................................................194
10.7.2 Unary Architecture ............................................................................195
10.7.3 Segmented Architecture ....................................................................196
10.8

Methods for Reduction of Dynamic Errors ..................................196


x

Contents
10.8.1 Glitches Reduction ............................................................................196
10.8.2 Voltage Difference between Control Signals ....................................198
10.8.3 Current Switch Sizing........................................................................202
10.8.4 Dummy Switches ..............................................................................203
10.8.5 Removing Spurs from Nyquist Band.................................................203
10.8.6 Sample and Hold ...............................................................................204
10.9
Timing Errors .................................................................................205
10.9.1 Control Signals Synchronization .......................................................205
10.9.2 Switch Driver Load Matching ...........................................................207
10.9.3 Layout................................................................................................209
10.10

Cascode Transistor .........................................................................209

REFERENCES...........................................................................213
11.

PULSE SHAPING AND INTERPOLATION FILTERS
219

11.1

Pulse Shaping Filter Design Algorithms .......................................219

11.2

Direct Form Structure of FIR Filter .............................................223

11.3

Transposed Direct Form Structure of FIR Filter ........................224

11.4

Hybrid Form ...................................................................................225

11.5

Word Length Effects and Scaling..................................................226

11.6

Canonic Signed Digit Format ........................................................227

11.7

Carry Save Arithmetic ...................................................................228

11.8

Polyphase FIR filters in Sampling Rate Converters ....................230

11.9

Half-Band Filters for Interpolation...............................................231

11.10

Cascaded Integrator Comb (CIC) Filter.......................................231

11.11

Pipelining/Interleaving ...................................................................234

REFERENCES...........................................................................234


Contents

xi

12.

RE-SAMPLING................................................................239

12.1

Interpolation for Timing Adjustment ...........................................240

12.2
Interpolation Filter with Polynomial-Based Impulse Response..241
12.2.1 Lagrange Interpolation ......................................................................242
12.3

Farrow Structure ............................................................................243

12.4

Alternative Polynomial Interpolators ...........................................246

12.5
Calculation of Fractional Interval µk Using NCO ........................250
12.5.1 Synchronization of Resampling NCO ...............................................252
12.5.2 Simulations........................................................................................255

REFERENCES...........................................................................255
13. FIR FILTERS FOR COMPENSATING D/A
CONVERTER FREQUENCY RESPONSE DISTORTION ......259
13.1

Four Different D/A Converter Pulse Shapes ................................262

13.2

Different Implementation...............................................................264

13.3

Filter Design ....................................................................................266

13.4

Implementations..............................................................................266

13.5

Measurement Result .......................................................................267

13.6

Conclusion .......................................................................................267

REFERENCES...........................................................................267
14. A DIRECT DIGITAL SYNTHESIZER WITH
TUNABLE DELTA SIGMA MODULATOR ..............................269
14.1

Direct Digital Synthesizer with Tunable ∆¦ Modulator .............270

14.2

Quadrature Modulator...................................................................271

14.3

Phase to Amplitude Converters .....................................................272


xii

Contents
14.4

Tunable ∆¦ Modulators .................................................................274

14.5

1-bit D/A Converter ........................................................................275

14.6

Implementations..............................................................................276

14.7

Measurement Results .....................................................................276

14.8

Conclusions......................................................................................277

REFERENCES...........................................................................277
15. A DIGITAL QUADRATURE MODULATOR WITH
ON-CHIP D/A CONVERTER.......................................................279
15.1

Multiplier Free Quadrature Modulation ......................................280

15.2

Interpolation Filters........................................................................281

15.3

D/A Converter .................................................................................283

15.4

Implementation and Layout...........................................................285

15.5
On-chip Capacitor ..........................................................................286
15.5.1 Analytic First Order Model ...............................................................287
15.5.2 Negative Feedback ............................................................................287
15.5.3 Reducing di/dt Noise .........................................................................288
15.5.4 Decoupling Capacitance....................................................................289
15.5.5 Resonance and Damping ...................................................................289
15.5.6 Implemented On-chip Capacitor .......................................................292
15.6

Measurement Results .....................................................................293

15.7

Conclusion .......................................................................................294

REFERENCES...........................................................................295
16. A GSM/EDGE/WCDMA MODULATOR WITH ONCHIP D/A CONVERTER FOR BASE STATIONS ....................297
16.1
Supported Communication Standards..........................................297
16.1.1 GSM System......................................................................................298

Contents

xiii

16.1.2 EDGE System....................................................................................300
16.1.3 WCDMA System ..............................................................................304
16.2

GSM/EDGE/WCDMA Modulator ................................................305

16.3

Pulse Shaping and Half-band Filters ............................................306

16.4

Re-Sampler......................................................................................307

16.5

CORDIC Rotator............................................................................308

16.6
Ramp Generator and Output Power Level Controller................309
16.6.1 Ramp Generator ................................................................................310
16.6.2 Initial Values of Ramp
m Generator......................................................310
16.6.3 Parallel Structure
t ...............................................................................311
16.7

Multicarrier Modulator Architectures .........................................312

16.8
Design Flow .....................................................................................313
16.8.1 High Level Modeling ........................................................................314
16.8.2 Hardware Description........................................................................314
16.8.3 Logic Synthesis .................................................................................314
16.8.4 Layout Synthesis ...............................................................................315
16.8.5 Final Layout ......................................................................................315
16.9

D/A Converter .................................................................................319

16.10

Measurement Results .....................................................................320

16.11

Conclusions......................................................................................322

REFERENCES...........................................................................323
17. EFFECT OF CLIPPING IN WIDEBAND CDMA
SYSTEM AND SIMPLE ALGORITHM FOR PEAK
WINDOWING.................................................................................327
17.1

Introduction.....................................................................................327

17.2
Clipping Methods............................................................................328
17.2.1 Baseband Clipping ............................................................................328
17.2.2 Adaptive Baseband Clipping .............................................................328
17.2.3 IF Clipping ........................................................................................329


Contents

xiv

17.2.4 Windowing Algorithm.......................................................................329
17.3

Simulation Model............................................................................332

17.4
Results..............................................................................................333
17.4.1 Single Carrier ....................................................................................333
17.4.2 Multicarrier........................................................................................336
17.5

Conclusions......................................................................................337

REFERENCES...........................................................................337
18. REDUCING PEAK TO AVERAGE RATIO OF
MULTICARRIER GSM AND EDGE SIGNALS........................339
18.1

Introduction.....................................................................................339

18.2

Signal Model....................................................................................340

18.3

Clipping Methods............................................................................341

18.4
Results..............................................................................................342
18.4.1 GSM ..................................................................................................342
18.4.2 EDGE ................................................................................................344
18.4.3 GSM/EDGE ......................................................................................345
18.5

Conclusions......................................................................................345

REFERENCES...........................................................................346
ADDITIONAL REFERENCES TO CLIPPING ....................347
19. APPENDIX: DERIVATION OF THE LAGRANGE
INTERPOLATOR ..........................................................................353
INDEX.........................................................................................355


Acknowledgements

A significant part of this work was conducted during project-work funded by
the Technology Development Center (Tekes) and the Academy of Finland.
Personal grants were received from the Nokia Foundation, Jenny and Antti

Wihuri Foundation, and the Electronic Engineering Foundation. I would like
to acknowledge my sincere gratitude to Jaakko Ketola, Marko Kosunen,
Jonne Lindeberg, Johan Sommarek, Ilari Teikari and Olli Väänänen for generously providing assistance during the development of the material presented in this book.


Preface

The approach adopted in this book will, it is hoped, provide an understanding of key areas in the field of digital synthesizers and transmitters. It is easy
to include different digital techniques in the digital synthesizers and transmitters by using digital signal processing methods, because the signal is in
digital form. By programming the digital synthesizers and transmitters, adaptive channel bandwidths, modulation formats, frequency hopping and data
rates are easily achieved. Techniques such as digital predistortion for power
amplifier linearization, digital compensation methods for analog I/Q modulator nonlinearities and digital power control and ramping are presented in this
book. The flexibility of the digital synthesizers and transmitters makes them
ideal as signal generators for software radio. Software radios represent a major change in the design paradigm for radios in which a large portion of the
functionality is implemented through programmable signal processing devices, giving the radio the ability to change its operating parameters to accommodate new features and capabilities. A software radio approach reduces the content of radio frequency (RF) and other analog components of
traditional radios and emphasizes digital signal processing to enhance overall
transmitter flexibility. Software radios are emerging in commercial and military infrastructure. This growth is motivated by the numerous advantages of
software radios, such as the following:
1. Ease of design—Traditional radio design requires years of experience
and great care on the part of the designer to understand how the various system components work in conjunction with one another. The time required to
develop a marketable product is a key consideration in modern engineering
design, and software radio implementations reduce the design cycles for new
products, freeing the engineer from much of the iteration associated with


Preface

xviii

analog hardware design. It is possible to design many different radio products using a common RF front-end with the desired frequency and bandwidth in conjunction with a variety of signal processing software.

2. Ease of manufacture—No two analog components have precisely identical performance; this necessitates rigorous quality control and testing of
radios during the manufacturing process. However, given the same input,
two digital processors running the same software will produce identical outputs. The move to digital hardware thus reduces the costs associated with
manufacturing and testing the radios.
3. Multimode operation—the explosive growth of wireless has led to a
proliferation of transmission standards; in many cases, it is desirable that a
radio operates according to more than one standard.
4. Use of advanced signal processing techniques—the availability of high
speed signal processing on board allows the implementation of new
transmitter structures and signal processing techniques. Techniques such as
digital predistortion for power amplifier linearization, digital compensation
methods for analog I/Q modulator errors and digital power control and ramping, previously deemed too complex, are now finding their way into commercial systems as the performance of digital signal processors continues to
increase.
5. Flexibility to incorporate additional functionality—Software radios
may be modified in the field to correct unforeseen problems or upgrade the
radio.
Figure 1 shows a block diagram of the conventional digital modulator. It
consists of the following blocks: clipping circuit (Chapter 17 and Chapter
18), pulse shaping filters (Chapter 11), interpolation filters (Chapter 11), resamplers (Chapter 12), quadrature direct digital synthesizer (Chapters 4, 7, 8
and 9), inverse sinc filter (Chapter 13) and D/A converter (Chapter 10). The
QUADRATURE
DIRECT DIGITAL
SYNTHESIZER

Carrier Frequency
Phase
Accumulator

Cosine
ROM

I

Pulse Shaping Filter

Interpolation
Filters

Resampler

Clipping
Circuit
Q

Sine
ROM

1/sinc
Filter
Pulse Shaping Filter

Interpolation
Filters

Resampler

Figure 1. Digital modulator.

D/AConverter

Preface

xix

alternative method of translating the baseband-centered spectrum to a programmable carrier center frequency is to use the CORDIC rotator (Chapter
6) instead of the quadrature direct digital synthesizer, two mixers and an adder. Three design examples of the digital modulator are presented (Chapters
14, 15 and 16).
Chapter 1 provides a basic introduction to transmitter architectures. The
classic transmitter architecture is based upon linear power amplifiers and
power combiners. Most recently, transmitters have been based upon a variety of different architectures including Envelope Elimination and Restoration (EER), polar loop, LInear amplification with Nonlinear Components
(LINC), Combined Analogue Locked Loop Universal Modulator
(CALLUM), LInear amplification employing Sampling Techniques (LIST)
and transmitters based on bandpass sigma delta modulators.
Power amplifier linearization techniques are used both to improve linearity and to allow more efficient, but less linear, methods of operation. The
three principal types of linearization are feedback, feedforward and predistortion. The combination of digital signal processing (DSP) and microprocessor control allows a widespread use of complicated feedback and predistortion techniques to improve power amplifier efficiency and linearity, as
shown in Chapter 2.
In Chapter 3, methods and algorithms to compensate analog modulator
errors are reviewed, while in Chapter 4, a description of the conventional
direct digital synthesizer (DDS) is given. It is easy to include different
modulation capabilities in DDSs by using digital signal processing methods,
because the signal is in digital form. By programming the DDSs, adaptive
channel bandwidths, modulation formats, frequency hopping and data rates
are easily achieved. The digital circuits used to implement signal-processing
functions do not suffer the effects of thermal drift, aging and component
variations associated with their analog counterparts. The flexibility of the
DDSs makes them ideal as signal generator for software radios. Recursive
sinusoidal oscillators are presented in Chapter 5.
In Chapter 6, it is seen that circular rotation can be implemented efficiently using the CORDIC algorithm, an iterative algorithm for computing
many elementary functions. The CORDIC algorithm is studied in detail. The
finite word length effects in the CORDIC algorithm are investigated. Redundant implementations of the CORDIC rotator are overviewed and the hybrid

CORDIC algorithms are reviewed.
The DDS is shown to produce spurs (spurious harmonics), as well as the
desired output frequency, in Chapter 7. Different noise and spur sources are
studied in detail. In Chapter 8, a study is made of how additional digital
techniques (for example, dithering, error feedback methods) may be incorporated in the DDS in order to reduce the presence of spurious signals at


xx

Preface

the DDS output. The spur reduction techniques used in the sine output direct
digital synthesizers are reviewed.
In Chapter 9, an investigation into the blocks of the DDS, namely a phase
accumulator, a phase to amplitude converter (conventionally a sine ROM)
and a filter, is carried out. Different techniques used to accelerate the operation speed of the phase accumulator are considered. Different sine memory
compression and algorithmic techniques and their trade-offs are investigated.
D/A converters, along with the power amplifier, are the most critical
components in software radio transmitters. Unfortunately, the development
of D/A converters does not keep up with the capabilities of digital signal
processing utilizing faster technologies. The different techniques used to enhance D/A converter static and dynamic performance are reviewed in Chapter 10.
The pulse shaping and interpolation filters are the topic of Chapter 11.
Different methods of designing the pulse shaping filters are reviewed. The
multirate signal processing is particularly important in software radio transmitters, where sample rates are low initially and must be increased for efficient subsequent processing.
The multi-standard modulator has to be able to accept data with different
symbol rates. This fact leads to the need for a re-sampler that performs a
conversion between variable sampling frequencies. There are several methods of realizing the re-sampler with an arbitrary sampling rate conversion. In
Chapter 12, the design of the polynomial-based interpolation filter using the
Lagrange method is presented. Some other polynomial-based methods are
also discussed.

Three different designs to compensate the sinc(x) frequency response distortion resulting from D/A converters by using digital FIR filters are represented in Chapter 13. The filters are designed to compensate the signal’s
second image distortion.
The design and implementation of a DDS with the tunable (real or complex) 1-bit ∆¦ D/A converter are described in Chapter 14. Since the 1-bit
∆¦ D/A converter has only one bit, the glitch problems and resulting spurious noise resulting from the use of the multi-bit D/A converter are avoided.
In traditional transmit solutions, a two-stage upconversion is performed
in which a complex baseband signal is digitally modulated to the first IF (intermediate frequency) and then mixed to the second IF in the analog domain.
The first analog IF mixer stage of the transmitter can be replaced with this
digital quadrature modulator, as shown in Chapter 15.
In Chapter 16, the digital IF modulator is designed using specifications
related to GSM, EDGE and WCDMA standards. By programming a
GSM/EDGE/WCDMA modulator, different carrier spacings, modulation
schemes, power ramping, frequency hopping and symbol rates can be


Preface

xxi

achieved. By combining the outputs of multiple modulators, multicarrier
signals can be formed or the modulator chips can be used for steering a
phased array antenna. The formation of multi-carrier signals in the modulator increases the base station capacity
In a WCDMA system, the downlink signal typically has a high Peak to
Average Ratio (PAR). In order to achieve a good efficiency in the power
amplifier, the PAR must be reduced, i.e. the signal must be clipped. In Chapter 17, the effects of several different clipping methods on Error Vector
Magnitude (EVM), Peak Code Domain Error (PCDE) and Adjacent Channel
Leakage power Ratio (ACLR) are derived through simulations. A very
straightforward algorithm for implementing a peak windowing clipping
method is also presented.
In conventional base station solutions, the carriers transmitted are combined after the power amplifiers. An alternative to this is to combine the carriers in the digital domain. The major drawback of combining digital carriers
is a strongly varying envelope of the composite signal. The high PAR sets

strict requirements for the linearity of the power amplifier. High linearity
requirements for the power amplifier lead to low power efficiency and therefore to high power consumption. In Chapter 18, the possibility of reducing
the PAR by clipping is investigated in two cases, GSM and EDGE.


List of Abbreviations

ACI
ACLR
ACP
ADC
ALT1
ALT2
AM-AM
AM-PM
ASIC
BiCMOS
BPF
CALLUM
tor
CATV
CDMA
CF
CFBM
CIA
CIC
CICC
CLK
CMOS

Adjacent channel interference
Adjacent channel leakage power ratio
First adjacent channel power
Analog-digital-converter
Second adjacent channel power
Third adjacent channel power
Amplitude-dependent amplitude distortion
Amplitude-dependent phase distortion
Application specific integrated circuit
Bipolar complementary metal-oxide-semiconductor
Bandpass filter
Combined analogue locked loop universal modulaCable Television
Code division multiple access
Crest factor
Cartesian feedback module
Carry increment adder
Cascaded-integrator-comb
Custom integrated circuits conference
Clock
Complementary metal-oxide-semiconductor


xxiv
CORDIC
CP
CS
CSD
CSFR
D/A
DAC

DAMPS
dB
dBc
dBFS
DCORDIC
DCT
DDFS
DDS
DECT
DEMUX
DFF
DFT
DNL
DPLL
DRC
DSP
EDGE
EER
EF
ETSI
EVM
FET
FFT
FIR
FPGA
GCD
GMSK

Abbreviations
Co-ordinate digital computer

Carry Propagation
Carry Save
Canonic signed digit
Constant scale factor redundant
Digital to analog
Digital to analog converter
Digital-advanced mobile phone service
Decibel
Decibels below carrier
Decibels below full-scale
Differential CORDIC
Discrete cosine transform
Direct digital frequency synthesizer
Direct digital synthesizer
Digital enhanced cordless telecommunications
Demultiplexer
Delay-flip-flop
Discrete Fourier transform
Differential non-linearity
Digital phase locked loop
Design rule check
Digital signal processing
Enhanced data rates for global evolution
Envelope elimination and restoration
Error feedback
European telecommunications standards institute
Error vector magnitude
Field-effect transistors
Fast Fourier transform
Finite impulse response

Field programmable gate array
Greatest common divisor
Gaussian minimum shift keying


Abbreviations

xxv

GPRS
GSM
HPF
HSCSD
IC
IDFT
IEE
IEEE
IEICE
tion engineers
IF
IIR
IMD
INL
ISI
ISM
ISSCC
LE
L-FF
LINC
LIST

niques
LMS
LMS
LO
LPF
LSB
LTI
LUT
LVS
MAE
MSB
MSD
MUX

General packet radio service
Groupe spécial mobile
High-pass filter
High-speed circuit switched data
Integrated circuit
Inverse discrete Fourier transform
Institution of electrical engineers
Institute of electrical and electronics engineers
Institute of electronics, information and communicaIntermediate frequency
Infinite impulse response
Inter-modulation distortion
Integral non-linearity
Inter-symbol interference
Industrial, scientific and medicine
International solid-state circuits conference
Logic element

Logic-flip-flop
Linear amplification with nonlinear components
Linear amplification employing sampling techLeast-mean-square
Least mean squares algorithm
Local oscillator
Low-pass filter
Least significant bit
Linear time invariant
Look-up table
Layout versus schematic
Maximum amplitude error
Most significant bit
Most significant digits
Multiplexer


Abbreviations

xxvi
NCO
NEG
NRZ
NTF
OSC
P/I
PA
PAR
PCDE
PFD
PLD

PLL
PPM
PSK
QAM
QDDS
QM
QMC
QPSK
R/P
RF
RLS
RLS
RMS
RNS
ROM
RTL
RZ
RZ2
RZ2c
SFDR
SIR
SMS
SNDR

Numerically controlled oscillator
Negator
Non-return-to-zero
Noise transfer
Oscillator
Pipelining/interleaving

Power amplifier
Peak to average ratio
Peak code domain error
Phase/frequency detector
Programmable logic device
Phase-locked loop
Part per million
Phase shift keying
Quadrature amplitude modulation
Quadrature direct digital synthesizer
Quadrature modulator
Quadrature modulator compensator
Quadrature phase-shift keying
Rectangular-to-polar
Radio frequency
Recursive least squares algorithm
Recursive least squares
Root-mean-square
Residue number system
Read-only memory
Register transfer level
Return-to-zero
Double RZ
Double complementary
Spurious free dynamic range
Signal-to-interference ratio
Short message services
Signal to noise and distortion ratio

Abbreviations

xxvii

SNR
TDD
TDD-WCDMA
TDMA
TEKES
VCO
VHDL
VHF
VLSI
VMCD
WCDMA
XOR

Signal-to-noise ratio
Time division duplex
Time division duplex WCDMA
Time division multiple access
Technology development center
Voltage controlled oscillator
Very high speed integrated circuit HDL
Very high frequency
Very large scale integration
Voltage Mode Class-D
Wideband code division multiple access
Exclusive or

∆¦

Delta sigma