Power IC FDA2100 from ST
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FDA2100LV
2 x 180 W / 1 x 300 W PWM digital input power amplifier
with built-in diagnostics features and step-up driver
Datasheet - production data
Description
*$*36
TQFP64 (exposed pad up)
Features
Integrated 105 dB D/A conversion
I2S & TDM digital input (3.3/1.8 V)
Input sampling frequency: 44.1kHz, 48 kHz,
96 kHz, 192 kHz
Step-up driver included
EMI control for FM/AM compatibility
Dithering possibility
Capable to operate down to 6 V (e.g."start-stop")
6 V - 35 V operating range (RL = 8 Ω)
Low component count output lowpass filter
Output low-pass filter included in the feedback
Low radiation function (LRF)
High output power capability
– 2 x 80 W/4 Ω @ 25 V, 1 kHz, 10 % THD
– 2 x 120 W/4 Ω @ 30 V, 1 kHz, 10 % THD
– 1 x 150 W/2 Ω @ 25 V, 1 kHz, 10 % THD
Full I2C bus driving (3.3/1.8 V):
– I2C bus digital diagnostics (including DC
and AC load detection); AC and DC
loudspeaker diagnostic
Very flexible fault detection though integrated
diagnostic
Protected against several kinds of
misconnections
The FDA2100LV is a new BCD technology dual
bridge class D amplifier, specially intended for car
radio applications.
Thanks to the BCD6-SOI (Silicon On Insulation)
technology it is possible to integrate a high
performance D/A converter together with powerful
MOSFET output amplifier working in class D, to
get an outstanding efficiency with respect to the
standard class AB.
The D/A conversion on board allows the
performance to reach an outstanding 110 dB S/N
ratio with 105 dB of dynamic range. The feedback
loop includes the output L-C low-pass filter,
allowing superior frequency response linearity
and lower distortion independently of the inductor
and capacitor quality.
A full diagnostics array communicates the status
of each speaker through the I2C bus. The
possibility to control the device by means of the
I2C bus makes FDA2100LV very flexible.
Thanks to the solutions implemented to solve the
EMI problems, the device can intended to be
used in the standard single DIN car-radio box
together with the tuner.
A built-in step-up driver allows up to 150 W output
power with the standard 14 V supply voltage.
The FDA2100LV is moreover compliant to the
most recent OEM specifications for low voltage
operation (so called 'start-stop' battery profile
during engine stop), helping car manufacturers to
reduce the overall emissions and thus
contributing to environment protection.
Offset detector (play or mute mode)
Table 1. Device summary
Two independent short circuit protections
Clipping detector
Order code
C-MOS compatible enable pin (3.3/5 V)
FDA2100LV
ESD protection
FDA2100LV-T
Package: TQFP64 exposed pad up
September 2013
This is information on a product in full production.
Rev 1
Package
TQFP64 (e.p.u.)
Packing
Tray
Tape & reel
1/61
www.st.com
Contents
FDA2100LV
Contents
1
Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
4
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1
New feedback topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2
LC filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3
Load possibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2
Legacy mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3
I2C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4
I2C functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.5
AM operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6
EMI and dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5
Mute function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6
Diagnostics functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1
2/61
Load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.1
Turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.2
AC/DC load diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.3
Permanent diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1.4
Output current digital acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2
ExtTherm pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3
Special cases: behavior under mis-connection conditions . . . . . . . . . . . . 38
6.3.1
Case 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.2
Case 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.3
Case 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Rev 1
FDA2100LV
7
Contents
6.4
Over-current limit threshold selection Isc . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.5
Suggested diagnosic procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Integrated step-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.1
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.2
Step-up settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.3
Turn-on procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8
Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9
Low voltage (“start stop”) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10
I2S bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12
11.1
Writing procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.2
Reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.3
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.4
Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.5
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.6
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.7
I2S and I2C relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
I2C register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.1
IB0-ADDR:”00000” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.2
IB1-ADDR:”00001” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.3
IB2-ADDR:”00010” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.4
IB3-ADDR:”00011” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.5
IB4-ADDR:”00100” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.6
IB5-ADDR:”00101” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.7
IB6-ADDR:”00110” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.8
IB7-ADDR:”00111” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12.9
IB8-ADDR:”10000” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12.10 IB9-ADDR:”10001” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.11 IB10-ADDR:”10010” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Rev 1
3/61
4
Contents
FDA2100LV
12.12 DB1-ADDR:”10000” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.13 DB2-ADDR:”10001” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.14 DB3-ADDR:”10010” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.15 DB4-ADDR:”10011” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.16 DB5-ADDR:”10100” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
12.17 DB6-ADDR:”10101” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
13
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4/61
Rev 1
FDA2100LV
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pins list description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General and audio characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Step-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC test diagnostic available settings and relative thresholds and signal amplitudes . . . . . 27
AC test diagnostic available settings and relative thresholds and signal amplitudes . . . . . 28
Step up settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
IB0-ADDR:”00000” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
IB1-ADDR:”00001” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
IB2-ADDR:”00010” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
IB3-ADDR:”00011” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
IB4-ADDR:”00100” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
IB5-ADDR:”00101” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
IB6-ADDR:”00110” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
IB7-ADDR:”00111” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
IB8-ADDR:”10000” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
IB9-ADDR:”10001” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
IB10-ADDR:”10010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DB1-ADDR:”10000” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DB2-ADDR:”10001” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DB3-ADDR:”10010” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DB4-ADDR:”10011” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DB5-ADDR:”10100” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DB6-ADDR:”10101” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Rev 1
5/61
5
List of figures
FDA2100LV
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
6/61
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pins connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Switching frequency scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Minimum duty cycle for the PWM output square wave diagram . . . . . . . . . . . . . . . . . . . . . 22
Hardware mute application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Load diagnostic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Examples of 'soft-short conditions' allowed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC load diagnostic result representation considering the impedance Z
in the complex plane (Lfilter = 22µH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC load diagnostic result representation considering the impedance Z
in the complex plane (Lfilter = 10µH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Impedance phase and magnitude frequency plots of a 2 ways speaker system . . . . . . . . 32
AC load diagnostic example in practice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Permanent diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Current sensing mode 1, ADC typical characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Current sensing mode 2, ADC typical characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
External temperature warning application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Flow chart of diagnostic procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Application schematic with step-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Application schematic without step-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Worst case battery cranking curve sample 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Worst case battery cranking curve sample 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
I2S standard data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
TDM4 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
TDM8 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
I2S interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
I2C bus protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Without/with auto-increment reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
FDA2100LV communication bus interaction scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
I2C programming possibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
TQFP64 (exposed pad up) mechanical data and package dimensions . . . . . . . . . . . . . . . 59
Rev 1
FDA2100LV
Block diagram and pins description
Figure 1. Block diagram
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Figure 2. Pins connection diagram (top view)
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6DD
6DD
6DD
6DD
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1
Block diagram and pins description
*$3*36
Rev 1
7/61
60
Block diagram and pins description
FDA2100LV
Table 2. Pins list description
Pin #
Pin name
64
N.C.
63
Gnd1-
51-62
N.C.
50
Gnd2-
49
TAB
48
Feedback2-
47
Out2-
Channel 2 half bridge output -
46
Out2-
Channel 2 half bridge output -
45
Vdd2-
Channel 2 half bridge power supply -
44
Vdd2+
Channel 2 half bridge power supply +
43
Out2+
Channel 2 half bridge output +
42
Out2+
Channel 2 half bridge output +
41
Feedback2+
40
Gnd2+
39
N.C.
38
I2S-Clock
I2S/TDM clock Input
37
I2S-Sinc
I2S/TDM sinc Input
36
I2S-Data
I2S/TDM data Input
35
Test
Test pin (do not use)
34
I2C-Clock
I2C data Clock
33
I2C-Data
I2C data input
32
CD/DIAG
Clip detector and diagnostic output: over-current protection, thermal warning, offset
detection
31
Enable 2
Chip enable 2
30
Enable 1
Chip enable 1
29
PLL_Filter
PLL filter network
28
Mute
27
D-Gnd
Digital ground
26
Dig-P
Positive digital supply V(svr)+1.65 (internally generated)
25
Dig-N
Negative digital supply V(svr)-1.65 (internally generated)
24
ExtTher
External thermal protection input
23
IsetProt
Current protection resistor setting
22
SVR
Supply voltage ripple rejection capacitor
21
An-N
Negative analog supply V(svr)-1.65 (internally generated)
20
An-P
Positive analog supply V(svr)+1.65 (internally generated)
8/61
Function
Not connected
Channel 1, half bridge power ground Not connected
Channel 2, half bridge power ground TAB connection
Channel 2 half bridge feedback -
Channel 2 half bridge feedback +
Channel 2, half bridge power ground +
Not connected
Mute input (6 µA source current)
Rev 1
FDA2100LV
Block diagram and pins description
Table 2. Pins list description (continued)
Pin #
Pin name
Function
19
A-Gnd
Analog ground
18
D-Vdd
Digital power supply
17
A-Vdd
Analog power supply
16
Enable 3
15
I2
Step-up current limiting reference
14
I1
Step-up current limiting input
13
Comp
Step-up compensation input
12
Vbat
11
Gate-driver
10
SU-Gnd
Step-up power ground
9
Gnd1+
Channel 1, half bridge power ground +
8
Feedback1+
7
Out1+
Channel 1 half bridge output +
6
Out1+
Channel 1 half bridge output +
5
Vdd1+
Channel 1 half bridge power supply +
4
Vdd1-
Channel 1 half bridge power supply -
3
Out1-
Channel 1 half bridge output -
2
Out1-
Channel 1 half bridge output -
1
Feedback1-
Chip enable 3
Power supply (battery)
External PowerMOS gate drive output
Channel 1 half bridge feedback +
Channel 1 half bridge feedback -
Rev 1
9/61
60
Electrical specifications
FDA2100LV
2
Electrical specifications
2.1
Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol
Vop
Vpeak
Parameter
Test conditions
Operating supply voltage
Peak supply voltage
2
Value
Unit
RL = 4 Ω
30
V
RL = 8 Ω
35
V
t = 50 ms Max.
50
V
Vi2c
I C bus pins voltage
-
-0.3 to 4.6
V
Vi2s
I2S
bus pins voltage
-
-0.3 to 4.6
V
Enable 1,2
Enable pins voltage
-
-0.3 to 6
V
CD/DIAG
CD/DIAG pin
-
-0.3 to 6
V
30V Max.
7.2
A
35V Max.
4
A
-
200
kHz
-
55 to 150
°C
-
–40 to 105
°C
IO
Fs max
Tstg, Tj
Tamb
Output peak current (repetitive f > 10 Hz)(1)
Max. input sample rate
Storage and junction
temperature(2)
Operative temperature range
1. For internal current limitation value refer to Section 6.4.
2. A suitable heatsink should be used to keep Tj inside specified limits.
2.2
Thermal data
Table 4. Thermal data
Symbol
Rth j-case
2.3
Parameter
Thermal resistance junction-to-case
Max.
Value
Unit
2
°C
Electrical characteristics
Refer to the test circuit, Vdd = Vbatt = 14.4 V; RL = 4 Ω; f = 1 kHz; Tamb = 25 °C; unless
otherwise specified. Tested at Tamb = 25 °C and Thot = 105 °C; functionality guaranteed for
Tj = -40 °C to 150 °C. Fsample = 48 kHz; PWM 'in phase'; unless otherwise specified.
Table 5. General and audio characteristics
Symbol
Parameter
Test condition
RL = 2 Ω
Vdd, Vbatt
Supply voltage range
RL = 4 Ω
Typ.
Max.
Unit
6
-
18(1)
V
-
(1)
30
V
-
35(1)
V
6
RL = 8 Ω
10/61
Min.
6
Rev 1
FDA2100LV
Electrical specifications
Table 5. General and audio characteristics (continued)
Symbol
Parameter
2
2
Test condition
Min.
Typ.
Max.
Unit
I C, I S bus pins
voltage
-
-
-
3.6
V
Venable
Enable pins voltage
-
-
-
5.5
V
CD/Diag
CD/Diag pin voltage
-
-
-
5.5
V
Idvbatt
Total quiescent drain
current pin Vbatt
Device in standby condition
-
-
2
µA
Idvdd
Total quiescent drain
current pins Vdd
Device in standby condition
-
-
5
µA
Idvbatt
Total quiescent drain
current pin Vbatt
Device ON
-
32
40
mA
Idvdd
Total quiescent drain
current pins Vdd
Device ON
-
80
100
mA
RL = 4 Ω; max power Vdd = 15.2 V
42(2)
50(2)
-
W
THD = 10 %
23(2)
29(2)
-
W
RL = 2 Ω; THD 10 %
38(2)
50(2)
-
W
RL = 2 Ω; max power
57(2)
78(2)
-
W
Vdd: 25 V; max power
-
135(2)
-
W
Vdd: 25 V; THD = 10 %
72(2)
80(3)
-
W
Vdd: 30 V; THD = 10 %
100(2)
120(3)
-
W
Vdd: 30 V; max power
-
180(3)
-
W
Total harmonic
distortion
PO = 1 W to 10 W, f = 1 kHz
-
0.03
00.5
%
PO = 1 W to 10 W, f = 10 kHz
-
0.2
0.5
%
CT
Cross talk
f = 1 kHz to 10 kHz
60
80
-
dB
GV1
Voltage gain high
GAIN @ -10 dBFS
44.1-48 and 96 KHz
192 kHz
9.3
11.5
10.3
13
11.3
14.5
Vp
Voltage gain low
GAIN @ -10 dBFS
44.1-48 and 96 KHz
192 kHz
5.5
6.7
6
7.6
6.5
8.5
Vp
Voltage gain match
-
-1
-
1
dB
DR
Dynamic range
-
-
108
-
dB
Awtd(3)
EIN1
Output noise GV = GV1
A-wtd, no output signal
-
75
100
µV
SNR
Signal to noise ratio
A-wtd
-
110
-
dB
A-wtd
SVR
Supply voltage rejection f = 1 kHz; Vr = 1 Vpk;
60
85
-
dB
Mute pin source current -
3
6
9
µA
VI2C, VI2S
PO
THD
GV2
GV1,2
IM
Output power (2)
Rev 1
11/61
60
Electrical specifications
FDA2100LV
Table 5. General and audio characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VMth
Mute pin voltage
threshold
-
1.6
2.2
2.6
V
VMcl
Mute pin internal clamp
voltage
-
4.3
5
5.5
V
AM
Mute attenuation
-
80
100
-
dB
VOS
Offset voltage
Mute and play
-20
-
20
mV
IB5-D4-5 I2C setting = 00
and legacy mode (Min)
5.4
5.7
6.0
V
IB5-D4-5 I2C setting = 01 (Med.)
6.75
7.25
7.75
V
7.8
8.4
9.0
V
IB5-D4-5I2C setting = 00
and legacy mode (Min.)
5.0
5.3
5.7
V
IB5-D4-5 I 2C setting = 01 (Med.)
6.4
6.8
7.2
V
7.5
8.0
8.5
V
-
0.1
0.3
0.5
V
IB5-D6-7 I2C setting = 00
and legacy mode (Min.)
5.4
5.7
6.0
V
-
7.5
-
V
-
8.8
-
V
IB5-D6-7
setting = 00
and legacy mode (Min.)
5.0
5.3
5.7
V
IB5-D6-7 I2C setting = 01 (Med.)
6.4
6.8
7.2
V
7.5
8.0
8.5
V
0.1
0.3
0.5
V
VAMVbatt
Vbatt supply mute
threshold (4)
2C
IB5-D4-5 I
VUVVbatt
Vbatt supply UVLO
threshold (4)
2C
IB5-D4-5 I
VUVhyst
VAMVdd
Vbatt supply UVLO
hysteresis (4)
Vdd supply mute
threshold (4)
setting = 10 - 11 (Max.)
setting = 10 - 11 (Max.)
IB5-D6-7 I2C setting = 01 (Med.)
2C
IB5-D6-7 I
setting = 10 - 11 (Max.)
I2C
VUVVdd
Vdd supply UVLO
threshold (4)
2C
IB5-D6-7 I
setting = 10 - 11 (Max.)
Vbatt supply UVLO
hysteresis (4)
-
CDLK
Clip det high leakage
current
CD off
-
0
15
µA
CDSAT
Clip det sat. voltage
CD on; ICD = 1 mA
-
150
300
mV
Clip det THD
THD@100 Hz with average
Vclipdet = 2 V
(pull-up resistor = 10 k to 3.3 V)
5
10
15
%
TslowM
Slow mute delay
-
85
100
115
ms
TfastM
Fast mute delay
-
1.7
2
2.3
ms
VUVhyst
CD1THD (5)
1. Maximum value at ATE = 25 V with 4 ohm load. 35 V tested w/o load.
2. Test correlated to the RdsON measurement (ATE test).
3. Value measured at bench (not tested at ATE).
4. Tested in 00 configuration only.
5. Not tested at ATE.
12/61
Rev 1
FDA2100LV
Electrical specifications
Table 6. Diagnostics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Turn on test (short to GND, short to Vs) current thresholds
Pgnd
No short to GND det. (below this
output current limit, the output is considered in normal conditions)
-
-
3
mA
Pps
No Short to positive Supply det.
(below this output current limit,
the output is considered in
normal conditions)
-
-
-3
mA
Pgnd
Short to GND det. (over this
output current limit, the output is
considered in short circuit to
GND)
30
-
-
mA
Pps
Short to positive Supply det.
(over this output current limit,
the output is considered in short
circuit to VS)
-30
-
-
mA
-
267.5
-
ms
AC-DC load diagnostic test timing
Tlt
Load test time (AC+DC)
Fs = 44.1 kHz
Tac
AC sweep length
-
-
20.5
-
ms
Tdc
DC pulse length
-
-
247
-
ms
Fac
AC test internal signal
generated frequency value
(1)
-
19.3
-
kHz
DC test - Low Gain
Vdc(2)
DC test output amplitude value
Differential signal
Rdc setting = Option 1
0.53
0.58
0.63
V
Vdc(2)
DC test output amplitude value
Differential signal
Rdc setting = Option 2
1.05
1.15
1.25
V
Vdc(2)
DC test output amplitude value
Differential signal
Rdc setting = Option 3
2.11
2.3
2.49
V
Vdc(2)
DC test output amplitude value
Differential signal
Rdc setting = Option 4
0.27
0.29
0.31
V
0.63
-
4.3
Ω
DC test - Low Gain - Rsetting = Option 1
Rdcnl
Normal load
DC diagnostic short
threshold selection = 00
Rdcsl
Shorted load
-
-
-
0.4
Ω
Open load
DC diagnostic short
threshold selection = 00
17
-
-
Ω
1.25
-
8.6
Ω
-
-
0.8
Ω
34
-
-
Ω
Rdcol
DC test - Low Gain - Rsetting = Option 2
Rdcnl
Normal load
DC diagnostic short
threshold selection = 00
Rdcsl
Shorted load
-
Rdcol
Open load
DC diagnostic short
threshold selection = 00
Rev 1
13/61
60
Electrical specifications
FDA2100LV
Table 6. Diagnostics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
2.5
-
17
Ω
-
-
1.6
Ω
68
-
-
Ω
0.35
-
2.15
Ω
-
-
0.2
Ω
DC test - Low Gain - Rsetting = Option 3
Rdcnl
Normal load
DC diagnostic short
threshold selection = 00
Rdcsl
Shorted load
-
Rdcol
Open load
DC diagnostic short
threshold selection = 00
DC test - Low Gain - Rsetting = Option 4 (intended for low ohminc speakers)
Rdcnl
Normal load
DC diagnostic short
threshold selection = 00
Rdcsl
Shorted load
-
Rdcol
Open load
DC diagnostic short
threshold selection = 00
8.5
-
-
Ω
AC test - Low Gain
Vac(2)
AC test output amplitude value
Single ended signal
Rac setting = Option 1
0.83
0.9
0.98
Vp
Vac(2)
AC test output amplitude value
Single ended signal
Rac setting = Option 2
1.65
1.8
1.95
Vp
Vac(2)
AC test output amplitude value
Single ended signal
Rac setting = Option 3
3.30
3.6
3.9
Vp
AC test - Low Gain - Rsetting = Option 1
Zmeas(nl)
Normal load
-
-
-
6
Ω
Zmeas(ol)
Open load
-
20
-
-
Ω
AC test - Low Gain - Rsetting = Option 2
Zmeas(nl)
Normal load
-
-
-
12
Ω
Zmeas(ol)
Open load
-
40
-
-
Ω
AC test - Low Gain - Rsetting = Option 3
Zmeas(nl)
Normal load
-
-
-
24
Ω
Zmeas(ol)
Open load
-
80
-
-
Ω
DC test - High Gain
Vdc(2)
DC test output amplitude value
Differential signal
Rdc setting = Option 1
0.9
1
1.1
V
Vdc(2)
DC test output amplitude value
Differential signal
Rdc setting = Option 2
1.81
2
2.19
V
Vdc(2)
DC test output amplitude value
Differential signal
Rdc setting = Option 3
3.61
4
4.39
V
Vdc(2)
DC test output amplitude value
Differential signal
Rdc setting = Option 4
0.45
0.5
0.55
V
14/61
Rev 1
FDA2100LV
Electrical specifications
Table 6. Diagnostics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
1.08
-
7.4
Ω
-
-
0.68
Ω
DC test - High Gain - Rsetting = Option 1
Rdcnl
Normal load
DC diagnostic short
threshold selection = 00
Rdcsl
Shorted load
-
Rdcol
Open load
DC diagnostic short
threshold selection = 00
29
-
-
Ω
2.17
-
15
Ω
-
-
1.39
Ω
DC test - High Gain - Rsetting = Option 2
Rdcnl
Normal load
DC diagnostic Short
Threshold selection = 00
Rdcsl
Shorted load
-
Rdcol
Open load
DC diagnostic Short
Threshold selection = 00
59
-
-
Ω
4.3
-
30.1
Ω
-
-
2.78
Ω
118
-
-
Ω
0.54
-
3.71
Ω
-
-
0.34
Ω
DC test - High Gain - Rsetting = Option 3
Rdcnl
Normal load
DC diagnostic short
threshold selection = 00
Rdcsl
Shorted load
-
Rdcol
Open load
DC diagnostic Short
Threshold selection = 00
DC test - High Gain - Rsetting = Option 4 (intended for low ohminc speakers)
Rdcnl
Normal load
DC diagnostic short
threshold selection = 00
Rdcsl
Shorted load
-
Rdcol
Open load
DC diagnostic short
threshold selection = 00
14.7
-
-
Ω
AC test - High Gain
Vac(2)
AC test output amplitude value
Single ended signal
Rac setting =Option 1
1.26
1.4
1.54
Vp
Vac(2)
AC test output amplitude value
Single ended signal
Rac setting = Option 2
2.53
2.8
3.07
Vp
Vac(2)
AC test output amplitude value
Single ended signal
Rac setting = Option 3
5.06
5.6
6.14
Vp
AC test - High Gain - Rsetting = Option 1
Zmeas(nl)
Normal load
-
-
-
8
Ω
Zmeas(ol)
Open load
-
30
-
-
Ω
AC test - High Gain - Rsetting = Option 2
Zmeas(nl)
Normal load
-
-
-
16
Ω
Zmeas(ol)
Open load
-
60
-
-
Ω
AC test - High Gain - Rsetting = Option 3
Zmeas(nl)
Normal load
-
-
-
32
Ω
Zmeas(ol)
Open load
-
120
-
-
Ω
Rev 1
15/61
60
Electrical specifications
FDA2100LV
Table 6. Diagnostics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Short to GND det. (over this
Power amplifier in Mute or
output current limit, the output is
play, one or more short
considered in short circuit to
circuits protection activated
GND)
30
-
-
mA
Short to Vs det. (over this output
current limit, the output is
considered in short circuit to VS)
-30
-
-
mA
-
-
-
±3
mA
-
Permanent diagnostics
Pgnd
Pvs
Pnop
Normal operation thresholds.
(Within these output current
limits, the output is considered
without faults)
Vo
Offset detection -
Output voltage (Gain High)
Vo
Offset detection
Output voltage (Gain Low)
4.3
-
V
2.2
-
V
Tph
Thermal protection junction
temperature
Gain attenuation of 60 dB
-
165
-
°C
Tpl
Thermal protection junction
temperature
Gain attenuation of 0.5 dB
-
155
-
°C
Tw1
Thermal warning junction
temperature
-
-
Tpl-5
-
°C
Tw2
Thermal warning junction
temperature
-
-
Tpl-20
-
°C
Tw3
Thermal warning junction
temperature
-
-
Tpl-35
-
°C
Fn
External thermal Sensor
Comparator Input normal
threshold value
Fn ≥ V(ExtTher)-V(AN-n)
1.9
-
-
V
Fw
External thermal sensor
comparator Input warning
threshold
Fw ≤ V(ExtTher)-V(AN-n)
-
-
1.4
V
Fh
External thermal sensor
comparator Input hysteresis
-
0.1
-
-
V
Vt
Comparator input test mode
-
0.2
-
0.6
V
1. Frequency digitally controlled by locking to
I 2S
clock.
2. Min/max test correlated to GV1, GV2 measurements.
16/61
Rev 1
FDA2100LV
Electrical specifications
Table 7. Step-up
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
1.4
1.55
1.7
V
Step-up
V(Comp)
I2C mode, v18 settled
Compensation pin voltage
2
V(Comp)
Compensation pin voltage
I C mode, v20 settled
1.55
1.7
1.95
V
V(Comp)
Compensation pin voltage
I2C mode, v22.5 settled
1.7
1.85
2
V
2
V(Comp)
Compensation pin voltage
I C mode, v25 settled and
legacy mode
1.85
2
2.15
V
V(Ilim)
Current limiting threshold
voltage(1)
V(I1-V(I2)
0.18
0.25
0.32
V
Vgdl
V gate drive low voltage
Isink = 0.5 A
Isink = 20 mA
-
-
2
0.1
V
Vgdh
V gate drive high voltage
Isource = 0.5 A
Isource = 20 mA
7
9
-
-
V
1. Applying this voltage to the pins I1, I2 the output voltage decreases, and the flag DB1-D7 must be set at 1.
Table 8. Interfaces
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
-
-
400
kHz
I2C bus interface
fSCL
Clock frequency
-
VIL
Input low voltage
-
-
-
0.8
V
VIH
Input high voltage
-
1.3
-
-
V
VOLMAX
Maximum low output voltage I2C
Isink = 3 mA
data
-
-
0.5
V
IOLMAX
Maximum low output current I2C
data
-
-
1
mA
ILIMAX
Maximum input leakage current
-
-
±1
µA
-
Enable 1,2,3
Venl
Input low voltage
-
-
-
1.5
V
Venh
Input high voltage
-
2.3
-
-
V
I2S bus interface
VIL-I2S
Input low voltage
-
-
-
0.8
V
VIH-I2S
Input high voltage
-
1.3
-
-
V
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General introduction
3
FDA2100LV
General introduction
The FDA2100LV is a fully digital single chip class D amplifier with high immunity to the
demodulation filter effects, built-in diagnostic functions and step-up driver. The high
integration level and the on-board signal processing allow an excellent audio performance
to be achieved. Thanks to the digital input and a feedback strategy in the power stage that
make the amplifier robust with respect to the output filter non-idealities, the number and size
of the external components are minimized. A number of features were is also included to
reduce EMI, making the system compliant with the stringent limits typical of automotive
applications and the fully digital approach provides a strong GSM immunity.
The FDA2100LV includes digital I2C and I2S interfaces, internal 20 bits DAC conversion,
digital signal processing for interpolation and noise shaping, step-up driver, self diagnostic
functions and automatic detection of wrong load connections or variation of the load with
respect to the expected one, internal PLL for a pure clock generation.
3.1
New feedback topology
Differently from the typical PWM switching amplifiers, a new feedback technique is adopted
by FDA2100LV. The LC filter is included in the feedback loop making the amplifier highly
insensitive to the characteristics of such a demodulator group. This solution optimizes the
system performance in terms of THD and frequency response.
Regardless of the big phase shifting introduced by the output filter the device shows a great
phase margin for any load condition.
The system stability has been tested taking in account:
Spread process
PWM switching variation (from 300 to 440 kHz)
Silicon temperature variation (from -40 to 150 °C)
Load variation (both inductive and capacitive considered)
LC demodulator filter variation and tolerance
Voltage supply variation (from 6 to 35 V)
The system has been designed to guarantee a phase margin > 45 deg for any working
condition.
The new feedback topology assures a strong control of voltage and current across the load
making the diagnostic load detection reliable.
3.2
LC filter design
The audio performance of a Class D amplifier is heavily influenced by the characteristics of
the output LC filter. The choice of its components is quite critical because a lot of constraints
have to be fulfilled at the same time: size, cost, effective EMI filtering, efficiency.
In particular, both the inductor and the capacitor exhibit a non linear behavior: the value of
the inductance is a function of the instantaneous current in it and similarly the value of the
capacitor is a function of the voltage across it.
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FDA2100LV
General introduction
In a classical approach, in which the feedback loop is closed right at the output of the power
stage, the LC filter is placed outside the loop and these nonlinearities cause the Total
Harmonic Distortion (THD) to increase. The only way to avoid this phenomenon would be to
use components which are highly linear, but this means they are also bigger and/or more
expensive.
Furthermore, when the LC filter is outside the loop, its frequency response heavily depends
on the impedance of the loudspeaker; this is one of the most critical aspects of Class-D
amplifiers. It can be mitigated, but not solved, by means of additional snubber networks,
increasing cost, volume and power dissipation.
The FDA2100LV proposes a novel strategy to include the output LC filter in the feedback
loop for Class D stages with pulse width modulation at fixed carrier in order to minimize the
effect of the filter itself on the global performances of the system.
However, since the demodulator group is now in the feedback path, some constraints
regarding the inductor and capacitor choice are still present but of course less stringent than
a typical switching application. For additional details, please refer to the Client Pack
documentation for further information.
3.3
Load possibilities
The FDA2100LV supports several load possibilities and configurations. Unless specified by
means of I2C bus communication, the default configuration is suitable for a 2 channels
application. By means I2C bus it is possible to choose a single channel solution with parallel
outputs.
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Operation mode
4
FDA2100LV
Operation mode
The device has four main operation modes:
Standby mode
Legacy mode 1(in phase)
Legacy mode 2 (not in phase)
I2C mode
These operations are selected by the pins ENABLE1, ENABLE2 and ENABLE3 following
the next table:
Table 9. Operation mode
Operation
ENABLE1
ENABLE2
ENABLE3
Standby mode
0
0
0
Legacy mode 1 (in phase)
1
0
0
Legacy mode 2 (not in phase)
1
0
1
I2C mode address 1 - (1101000)
0
1
0
I
2C
mode address 2 - (1101001)
1
1
0
I
2C
mode address 3 -(1101010)
0
0
1
I
2C
mode address 4 - (1101011)
Reserved (test mode)
4.1
0
1
1
1
1
1
Standby mode
When the ENABLE1, ENABLE2, ENABLE3 pins are low the device is in standby mode. The
current consumption is ISB.
4.2
Legacy mode
With an appropriate selection of ENABLE1/2/3 it is possible to select two Legacy modes (in
phase/ not in phase). When either Legacy mode 1 or Legacy mode 2 is selected, the
I2C bus is disabled (it is not possible to send commands to the amplifier or to receive data
from device to the µP).(a)
4.3
I2C mode
Refer to Table 9 for the description of ENABLE1/2/3 combinations that bring device in
I2C bus mode, with addresses "1", "2", "3" and "4" respectively. In this way, 4 devices can be
easily used in a board with a single I2C bus.
When a valid combination of ENABLE1/2/3 is recognized, the device turns on the internal
supply voltage of the I2C interface (and after ~5ms becomes ready to be programmed).
The internal I2C registers are pre-settled in "default condition", waiting for the I2C next
instruction.
a. Although in legacy mode the I2C bus is not effective, the device recognizes the address with the acknowledge.
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Rev 1
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4.4
Operation mode
I2C functions
Several functions can be enabled/disabled by means of an I2C serial communication bus.
Here a simplified list of the main I2C options:
Step-up driver settings (ON/OFF, output voltage selection, clock dithering,
Soft start activation, auto-off function for high chip temperature)
Amplifier gain selection (high/low gain)
Power stage ON/OFF control channel by channel
Parallel outputs configuration
Slow/Fast play and mute functions
High pass filtering for the digital input signal
Woofer and tweeter mis-connections test settings
Low Radiation Mode (anti pulse-skipping function)
I2S / TDM 4/8 channels
44.1 kHz, 48 kHz, 96 kHz, 192 kHz word frame clock selection
PWM switching frequency selection
PWM and/or PLL clock dithering
Thermal warning selection
Mute/Unmute function
Under voltage warning events
LC filter output filter selection
Any detected fault condition will be reported by means I2C, included shorts event to Vdd,
GND and mixed mis-connections, over voltage, over-temperature, digital offset warning.
The FDA2100LV can work in slave mode only.
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Operation mode
4.5
FDA2100LV
AM operation mode
In order to assure EMC in an AM band it is advisable to exploit special functions provided by
FDA2100LV. By means of I2C interface, a suitable switching frequency can be set
depending on the AM station selected by the tuner. The switching frequency can be
selected just in case the input signal frequency sample is 44.1 kHz or 48 kHz.
Figure 3. Switching frequency scheme
K (Z
K (Z
K(Z )3 FRAME CLOCK
07- SWITCHING FREQUENCY
K (Z
K (Z
K(Z )3 FRAME CLOCK
K (Z
07- SWITCHING FREQUENCY
K (Z
'!0'03
Actually, the PWM spectrum of the output square wave can be controlled in AM band just in
case it is possible to fix the switching frequency, in other words without skipping any power
stage commutation (typical phenomenon for a class D amplifier close to the clipping). That's
why FDA2100LV offers an additional control called LRF (low radiation function). This I2C
option assures a minimum duty cycle for the PWM output square wave avoiding any missing
pulses.
Figure 4. Minimum duty cycle for the PWM output square wave diagram
MISSING COMMUTATION
6SS
./ ,2&
6SS
FORCED COMMUTATION
6SS
,2&
6SS
#LIPPING WITHOUT ,2&
#LIPPING WITH ,2&
6SS
'!0'03
Consequently, by limiting the PWM duty cycle, a limitation of the output power occurs (the
output power in case of usage of LRF function decreases about 10 % @ 1 % THD).
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FDA2100LV
4.6
Operation mode
EMI and dithering
The best audio performances of the FDA4100 are obtained in the following conditions:
PWM "in phase"
No PLL dithering
No PWM dithering
The EMI test result shows the compliance of the device at the CEI EN 55025 (2009-10) also
in the above mentioned “standard” condition.
To increase the flexibility of the device in terms of EMI some added features are
implemented:
Selectable PWM output frequency
PWM “out of phase” possibility
PLL dithering possibility
PWM dithering possibility
Generally speaking these features (except for the PWM output frequency selection) are
slightly degrading the audio performance.
In AM operation mode, PWM dithering is not suggested, because increases the spread of
the switching frequency, reducing in turn the “spurious free” band.
PWM dithering is allowed only in the followings PWM switching frequency:
358.2 kHz in case of I2S @ 44.1 kHz
384 kHz in case of I2S @ 48 kHz
Rev 1
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Mute function
5
FDA2100LV
Mute function
The FDA2100LV offers two different ways to mute the IC:
1.
Software mute
Through I2C bus, selecting the bits IB6 - D1 and IB6 - D0, it is possible mute/unmute
the channels 1 and 2 respectively. (see Table 21) The mute/unmute behavior is soft,
with ramps duration of 2 ms (fast mute) or 100 ms (slow mute) depending on the bit
IB1 - D1. (see Table 16)
2.
Hardware mute
The pin "Mute" acts as mute for all the channels. The device is muted when this pin is
low (VMute <1.6V) while is in play when this pin is high (VMute > 2.6 V).
Inside the device, connected to this pin a 6 uA pull-up current generator puts the device
in play if left floating.
A 5 V internal clamp limits the Mute pin voltage. If not used, this pin must remain
floating.
To drive the Mute pin to get a hardware mute, an external pull-down open drain (QMute)
5 V tolerant is needed. (see Figure 5) RMute must be < 100k.
The typical time constant to reach the typical mute threshold (2.1 V) is:
TMute = CMute x 350k
TUnmute = CMute x RMute x 350k/(RMute + 350k)
Figure 5. Hardware mute application schematic
2-UTE
!
-UTE
6-UTE
2EF-UTE
#-UTE
'!0'03
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Rev 1
FDA2100LV
6
Diagnostics functional description
Diagnostics functional description
The FDA amplifiers family provides diagnostic functions to detect several possible fault
conditions. Any warning information will be stored in the I2C interface and kept until the first
I2C bus reading operation. Here reported the FDA2100LV's diagnostic features:
6.1
Load detection
Under/over voltage events
Chip over temperature
Digital input offset
Output clipping
Over temperature of an external component (i.e. step-up DMOS) through a suitable
NTC external sensor
Output current digital acquisition
Load detection
A new concept of load diagnostic is provided by the FDA family, specially designed for
automotive applications. Advanced digital algorithms make tests extremely reliable.
The FDA family load diagnostic is performed in three phases and can be classified in:
Turn on diagnostic
AC/DC diagnostic
Permanent diagnostic
While turn on and permanent tests are automatically made by FDA, AC/DC can be
enabled/disabled by means of I2C bus.
During AC/DC load test the I2C acknowledge is kept low.
AC/DC load test signal is generated and test is done, independently of software mute value
(IB6 D0-D1), only if:
1.
operation mode passes from st-by to I2C mode through enable pin setting;
2.
DC test enable is 1 (IB2 D7);
3.
the desired channel is put in working mode (IB1 D7-D6);
4.
FDA is NOT kept in hardware mute (by means of the dedicated pin).
This means that if the first I2C programming sets PWM off in a channel, the test is not made
on that channel (relative test result must be discharged). To perform a test on that channel,
or simply to repeat the load detection test, the amplifier must be switched off by enable pins
(operation mode set to 000), and the I2C setting re-sent.
Out of phase modulation option, if desired, must be selected after the AC-DC load
diagnostic execution to avoid pop noise.
Rev 1
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