VLSI design and test for systems dependability

Shojiro Asai Editor

VLSI Design
and Test for
Systems
Dependability


VLSI Design and Test for Systems Dependability


A group picture of participants in the DVLSI Program: researchers from universities, national
laboratories and industry, external program advisors and the staff members of JST are
photographed. 13 March, 2013


Shojiro Asai
Editor

VLSI Design and Test
for Systems Dependability

123


Editor
Shojiro Asai
Rigaku Corporation
Tokyo
Japan

ISBN 978-4-431-56592-5
ISBN 978-4-431-56594-9
/>
(eBook)

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Preface

The technological progress, with its tremendous economic impact, of electronic

systems stands out among other industrial products of modern times and has produced various innovations over the last 50 years or so. It has had two major
enablers, computer programs and the very-large-scale integration (VLSI) of semiconductor circuits. The concept of programed computing first materialized in
computers that crunched alphanumeric data. The computer program has gone
through a remarkable transformation since the introduction of high-level programing languages, close in form to human languages, describing how information
is to be processed in the system; translating the program into machine-executable
codes became a part of the job of computers. Electronic systems hardware has
likewise shown progress in performance at an unprecedented pace starting out from
the vacuum tube to the transistor to VLSI. High-performance computers, consisting
of thousands of VLSI processors, each one containing billions of transistors, are
being used for scientific calculations and big-data analysis. More remarkably, VLSI
is used today in a far greater variety of electronic systems. Public infrastructures,
such as transportation, utilities, public safety, and telecommunications, are
large-scale electronic systems. Consumer items such as cell phones and automobiles are other examples of advanced electronic systems. All these electronic systems, in contrast to computers used for general computing, are customarily called
computer-embedded systems. Progress in the development of these systems has
been driven by the evolution of computer software (programing) and electronic
hardware (VLSI among others), considered as twin engines working in harmony.
The three most important value metrics of an electronic system are performance,
cost (price), and dependability. All three are carefully considered when a user is
about to buy a system, or a manufacturer contemplates developing a system for sale.
What is meant by performance and cost (price) is obvious and is talked about in
terms of straightforward quantitative metrics. The concept of dependability, a term
that has evolved from reliability, has expanded its attributes to range from a relatively simple quantity, such as mean time to failure (MTTF), a good statistical index
of the availability of systems, to far harder to quantify metrics such as safety and
tamper resistance. The bearings of dependability have become much more
v


vi

Preface

important as humans increasingly rely on the convenience and benefit of electronic
systems while the scale and severity of the detrimental effects of potential failures in
such systems have become more devastating. The purpose of this book is to discuss
how design and testing can help mitigate threats to the dependability of VLSI
systems. Here the term VLSI system is meant to cover not only VLSI per se but also
electronic systems that use VLSI (of semiconductor circuits) as a key component.
This book consists of three parts. Part I is a general introduction to the book and
is made up of two chapters. It starts by describing in Chap. 1 the background and
motivation that led to the undertaking of a government-funded research program
entitled, “Fundamental technologies for dependable VLSI systems (called DVLSI
hereafter),” funded by the Japan Science and Technology Agency (JST) under the
Core Research of Evolutional Science and Technology (CREST) initiative. The
program was started in April 2007 and lasted for about 8 years until March 2015,
with 11 teams of researchers participating from universities, government laboratories, and industrial corporations. The rest of Chap. 1 describes the scope, activities, and management of the program. Detailed accounts are given as to how
overarching issues of dependability were covered, how efforts were made to push
expected deliverables toward applications, how exciting industry–academia collaborations were promoted during the term, and the final outcomes of the program.
Chapter 2 begins with a quick overview of the principles and disciplines of design
and verification/testing of electronic systems. Then, using this as a background, the
implications of new technologies developed in the DVLSI program are discussed in
light of other emerging trends in technology and the markets.
Part II of this book is entitled, “VLSI Issues in Systems Dependability.”
Chapters 3 through 12 discuss various threats to the dependability of VLSIs: ionizing radiation, electromagnetic interference, time-dependent degradation, variations in device characteristics, design errors, malicious tampering, etc., and what
design and testing can do to manage these threats. Part III, which is entitled,
“Design and Test of VLSI for Systems Dependability,” consists of Chaps. 13
through 29, which describe technologies developed in the program as possible
solutions for dependability in the design and testing of realistic systems such as
robots and vehicles, data processing and storage in the cloud environment, wireless
public telecommunications with improved connectivity, advanced electronic
packaging with wireless interconnect, and so forth. Most chapters and sections of

Part II and Part III are authored by the members of research teams in the DVLSI
program, but some are contributed by “invited” authors, who, having participated in
the various events of the program in one way or other, kindly agreed to express their
thoughts in this book.
This book is intended to be a reference for engineers who work on the design
and testing of electronic systems with particular attention on dependability. It can
be used as an auxiliary textbook in undergraduate and graduate courses as well. It is
also hoped that readers of this book with non-engineering backgrounds, such as
mathematics and social economists, will gain insight into the problems of systems
dependability, and may consider taking them on as innovative challenges.


Preface

vii

It was a real pleasure to be able to work with the members of the DVLSI
program, and to witness industry–university collaborations from inception to fruition. I am thankful to numerous speakers from outside the program who gave
stimulating talks and shared thoughts and discussions at program conferences. It
was good to have been able to interact and exchange ideas with scholars and
engineers from various parts of the world (the United States, China, Taiwan, India,
and Germany) including active members of the United States program,
“Failure-Resistant Systems (FRS)” sponsored by the National Science Foundation
(NSF) and the Semiconductor Research Corporation (SRC), and the German program, “SPP1500 Dependable Embedded Systems,” sponsored by the Deutsche
Forschungsgemeinschaft (DFG). I only wish we had closer interactions between
these programs—FRS (2013–present), SPP1500 (2012–2016), and DVLSI (2007–
2015)—with more overlapping elements.
My heartfelt thanks go to the following gentlemen: Tohru Kikuno, Atsushi
Hasegawa, Masatoshi Ishikawa, Yoshio Masubuchi, Naoki Nishi, Koki Noguchi,
Tadayuki Takahashi, Koichiro Takayama, and Kazuo Yano, all of whom are

advisory members of the DVLSI program. I would like to thank JST and all its
management and staff members for their encouraging and patient support for this
program: Kazunori Tsujimoto, Shinobu Masubuchi, Daichi Terashita, Toshiaki
Ikoma, Michiharu Nakamura, and the late Koichi Kitazawa, to name but a few.
I would like to thank Toyota Motors Corporation for kindly providing a chart
describing the power train of a hybrid vehicle to be used in this book as an
illustration, and the Xilinx Company for kindly agreeing that the use of a chart
showing an FPGA (Field Programmable Gate Array) coupled with an ARM (ARM
is a company that provides an embedded processor architecture) processor, could be
included in this book.
I am also thankful to Hikaru Shimura of the Rigaku Corporation who generously
allowed me to spend some of my time on the job overseeing this program, and to
his technical staff members, of which Kenji Wakasaya was one, who kindly shared
their experience in systems design. I am thankful to Binu Thomas of Quest Global,
a partner of Rigaku’s in software development, for sharing his thoughts about
verification and testing. I cannot thank my colleagues enough at Hitachi Ltd. for
stimulating and helping me form ideas about what systems design is. Just to single
out a person from the many I worked with, Masayoshih Tsutsumi was an engineer–
philosopher who shared his great insight into how to guide thoughts in designing a
product, which I have tried to reproduce, only to a very limited extent, in Chap. 2.
My last thanks go to Shigeru Oho and Koki Noguchi for thoroughly reviewing the
first two chapters and suggesting many important and necessary corrections.
Tokyo, Japan
March 2017

Shojiro Asai


Contents

Part I
1

2

Introduction

Challenges and Opportunities in VLSI for Systems
Dependability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shojiro Asai
1.1 VLSI in Electronic Systems and Their Dependability
1.2 Background and Motivation for the Program . . . . . .
1.3 Threats and Opportunities for the VLSI Systems . . .
1.4 The DVLSI Program . . . . . . . . . . . . . . . . . . . . . . . .
1.5 A Summary of Results . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Design and Development of Electronic Systems for Quality
and Dependability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shojiro Asai
2.1 Core Considerations in Designing an Electronic System
Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Design and Development of an Electronic System Product .
2.3 Process and Management of Product Development . . . . . . .

2.4 Risk Assessment and Refinement of Design Against Risks .
2.5 Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . .
2.6 Appendix to Chapter 2: The Case of a Scientific Instrument
System—An Example Electronic System . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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ix


x

Contents

Part II
3

4

5

VLSI Issues in Systems Dependability

Radiation-Induced Soft Errors . . . . . . . . . . . . . . . . . . . . . . . .
Eishi H. Ibe, Shusuke Yoshimoto, Masahiko Yoshimoto,
Hiroshi Kawaguchi, Kazutoshi Kobayashi, Jun Furuta,
Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye,

Hiroyuki Kanbara, Hiroyuki Ochi, Kazutoshi Wakabayashi,
Hidetoshi Onodera and Makoto Sugihara
3.1 Fundamentals and Highlights in Radiation-Induced
Soft-Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Soft-Error Tolerant SRAM Cell Layout . . . . . . . . . . . . . .
3.3 Radiation-Hardened Flip-Flops . . . . . . . . . . . . . . . . . . . .
3.4 Soft-Error-Tolerant Reconfigurable Architecture . . . . . . . .
3.5 Simulation and Design Techniques for Computer Systems
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electromagnetic Noises . . . . . . . . . . . . . . . . . . . . . . . . . .
Makoto Nagata, Nobuyuki Yamasaki, Yusuke Kumura,
Shuma Hagiwara and Masayuki Inaba
4.1 Electromagnetic Compatibility of CMOS ICs . . . . . .
4.2 Electromagnetic Noise Immunity in Memory Circuits
4.3 Power Noise of IC Chips in Assembly
and Its Mitigations . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Responsive Link for Noise-Tolerant Real-Time
Communications . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Variations in Device Characteristics . . . . . . . . . . . . . . . . . . .
Hidetoshi Onodera, Yukiya Miura, Yasuo Sato, Seiji Kajihara,
Toshinori Sato, Ken Yano, Yuji Kunitake and Koji Nii
5.1 Overview of Device Variations . . . . . . . . . . . . . . . . . . .
5.2 Monitoring and Compensation for Variations in Device
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Highly Accurate On-chip Measurement of Circuit Delay
Time for Dependable VLSI Systems . . . . . . . . . . . . . . .
5.4 Timing-Error-Sensitive Flip-Flop for Error Prediction . . .
5.5 Fine-Grain Assist Bias Control for Dependable SRAM . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Contents

6

7

Time-Dependent Degradation in Device Characteristics
and Countermeasures by Design . . . . . . . . . . . . . . . . . . . . . . . . .
Takashi Sato, Masanori Hashimoto, Shuhei Tanakamaru,
Ken Takeuchi, Yasuo Sato, Seiji Kajihara, Masahiko Yoshimoto,

Jinwook Jung, Yuta Kimi, Hiroshi Kawaguchi, Hajime Shimada
and Jun Yao
6.1 Time-Dependent Device Degradation; Mechanisms
and Mitigation Measures . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Degradation of Flash Memories and Signal Processing
for Dependability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 In-Field Monitoring of Device Degradation for Predictive
Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 A Reconfigurable SRAM Cache Design for Wide-Range
Reliable Low-Voltage Operation . . . . . . . . . . . . . . . . . . . . .
6.5 Runtime Self-reconstruction for Tolerating Software/Hardware
Faults Increment from Aging . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity in Wireless Telecommunications . . . . . . . . . . . . . . .
Kazuo Tsubouchi, Fumiyuki Adachi, Suguru Kameda,
Mizuki Motoyoshi, Akinori Taira, Noriharu Suematsu,
Tadashi Takagi, Hiroshi Oguma, Minoru Fujishima, Ryuji Inagaki,
Masaomi Tsuru, Eiji Taniguchi, Hiroshi Fukumoto,
Akira Matsuzawa, Masaya Miyahara, Makoto Iwata,
Fumihiro Yamagata and Noboru Izuka
7.1 Evolution of Public Wireless Networks
and Future Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Challenges for Dependable Wireless System . . . . . . . . . . . . .
7.3 Transceiver Technologies for Dependable Wireless System . .
7.4 Broadband RF Circuit for Versatile, Dependable Wireless
Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 All-Si-CMOS Front-End ICs for Multiband
Micro-/Millimeter-Wave Communications . . . . . . . . . . . . . .
7.6 Analog-to-Digital Converters for Versatile and Multiband
Wireless Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7 Multimode Frequency Domain Equalizer for Heterogeneous
Wireless Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8 Network Technology for Heterogeneous Wireless Systems . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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xii

8

9

Contents

Connectivity in Electronic Packaging . . . . . . . . . . . . . . . .
Hiroki Ishikuro, Tadahiro Kuroda, Atsutake Kosuge,
Mitsumasa Koyanagi, Kang Wook Lee, Hiroyuki Hashimoto
and Makoto Motoyoshi
8.1 Requirements for Dependable Electronic Packaging . .
8.2 Wireless Interconnect for Dependable Electronic
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Connectivity Issues in 3D Integration . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Responsiveness and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tomohiro Yoneda, Yoshihiro Nakabo, Nobuyuki Yamasaki,
Masayoshi Takasu, Masashi Imai, Suguru Kameda, Hiroshi Oguma,
Akinori Taira, Noriharu Suematsu, Tadashi Takagi
and Kazuo Tsubouchi
9.1 Responsiveness for Hard Real-Time Control . . . . . . . . . . . . .
9.2 Microprocessor Architecture for Real-Time Processing . . . . .

9.3 Asynchronous Networks-on-Chip . . . . . . . . . . . . . . . . . . . . .
9.4 Timing and Synchronicity for Dependable Wireless
Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 Malicious Attacks on Electronic Systems
and VLSIs for Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Takeshi Fujino, Daisuke Suzuki, Yohei Hori, Mitsuru Shiozaki,
Masaya Yoshikawa, Toshiya Asai and Masayoshi Yoshimura
10.1 The Role of Security LSI and the Example of Malicious
Attacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2 Methods for Tampering Cryptographic VLSIs . . . . . . . .
10.3 Tamper-Resistant Symmetric-Key Cryptographic Circuits
10.4 Verification Method for Tamper-Resistant VLSI Design .
10.5 A Method for Evaluating Vulnerability
to Scan-Based Attacks . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6 Evaluation of Tamper Resistance of VLSIs . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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11 Test Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Masahiro Fujita, Koichiro Takayama, Takeshi Matsumoto,
Kosuke Oshima, Satoshi Jo, Michiko Inoue, Tomokazu Yoneda
and Yuta Yamato
11.1 Verification and Test Coverage . . . . . . . . . . . . . . . . . . . . . . . . 440
11.2 Design Errors and Formal Verification . . . . . . . . . . . . . . . . . . . 444


Contents

xiii

11.3 High-Quality Delay Testing for In-field Self-test . . . . . . . . . . . . 461
11.4 Temperature-and-Voltage-Variation-Aware Test . . . . . . . . . . . . 466
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
12 Unknown Threats and Provisions . . . . . . . . . . . . . . . . . . . . . .
Nobuyasu Kanekawa, Takashi Miyoshi, Masahiro Fujita,
Takeshi Matsumoto, Hiroaki Yoshida, Satoshi Jo, Seiji Kajihara,
Satoshi Ohtake, Masashi Imai, Tomohiro Yoneda,
Hiroyuki Takizawa, Ye Gao, Masayuki Sato, Ryusuke Egawa
and Hiroaki Kobayashi
12.1 A Historical Review of Faults and Unidentified Future
Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 Challenges to Dependability at Data Centers . . . . . . . . . .
12.3 Post-silicon Validation and Patchable Hardware for
Rectification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4 Logging and Using Field Test Data for Improved

Dependability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5 Fault Detection and Reconfiguration in NoC-Coupled
Multiple-CPU Cores for Deadline-Specified Periodical
Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6 Checkpoint-Restart for Heterogeneous Multiple-Processor
Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Part III

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Design and Test of VLSI for Systems Dependability

13 Design Automation for Reliability . . . . . . . . . . . .
Hiroto Yasuura
13.1 Design Automation Tools and Dependability
13.2 Analysis Tools for Soft Errors . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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14 Formal Verification and Debugging of VLSI Logic Design
for Systems Dependability: Experiments and Evaluation . . . . .
Masahiro Fujita, Takeshi Matsumoto, Amir Masoud Gharehbaghi,
Kosuke Oshima, Satoshi Jo, Hiroaki Yoshida, Takashi Takenaka
and Kazutoshi Wakabayashi
14.1 Goal of Logic Verification and Necessity
of Formal Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2 Formal Equivalence Checking Under C-Based Design . . . .
14.3 Logic Debugging with Formal Analysis . . . . . . . . . . . . . . .
14.4 Conclusion and Future Perspectives . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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xiv

Contents

15 Virtualization: System-Level Fault Simulation of SRAM
Errors in Automotive Electronic Control Systems . . . . . . . . . . .
Shigeru Oho, Yasuhiro Ito, Yasuo Sugure, Yohei Nakata,
Hiroshi Kawaguchi and Masahiko Yoshimoto
15.1 Automotive Control Systems and Model-Based
Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.2 Virtual ECU and Its Applications . . . . . . . . . . . . . . . . . . . .
15.3 Dependable SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.4 Multilayer Modeling of Dependable SRAM and Automotive
Control Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.5 Large-Scale Fault Injection Testing with Cloud Computing . .
15.6 Future Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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.

16 DART—A Concept of In-field Testing for Enhancing System
Dependability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Kazumi Hatayama, Seiji Kajihara, Tomokazu Yoneda, Yuta Yamato,
Michiko Inoue, Yasuo Sato, Yukiya Miura and Satoshi Ohtake
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.2 Outline of DART Technology . . . . . . . . . . . . . . . . . . . . . . . .
16.3 Outlines of DART Elemental Technologies . . . . . . . . . . . . . .
16.4 Implementation of DART Technology . . . . . . . . . . . . . . . . . .
16.5 Other Activities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17 Design of SRAM Resilient Against Dynamic Voltage
Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Masahiko Yoshimoto, Yohei Nakata, Yuta Kimi, Hiroshi Kawaguchi,
Makoto Nagata and Koji Nii
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2 Resilient Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18 Design and Applications of Dependable Nonvolatile Memory
Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shuhei Tanakamaru and Ken Takeuchi
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3 Reliability Improvement Techniques . . . . . . . . . . . . . . . .
18.4 Summary and Conclusion . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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544
547
549
550

. 553

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554

556
564
567
574
575
576

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580
580
586
590
590

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594
594
596
604
605


Contents

xv

19 Network-on-Chip Based Multiple-Core Centralized ECUs for
Safety-Critical Automotive Applications . . . . . . . . . . . . . . . . . .
Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Akira Mochizuki,

Takahiro Hanyu, Kenji Kise and Yuichi Nakamura
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.2 Asynchronous On-chip and Inter-chip Network . . . . . . . . .
19.3 Dependable Routing Algorithm . . . . . . . . . . . . . . . . . . . . .
19.4 Dependable Task Execution . . . . . . . . . . . . . . . . . . . . . . . .
19.5 Evaluation Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

.
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20 An On-chip Router Architecture for Dependable Multicore
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Kenji Kise
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.2 SmartCore System . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.3 NoC Multifunction Router for SmartCore System . . . . .
20.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

.
.
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.

.

21 Wireless Interconnect in Electronic Systems
Tadahiro Kuroda and Atsutake Kosuge
21.1 Introduction . . . . . . . . . . . . . . . . . . . .
21.2 Wireless Interconnection . . . . . . . . . . .
21.3 Transmission Line Couplers . . . . . . . .
21.4 Conclusion . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 607

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608
610

617
626
629
632
632

. . . . . . 635
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635
636
640
642
643

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22 Wireless Power Delivery Resilient Against Loading Variations .
Hiroki Ishikuro
22.1 Applications and Issues of Wireless Power
Delivery Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.2 Wireless Power Delivery by Inductive Coupling . . . . . . . . .
22.3 Approach for Power Efficiency Improvement and Size
Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.4 Fast Load Tracking and EMI Reduction Technique . . . . . .
22.5 Wireless Power Delivery System Implementation . . . . . . . .
22.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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646
646
648
655
656

. . . 659

. . . 660
. . . 662
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663
664
667
670
673
674


xvi

Contents

23 Extended Dependable Air: Use of Satellites in Boosting
Dependability of Public Wireless Communications . . . . . . . . . . .

Kazuo Tsubouchi, Suguru Kameda, Hiroshi Oguma, Akinori Taira,
Noriharu Suematsu and Tadashi Takagi
23.1 3S Network: For Space, Surface, and Sea . . . . . . . . . . . . . .
23.2 SS-CDMA: A Proposal for Disaster Message Exchange . . . .
23.3 Heterogeneous Wireless System with Network Selection
Scheme Using Positioning Information . . . . . . . . . . . . . . . . .
23.4 Readiness of Required Technologies . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 687
. . 690
. . 691

24 Responsive Multithreaded Processor for Hard Real-Time
Robotic Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nobuyuki Yamasaki, Hiroyuki Chishiro, Keigo Mizotani
and Kikuo Wada
24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24.2 Responsive Multithreaded Processor (RMTP) . . . . . . .
24.3 Co-design of SoC and SiP . . . . . . . . . . . . . . . . . . . . .
24.4 Real-Time Operating Systems . . . . . . . . . . . . . . . . . .
24.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

.
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. . 675

. . 676
. . 678

. . . . . . . 693

.
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25 A Low-Latency DMR Architecture with Fast Checkpoint
Recovery Scheme Using Simultaneously Copyable SRAM
Masahiko Yoshimoto, Go Matsukawa, Yohei Nakata,
Hiroshi Kawaguchi, Yasuo Sugure and Shigeru Oho
25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25.2 Proposed DMR Architecture with a Recovery Scheme
25.3 Instantaneous Comparison and Simultaneous Copy . . .
25.4 Evaluation Results . . . . . . . . . . . . . . . . . . . . . . . . . .
25.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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.
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26 A 3D-VLSI Architecture for Future Automotive Visual
Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mitsumasa Koyanagi, Hiroaki Kobayashi, Takafumi Aoki,
Toshinori Sueyoshi and Tadashi Kamada
26.1 3D-VLSI Image Sensor System for Automatic
Driving Vehicle . . . . . . . . . . . . . . . . . . . . . . . . . .
26.2 3D-Stacked Image Sensor for Stereo Vision . . . . . .
26.3 3D-Stacked Dependable Multicore Processor . . . . .
26.4 Conclusions and Future Work . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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693
695
699
701
705

706

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709
710
713
715
717
718

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720
723
727
730
732


Contents

27 Applications of Reconfigurable Processors as Embedded
Automatons in the IoT Sensor Networks in Space . . . . . . . . . . .
Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi,
Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara,
Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka,
Hiromitsu Hada and Munehiro Tada
27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.2 Intelligent Sensors for IoT Applications—Target

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.3 Choosing Proper Processor Architecture for
IoT Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27.4 The FRRA Implementation of Embedded Automatons . . . . .
27.5 An Example Implementation and Result . . . . . . . . . . . . . . . .
27.6 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28 An FPGA Implementation of Comprehensive Security Functions
for Systems-Level Authentication . . . . . . . . . . . . . . . . . . . . . . . .
Daisuke Suzuki, Koichi Shimizu and Takeshi Fujino
28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.2 Overview of Glitch PUFs . . . . . . . . . . . . . . . . . . . . . . . . . .
28.3 Physical Random Number Generator . . . . . . . . . . . . . . . . . .
28.4 Unified Security Coprocessor . . . . . . . . . . . . . . . . . . . . . . . .
28.5 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29 SRAM-Based Physical Unclonable Functions (PUFs) to Generate
Signature Out of Silicon for Authentication and Encryption . . .
Koji Nii
29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29.2 A Unique Chip-ID Generation Scheme Using SRAM-Based
PUF with Random Fail-Bit Addresses . . . . . . . . . . . . . . . . .
29.3 Assessing Uniqueness and Reliability of SRAM-Based PUFs
from Silicon Measurements . . . . . . . . . . . . . . . . . . . . . . . . .
29.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xvii

. . 735

. . 736
. . 737
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741
743
745
747
749

. . 751
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751
752
753
756
762
771
772

. . 775
. . 775
. . 777
. . 782
. . 791
. . 791

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793


Part I

Introduction

Chapter 1

Challenges and Opportunities in VLSI
for Systems Dependability
Shojiro Asai

Abstract This chapter describes the scope, activities, and results of a research
program entitled, “Fundamental Technologies for Dependable VLSI Systems
(DVLSI for short henceforth)” which began in 2007 and ended in 2015. The
program, funded by JST (Japan Science and Technology Agency) under the
CREST (Core Research of Evolutional Science and Technology) initiative, consisted of 11 projects and addressed problems in dependability of electronic systems
from various different angles. VLSI is a complex system in its own right and
involves a number of potential hazards that arise internally from aging in elements
or those that can be caused by external disturbances such as ionizing radiations.
Coping with these phenomena has always been a challenge in semiconductor
engineering and this program as well. Fabrics (physical structures) robust against
threats, bit-error correction methods, and logic-level redundancies have been
extensively studied. To go further, challenges of 3-D integration, chip-area (on-chip
and across-chip) network, and wireless packaging have been taken on. Exploiting
the potential of VLSI in solving problems in systems that call for hard real-time
response and/or synchronicity as in robotics and wireless telecommunications has
been addressed as new great opportunities for VLSIs. Advanced ways of verification and test for VLSIs have also been dealt with. We will begin this chapter by
going over the background of VLSIs for electronic systems and reviewing the
necessity of dependability. We will then describe how this multi-project program of
CREST DVLSI was formed and conducted. The university-industry collaboration
in goal-oriented management efforts is highlighted as essential. A summary of
results obtained follows.

⋅

⋅

Keywords Dependable system
VLSI
CREST
collaboration
Goal-oriented management

⋅

⋅

University-industry

S. Asai (✉)
Rigaku Corporation, Tokyo, Japan
e-mail:
© Springer Japan KK, part of Springer Nature 2019
S. Asai (ed.), VLSI Design and Test for Systems Dependability,
/>
3


4

S. Asai

1.1

VLSI in Electronic Systems and Their Dependability

1.1.1

Pervasiveness of VLSI

The VLSI (Very Large Scale Integration of semiconductor circuits) and software
(computer program) are two great enablers of electronic systems, a synonym to
modern-day convenience. Personal computers and cell phones, almost indispensable personal items these days, are good examples. Figure 1.1 shows a simplified
block diagram of a personal computer. It is seen that VLSI chips such as a
microprocessor [1–3], and semiconductor memories [4], e.g., RAM (Random
Access Memory) and NVM (Nonvolatile Memory), are the most important parts
among others. Important peripheral devices such as HDD (Hard Disk Drive),
communications control, and monitoring display have built-in processors as well.
The PC (Personal Computer) is a typical general-purpose computer where users run
various different application programs. High-performance (Super-) computers are at
the highest end of general-purpose computers.
Figure 1.2 depicts the power train (power generation and transmission) in a
hybrid electric-gasoline-engine vehicle which uses a number of ECUs (electronic
control units). Each ECU has at least one microprocessor “embedded” and is thus
an electronic system in its own right. The automobile these days is a typical
embodiment of embedded computing [5]. A high-end car these days uses as many

Purpose
Outputs

Multiple purposes:
Text editing
Video/Audio

Spreadsheet
Data analysis
Simulation
Emailing
Social networking
Internet trading

Software
Application Software

Processor

Compiler

RAM

Assembler

NVM

Peripheral devices
WiFi
base station

Printer
Middleware

Auxiliary storage
SSD or HDD
Communication

control

Operating System
Firmware
Device Driver

Inputs

Hardware

Video screen
Audio interfaces
Keyboard/Touchpad

PC Personal Computer

Backup storage

Legend:
VLSI
VLSI-embedded
sub-system
Software

Fig. 1.1 A simplified block diagram of a PC (Personal Computer) to illustrate the use of VLSIs as
key components


1 Challenges and Opportunities in VLSI for Systems Dependability

motor, generator
drive request torque

Shift lever position

rpm, current

Acceleration pedal

Regenerative
Brake ECU

5

regenerative
brake request
value

SOC,current
voltage

rpm

electric
motor

Inverter
(Motor)

voltage

Hybrid ECU

regenerative
brake effective
value

generator

Inverter
(Generator)
Motor
ECU

Main power
supply relay

engine output
request value

Engine ECU

gasoline engine
power split
device

Battery ECU

Battery

electrical power path
wheel

mechanical power path

Fig. 1.2 Electronic control units in the power train of a hybrid electric and gasoline-engine
vehicle to illustrate use of VLSI-powered ECUs (Electronic Control Units). Courtesy, Toyota
Motor Corporation

as 80 microprocessors for various subsystem and module-level control [6]. Actually,
the VLSI has provided the biggest momentum to improve the quality and reduce the
cost of products or services of electronic systems. This is true with most of complex
systems products, which may be mechanical (stationary or mobile), aerodynamic,
electrical, electromechanical, electromagnetic, optical, electro-optical, or chemical.
Because these systems generally need control for precision and throughput, which is
hard to achieve were it not for the VLSI and program control. Automobiles, aircrafts,
rockets, robots, chemical plants, utilities, medical devices, ATMs (Automatic Teller
Machines), data storages, and agricultural plants of today are good examples of
computer-embedded systems. They would not have existed without the VLSI as their
key components for smart control. It is almost funny that we are accustomed to call
these computer-embedded electronic systems “dedicated systems.” Although the
purpose of the system is certainly “dedicated”, for example, to automotive control,
computers (microprocessors) have actually found far more general and voluminous
applications in embedded control than in “general-purpose” computing by PCs and
HPCs (High-Performance Computers).
The more the benefits are drawn out of these systems and the more extensive
their uses become over the population, the more heavily the human life depends on
them. It is necessary therefore to see to it that these systems are available whenever
they are needed. Because the VLSI is at the core of these systems as the workhorse,
it is necessary to understand what the VLSI does in electronic systems, what would

6

S. Asai

happen if it fails to function as expected, what could be done to prevent serious
failures from happening, and what we can innovate further in realizing more
dependable systems technologies. Actually, these are the subjects discussed in this
book. (Let us call the systems that use VLSIs as key components “electronic
systems” hereafter. The term VLSI systems may be used interchangeably.)

1.1.2

Necessity of Dependability

Dependability is never a single quality merit of a system. Central to the merit is
rather the “performance” or “performance/cost,” in other words, “better fulfillment
of the primary purpose” it is intended for. Table 1.1 shows the factors that would
affect the decision a user would make in the procurement of a product or service
offered in the marketplace. During early stages of market introduction, cost and or
performance may be the most influential factors, but as a product category and its
market mature, increased attention is paid to dependability for increased social and
economic implications, and this is true now with all kinds of electronic systems.
These days, dependability of an electronic system is an interest shared among all
those concerned: producers, users, and service providers alike.
The requirements for dependability have been discussed in and among various
government regulatory agencies, global/regional/national standards bodies,
mission-oriented agencies, industrial associations, and academic societies. Figure 1.3
shows such organizations along with the documents they have published. It will be

Table 1.1 Factors affecting the decision-making for procurement of a product or service


1 Challenges and Opportunities in VLSI for Systems Dependability
Legislature

CE marking
Low-voltage directive, EMC
directive, Machine directive
Conformity required
for certain product categories

Government Body

US DoD
MIL-STD-882E system safety

Regulatory Agencies

US FDA
21 CFR Part 11 electronic records
US FAA
14 CFR Part 25 airworthiness

Academic/Engineering Societies
IEEE
TCFT fault tolerance,
IFIP
WG10.4 dependable computing
SAE

ARP4761 safety assessment
process for civil airborne systems

Component Industry Associations

JEDEC, JEITA
Semiconductor test methods

7
Standard Bodies

IEC
IEC 60300 dependability management
IEC 60812 analysis for system reliability
IEC 61508 functional safety
ISO
ISO 9000 management quality
ISO 26262 road vehicle functional safety

Special Mission Entities

NASA, ESA, JAXA
Spacecraft safety requirements,
standards

Systems Industry Associations

Automotive Electronic Council:
AEC Q-100, Q-101, Q-200, etc.,

Fig. 1.3 Organizations engaged in regulations, standards, and guidelines for dependability as part
of product quality

relevant to refer in particular to IEC 60300 [7] for dependability management, IEC
61508 [8] for functional safety in industrial process measurement, control and
automation, and ISO 26262 [9] for the functional safety for road vehicles, since these
will be frequently cited throughout this book.

1.2
1.2.1

Background and Motivation for the Program
What VLSI Has Brought About—A Historical
Perspective

The VLSI has contributed to the progress in electronic systems in so many ways,
which may be summarized as follows.
#1 Great number of devices integrated on a chip
As first observed by Gordon Moore and later named as Moore’s Law that has held
up until very recently, the number of transistors integrated on a chip of VLSI silicon
has doubled every 18 months [10]. It is interesting to review the progress that the
VLSI made following what Gordon Moore predicted [11]. I will not go into that
here, however, since there already are abundant references available for this history


8

S. Asai

[12]. It is worthwhile to note here, however, that there is a very solid theoretical

background to the scaling down the sizes (other physical parameters and operating
voltages as well) of the transistor, the most basic element of VLSI that has underlain
its progress [13]. The number of transistors in a microprocessor has actually
increased from the mere 2300 of Intel 4004 in 1971 to the billions today [14]. The
same is true with memory chips. In no other technologies has it ever been possible
to integrate uniformly performing, reliable components the way VLSI has enabled,
which has provided the most powerful driving force for the complex electronic
systems [15].
#2 Variety of circuit functions realized on silicon
The VLSI rapidly evolved from the early days of chips with a few logic gates into a
variety of circuit functions covering arithmetic, logic, memory, analog, and more.
Memories include SRAM (Static Random Access Memory), DRAM (Dynamic
Random Access Memory), ROM (Read-Only Memory), EPROM (Electrically
Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM),
and Flash Memory [4]. The analog and analog–digital tier of the silicon circuitry is
capable of small-signal and high-power amplification, and analog-to-digital and
digital-to-analog conversion [16]. A very important type of products of VLSI called
FPGA (Field Programmable Gate Array) emerged during the course of the development [17, 18]. Image sensors with billions of pixels have been used in cameras
[19]. Micro-Electro-Mechanical (MEMS) is another direction the VLSI has taken to
develop [20].
#3 Single-chip implementation of multiple circuit functions
Almost all the circuit functions described in #2 have actually been integrated in
chips by now in the form of microprocessors used for personal computers, mobile
communication devices, and computer-embedded electric, electronic, and
software-controlled systems. The CMOS (Complementary Metal-Oxide Semiconductor), which emerged originally as low-power but low-speed integrated circuit
technology, has since been exploited fully to realize all of the logic, memory, and
coupled analog–digital functions, taking over the roles played by ECL, TTL and
NMOS, and Bi-CMOS (hybrid bipolar and CMOS), realizing the highest density of
integration by virtue of low power (virtually no power consumption when idle)
inherent in that technology. This history is very well captured in Table 1.2 compiled by Makimoto et al. [21].

#4 Application functions and accelerated processing
During the course of evolution in VLSI, what is now called the ASIC
(Application-Specific Integrated Circuit) [22] has evolved. The ASIC contrasts to
general-purpose integrated circuits such as standard memories and microprocessors.
ASICs with specific system- or subsystem-level functions have often been developed in-house at a systems house, or at a semiconductor house to the order of a
systems house, for signal processing in telecom, image-processing applications (routers and switches, data compression, data correction, display control), for example.


1 Challenges and Opportunities in VLSI for Systems Dependability

9

Table 1.2 Evolution of CMOS to encompass broader applications over time. CMOS has
gradually outperformed other circuit technologies and enabled the integration of various different
circuit functions on a single chip of VLSI [21]

Some of these application functions that were originally developed for ASICS such
as efficient display control, encryption, and decryption for secure data transmission
have been integrated in a general-purpose microprocessor. There are other types of
VLSIs that evolved into high-performance, dedicated computation to complement
microprocessors. In this category are DSP (Digital Signal Processor) [23] and GPU
(Graphic Processing Unit) [24].
#5 Abundance of on-chip resource
The availability of an abundance of circuit resource has been exploited to introduce
fault tolerance to the VLSI. The use of redundant bits for error correction was first
used in DRAMs and SRAMs, easily accommodating a few defective bits to the
effect of salvaging partially defective chips and thus drastically lowering the
average memory prices. The introduction of error correction dramatically improved
the tolerance of semiconductor memories against radiation-induced soft errors.
(Please refer to paragraphs below). The fault-tolerant technology is used in flash

memories in a more sophisticated fashion to optimize the memory retention and
write–erase endurance. Error-correcting codes and encoding techniques are used to
avoid physical interference of charges in the neighboring cells [25, 26]. Recent
multiple-processor chips as well as FPGAs are capable of performing redundant
concurrent calculation and then having a vote for the correct result to be robust
against faults in a part of the chip. Two of most advanced VLSI architectures are
shown in Figs. 1.4 and 1.5 for illustrative purposes. Figure 1.4 shows a powerful
integration of a multi-core processor and an FPGA which includes security features
such as AES (Advanced Encryption Standard), SHA (Secure Hash Algorithm), and
RSA (Rivest–Shamir–Aldeman encryption) [27]. Figure 1.5 is a microprocessor for
automotive applications. Security features to support ISO 26262 have been integrated [28].