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1

Solutions

Solution 1.1
1.1.1 Computer used to run large problems and usually accessed via a network:
(3) servers
1.1.2 1015 or 250 bytes: (7) petabyte
1.1.3 A class of computers composed of hundred to thousand processors and terabytes of memory and having the highest performance and cost: (5) supercomputers
1.1.4 Today’s science fiction application that probably will be available in near
future: (1) virtual worlds
1.1.5 A kind of memory called random access memory: (12) RAM
1.1.6 Part of a computer called central processor unit: (13) CPU
1.1.7 Thousands of processors forming a large cluster: (8) data centers
1.1.8 Microprocessors containing several processors in the same chip: (10) multicore processors
1.1.9 Desktop computer without a screen or keyboard usually accessed via a network: (4) low-end servers
1.1.10 A computer used to running one predetermined application or collection
of software: (9) embedded computers
1.1.11 Special language used to describe hardware components: (11) VHDL
1.1.12 Personal computer delivering good performance to single users at low cost:
(2) desktop computers
1.1.13 Program that translates statements in high-level language to assembly
language: (15) compiler

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S2

Chapter 1

Solutions

1.1.14 Program that translates symbolic instructions to binary instructions:
(21) assembler
1.1.15 High-level language for business data processing: (25) Cobol
1.1.16 Binary language that the processor can understand: (19) machine language
1.1.17 Commands that the processors understand: (17) instruction
1.1.18 High-level language for scientific computation: (26) Fortran
1.1.19 Symbolic representation of machine instructions: (18) assembly language
1.1.20 Interface between user’s program and hardware providing a variety of
services and supervision functions: (14) operating system
1.1.21 Software/programs developed by the users: (24) application software
1.1.22 Binary digit (value 0 or 1): (16) bit
1.1.23 Software layer between the application software and the hardware that
includes the operating system and the compilers: (23) system software
1.1.24 High-level language used to write application and system software: (20) C
1.1.25 Portable language composed of words and algebraic expressions that must
be translated into assembly language before run in a computer: (22) high-level
language
1.1.26 1012 or 240 bytes: (6) terabyte

Solution 1.2
1.2.1 8 bits × 3 colors = 24 bits/pixel = 3 bytes/pixel.
AQ 1

a.

Configuration 1: 640 × 480 pixels = 179,200 pixels => 179,200 × 3 = 537,600 bytes/frame
Configuration 2: 1280 × 1024 pixels = 1,310,720 pixels => 1,310,720 × 3 = 3,932,160
bytes/frame

b.

Configuration 1: 1024 × 768 pixels = 786,432 pixels => 786,432 × 3 = 2,359,296
bytes/frame
Configuration 2: 2560 × 1600 pixels = 4,096,000 pixels => 4,096,000 × 3 = 12,288,000
bytes/frame

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Chapter 1

Solutions

S3

1.2.2 No. frames = integer part of (Capacity of main memory/bytes per frame)
a.

Configuration 1: Main memory: 2 GB = 2000 Mbytes. Frame: 537.600 Mbytes => No. frames = 3
Configuration 2: Main memory: 4 GB = 4000 Mbytes. Frame: 3,932.160 Mbytes => No. frames = 1

b.

Configuration 1: Main memory: 2 GB = 2000 Mbytes. Frame: 2,359.296 Mbytes => No. frames = 0
Configuration 2: Main memory: 4 GB = 4000 Mbytes. Frame: 12,288 Mbytes => No. frames = 0

1.2.3 File size: 256 Kbytes = 0.256 Mbytes.
Same solution for a) and b)
Configuration 1: Network speed: 100 Mbit/sec = 12.5 Mbytes/sec. Time = 0.256/12.5 = 20.48 ms
Configuration 2: Network speed: 1 Gbit/sec = 125 Mbytes/sec. Time = 0.256/125 = 2.048 ms

1.2.4
a.

2 microseconds from cache ⇒ 20 microseconds from DRAM.

b.

2 microseconds from cache ⇒ 20 microseconds from DRAM.

AQ 2

1.2.5
a.

2 microseconds from cache ⇒ 2 ms from Flash memory.

b.

2 microseconds from cache ⇒ 4.28 ms from Flash memory.

1.2.5

a.

2 microseconds from cache ⇒ 2 s from magnetic disk.

b.

2 microseconds from cache ⇒ 5.7 s from magnetic disk.

Solution 1.3
1.3.1 P2 has the highest performance.
Instr/sec = f/CPI
a.

performance of P1 (instructions/sec) = 3 × 109/1.5 = 2 × 109
performance of P2 (instructions/sec) = 2.5 × 109/1.0 = 2.5 × 109
performance of P3 (instructions/sec) = 4 × 109/2.2 = 1.8 × 109

b.

performance of P1 (instructions/sec) = 2 × 109/1.2 = 1.66 × 109
performance of P2 (instructions/sec) = 3 × 109/0.8 = 3.75 × 109
performance of P3 (instructions/sec) = 4 × 109/2 = 2 × 109

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S4

Chapter 1

Solutions

1.3.2 No. cycles = time × clock rate
time = (No. Instr × CPI)/clock rate, then No. instructions = No. cycles/CPI
a.

cycles(P1) = 10 × 3 × 109 = 30 × 109 s
cycles(P2) = 10 × 2.5 × 109 = 25 × 109 s
cycles(P3) = 10 × 4 × 109 = 40 × 109 s
No. instructions(P1) = 30 × 109/1.5 = 20 × 109
No. instructions(P2) = 25 × 109/1 = 25 × 109
No. instructions(P3) = 40 × 109/2.2 = 18.18 × 109

b.

cycles(P1) = 10 × 2 × 109 = 20 × 109 s
cycles(P2) = 10 × 3 × 109 = 30 × 109 s
cycles(P3) = 10 × 4 × 109 = 40 × 109 s
No. instructions(P1) = 20 × 109/1.2 = 16.66 × 109
No. instructions(P2) = 30 × 109/0.8 = 37.5 × 109
No. instructions(P3) = 40 × 109/2 = 20 × 109

1.3.3 timenew = timeold × 0.7 = 7 s
a.

CPInew = CPIold × 1.2, then CPI(P1) = 1.8, CPI(P2) = 1.2, CPI(P3) = 2.6
f = No. Instr × CPI/time, then

AQ 3

f(P1) = 20 × 109 × 1.8 / 7 = 5.14 GHz
f(P2) = 25 × 109 × 1.2 / 7 = 4.28 GHz
f(P1) = 18.18 × 109 × 2.6 / 7 = 6.75 GHz
b.

CPInew = CPIold × 1.2, then CPI(P1) = 1.44, CPI(P2) = 0.96, CPI(P3) = 2.4
f = No. Instr × CPI/time, then
f(P1) = 16.66 × 109 × 1.44/7 = 3.42 GHz
f(P2) = 37.5 × 109 × 0.96/7 = 5.14 GHz
f(P1) = 20 × 109 × 2.4/7 = 6.85 GHz

1.3.4 IPC = 1/CPI = No. instr/(time × clock rate)
a.

IPC(P1) = 0.95
IPC(P2) = 1.2
IPC(P3) = 2.5

b.

IPC(P1) = 2
IPC(P2) = 1.25
IPC(P3) = 0.89

1.3.5
a.

Timenew/Timeold = 7/10 = 0.7. So fnew = fold/0.7 = 2.5 GHz/0.7 = 3.57 GHz.

b.

Timenew/Timeold = 5/8 = 0.625. So fnew = fold/0.625 = 4.8 GHz.

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Chapter 1

Solutions

S5

1.3.6
a.

Timenew/Timeold = 9/10 = 0.9. Then Instructionsnew = Instructionsold × 0.9 = 30 × 109 × 0.9 = 27
× 109.

b.

Timenew/Timeold = 7/8 = 0.875. Then Instructionsnew = Instructionsold × 0.875 = 26.25 × 109.

Solution 1.4
1.4.1

Class A: 105 instr.
Class B: 2 × 105 instr.
Class C: 5 × 105 instr.
Class D: 2 × 105 instr.
Time = No. instr × CPI/clock rate
a.

Total time P1 = (105 + 2 × 105 × 2 + 5 × 105 × 3 + 2 × 105 × 3)/(2.5 × 109) = 10.4 × 10−4 s
Total time P2 = (105 × 2 + 2 × 105 × 2 + 5 × 105 × 2 + 2 × 105 × 2)/(3 × 109) = 6.66 × 10−4 s

b.

Total time P1 = (105 × 2 + 2 × 105 × 1.5 + 5 × 105 × 2 + 2 × 105)/(2.5 × 109) = 6.8 × 10−4 s
Total time P2 = (105 + 2 × 105 × 2 + 5 × 105 + 2 × 105)/(3 × 109) = 4 × 10−4 s

1.4.2 CPI = time × clock rate/No. instr
a.

CPI (P1) = 10.4 × 10−4 × 2.5 × 109/106 = 2.6
CPI (P2) = 6.66 × 10−4 × 3 × 109/106 = 2.0

b.

CPI (P1) = 6.8 × 10−4 × 2.5 × 109/106 = 1.7
CPI (P2) = 4 × 10−4 × 3 × 109/106 = 1.2

1.4.3
a.

clock cycles (P1) = 105 × 1 + 2 × 105 × 2 + 5 × 105 × 3 + 2 × 105 × 3 = 26 × 105

clock cycles (P2) = 105 × 2 + 2 × 105 × 2 + 5 × 105 × 2 + 2 × 105 × 2 = 20 × 105

b.

clock cycles (P1) = 17 × 105
clock cycles (P2) = 12 × 105

1.4.4
a.

(650 × 1 + 100 × 5 + 600 × 5 + 50 × 2) × 0.5 × 10–9 = 2,125 ns

b.

(750 × 1 + 250 × 5 + 500 × 5 + 500 × 2) × 0.5 × 10–9 = 2,750 ns

1.4.5 CPI = time × clock rate/No. instr
a.

CPI = 2,125 × 10–9 × 2 × 109/1,400 = 3.03

b.

CPI = 2,750 × 10–9 × 2 × 109/2,000 = 2.75

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S6

Chapter 1

Solutions

1.4.6
a.

Time = (650 × 1 + 100 × 5 + 300 × 5 + 50 × 2) × 0.5 × 10–9 = 1,375 ns
Speedup = 2,125 ns/1,375 ns = 1.54
CPI = 1,375 × 10–9 × 2 × 109/1,100 = 2.5

b.

Time = (750 × 1 + 250 × 5 + 250 × 5 + 500 × 2) × 0.5 × 10–9 = 2,125 ns
Speedup = 2,750 ns/2,125 ns = 1.29
CPI = 2,125 × 10–9 × 2 × 109/1,750 = 2.43

Solution 1.5
1.5.1
a.

P1: 2 × 109 inst/sec, P2: 2 × 109 inst/sec

b.

P1: 2 × 109 inst/sec, P2: 3 × 109 inst/sec

1.5.2
a.

T(P2)/T(P1) = 4/7;

b.

T(P2)/T(P1 )= 4.66/5; P2 is 1.07 times faster than P1

P2 is 1.75 times faster than P1

1.5.3
a.

T(P2)/T(P1) = 4.5/8;

b.

T(P2)/T(P1) = 5.33/5.5; P2 is 1.03 times faster than P1

P2 is 1.77 times faster than P1

1.5.4
a.

2.91 µs

b.

2.50 µs

1.5.5
a.

0.78 µs

b.

0.90 µs

1.5.6
a.

T = 0.68µs => 1.14 times faster

b.

T = 0.75µs => 1.20 times faster

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Chapter 1

Solutions

S7

Solution 1.6
1.6.1 CPI = Texec × f/No. Instr
Compiler A CPI

Compiler B CPI

a.

1.8

1.5

b.

1.1

1.25

1.6.2 fA/fB = (No. Instr(A) ´ CPI(A))/(No. Instr(B) ´ CPI(B))
a.

fA/fB = 1

b.

fA/fB = 0.73

1.6.3
Speedup vs. Compiler A

Speedup vs. Compiler B

a.

Tnew/TA = 0.36

Tnew/TB = 0.36

b.

Tnew/TA = 0.6

Tnew/TB = 0.44

1.6.4
P1 Peak

P2 Peak

a.

4 × 109 Inst/s

2 × 109 Inst/s

b.

9

3 × 109 Inst/s

4 × 10 Inst/s

1.6.5 Speedup, P1 versus P2:
a.

T1/T2 = 1.9

b.

T1/T2 = 1.5

1.6.6
a.

4.37 GHz

b.

6 GHz

Solution 1.7
1.7.1
Geometric mean clock rate ratio = (1.28 × 1.56 × 2.64 × 3.03 × 10.00 × 1.80 ×
0.74)1/7 = 2.15
Geometric mean power ratio = (1.24 × 1.20 × 2.06 × 2.88 × 2.59 × 1.37 × 0.92)1/7 = 1.62

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S8

Chapter 1

Solutions

1.7.2
Largest clock rate ratio = 2000 MHz/200 MHz = 10 (Pentium Pro to Pentium 4
Willamette)
Largest power ratio = 29.1 W/10.1 W = 2.88 (Pentium to Pentium Pro)
1.7.3
Clock rate: 2.667 × 109/12.5 × 106 = 213.36
Power: 95 W/3.3 W = 28.78
1.7.4 C = P/V2 × clock rate
80286: C = 0.0105 × 10−6
80386: C = 0.01025 × 10−6
80486: C = 0.00784 × 10−6
Pentium: C = 0.00612 × 10−6
Pentium Pro: C = 0.0133 × 10−6
Pentium 4 Willamette: C = 0.0122 ×10−6
Pentium 4 Prescott: C = 0.00183 × 10−6
Core 2: C = 0.0294 ×10−6
1.7.5 3.3/1.75 = 1.78 (Pentium Pro to Pentium 4 Willamette)
1.7.6
Pentium to Pentium Pro: 3.3/5 = 0.66
Pentium Pro to Pentium 4 Willamette: 1.75/3.3 = 0.53

Pentium 4 Willamette to Pentium 4 Prescott: 1.25/1.75 = 0.71
Pentium 4 Prescott to Core 2: 1.1/1.25 = 0.88
Geometric mean = 0.68

Solution 1.8
1.8.1 Power = V2 × clock rate × C. Power2 = 0.9 Power1
a.

C2/C1 = 0.9 × 1.752 × 1.5 × 109/(1.22 × 2 × 109) = 1.43

b.

C2/C1 = 0.9 × 1.12 × 3 × 109/(0.82 × 4 × 109) = 1.27

1.8.2 Power2/Power1 = V22 × clock rate2/(V12 × clock rate1)
a.

Power2/Power1 = 0.62 => Reduction of 38%

b.

Power2/Power1 = 0.7 => Reduction of 30%

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Chapter 1

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S9

1.8.3
a.

Power2 = V22 × 2 × 109 × 0.8 × C1 = 0.6 × Power1
Power1 = 1.752 × 1.5 × 109 × C1
V22 × 2 × 109 × 0.8 × C1 = 0.6 × 1.752 × 1.5 × 109 × C1
V2 =((0.6 × 1.752 × 1.5)/(2 × 0.8))1/2 = 1.31 V

b.

Power2 = V22 × 4 × 109 × 0.8 × C1 = 0.6 × Power1
Power1 = 1.12 × 3 × 109 × C1
V22 × 4 × 109 × 0.8 × C1 = 0.6 × 1.12 × 3 × 109 × C1
V2 = ((0.6 × 1.12 × 3)/(4 × 0.8))1/2 = 0.825 V

1.8.4
a.

Powernew = 1 × Cold × V2old/(21/2)2 × clock rate × 1.15. Thus, Powernew = 0.575 Powerold

b.

Powernew = 1 × Cold × V2old/(21/4)2 × clock rate × 1.2. Thus, Powernew = 0.848 Powerold

1.8.5

a.

1/21/2 = 0.7

b.

1/21/4 = 0.8

1.8.6
a.

Voltage = 1.1 × 1/21/2 = 0.77 V.
Clock rate = 2.667 × 1.15 = 3.067 GHz.

b.

Voltage = 1.1 × 1/21/4 = 0.92 V.
Clock rate = 2.667 × 1.2 = 3.2 GHz.

Solution 1.9
1.9.1
a.

10/60 × 100 = 16.6%

b.

60/150 × 100 = 40%

1.9.2

Ptotal_new = 0.9 Ptotal_old
Pstatic_new/Pstatic_old = Vnew/Vold
a.

1.08 V

b.

0.81 V

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Chapter 1

Solutions

1.9.3
a.

Powerst/Powerdyn = 10/50 = 0.2

b.

Powerst/Powerdyn = 60/90 = 0.66

1.9.4 Powerst/Powerdyn = 0.6 => Powerst = 0.6 × Powerdyn
a.

Powerst = 0.6 × 35 W = 21 W

b.

Powerst = 0.6 × 30 W = 18 W

1.9.5
1.2 V

1.0 V

0.8 V

a.

Pst = 12.5 W
Pdyn = 62.5 W

Pst = 10 W
Pdyn = 50 W

Pst = 5.8 W
Pdyn = 29.2 W

b.

Pst = 24.8 W
Pdyn = 37.2 W

Pst = 20 W
Pdyn = 30 W

Pst = 12 W
Pdyn = 18 W

1.9.6
a.

29.15

b.

23.32

Solution 1.10
1.10.1
a.

b.

Processors

Instructions per Processor

Total Instructions

1

4096

4096

2

2048

4096

4

1024

4096

8

512

4096

Processors

Instructions per Processor

Total Instructions

1

4096

4096

2

2048

4096

4

1024

4096

8

512

4096

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Chapter 1

Solutions

S11

1.10.2
a.

b.

Processors

Execution Time (µs)

1

4.096

2

2.368

4

1.504

8

1.152

Processors

Execution Time (µs)

1

4.096

2

2.688

4

1.664

8

0.992

Processors

Execution Time (µs)

1

5.376

2

3.008

4

1.824

8

1.312

Processors

Execution Time (µs)

1

5.376

2

3.328

4

1.984

8

1.152

Cores

Execution Time (s) @ 3 GHz

1

4.00

2

2.33

4

1.50

8

1.08

Cores

Execution Time (s) @ 3 GHz

1

3.33

2

2.00

4

1.16

8

0.71

1.10.3
a.

b.

1.10.4
a.

b.

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S12

Chapter 1

Solutions

1.10.5
Cores

Power (W) per Core
@ 3 GHz

Power (W) per Core
@ 500 MHz

Power (W)
@ 3 GHz

Power (W)
@ 500 MHz

1

15

0.625

15

0.625

2

15

0.625

30

1.25

4

15

0.625

60

2.5

8

15

0.625

120

5

Cores

Power (W) per Core
@ 3 GHz

Power (W) per Core
@ 500 MHz

Power (W)
@ 3 GHz

Power (W)
@ 500 MHz

1

15

0.625

15

0.625

2

15

0.625

30

1.25

4

15

0.625

60

2.5

8

15

0.625

120

5

a.

b.

1.10.6
a.

AQ 4

b.

Processors

CPI for 1 Core

1

1.2

2

0.7

4

0.45

8

0.32

Processors

CPI for 1 Core

1

1

2

0.6

4

0.35

8

0.21

Solution 1.11
1.11.1 Wafer area = p × (d/2)2
a.

wafer area = π × 7.52 = 176.7 cm2

b.

wafer area = π × 102 = 314.2 cm2

Die area = wafer area/dies per wafer
a.

Die area = 176.7/84 = 2.10 cm2

b.

Die area = 314.2/100 = 3.14 cm2

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S13

Yield = 1/(1 + (defect per area × die area)/2)2
a.

Yield = 0.96

b.

Yield = 0.91

1.11.2 Cost per die = cost per wafer/(dies per wafer × yield)
a.

Cost per die = 0.15

b.

Cost per die = 0.16

1.11.3
a.

Dies per wafer = 1.1 × 84 = 92
Defects per area = 1.15 × 0.02 = 0.023 defects/cm2
Die area = wafer area/Dies per wafer = 176.7/92 = 1.92 cm2
Yield = 0.96

b.

Dies per wafer = 1.1 × 100 = 110
Defects per area = 1.15 × 0.031 = 0.036 defects/cm2
Die area = wafer area/Dies per wafer = 314.2/110 = 2.86 cm2
Yield = 0.90

1.11.4 Yield = 1/(1 + (defect per area × die area)/2)2
Then defect per area = (2/die area)(y−1/2 − 1)
Replacing values for T1 and T2 we get:
T1: defects per area = 0.00085 defects/mm2 = 0.085 defects/cm2
T2: defects per area = 0.00060 defects/mm2 = 0.060 defects/cm2
T3: defects per area = 0.00043 defects/mm2 = 0.043 defects/cm2
T4: defects per area = 0.00026 defects/mm2 = 0.026 defects/cm2
1.11.5 no solution provided

Solution 1.12
1.12.1 CPI = clock rate × CPU time/instr count
clock rate = 1/cycle time = 3 GHz
a.

CPI(bzip2) = 3 × 109 × 750/(2,389 × 109) = 0.94

b.

CPI(go) = 3 × 109 × 700/(1,658 × 109) = 1.26

1.12.2 SPECratio = ref. time/execution time
a.

SPECratio(bzip2) = 9,650/750 = 12.86

b.

SPECratio(go) = 10,490/700 = 14.98

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Chapter 1

Solutions

1.12.3
(12.86 × 14.98)1/2 = 13.88

1.12.4 CPU time = No. instr × CPI/clock rate
If CPI and clock rate do not change, the CPU time increase is equal to the increase
in the of number of instructions, that is, 10%.
1.12.5 CPU time(before) = No. instr × CPI/clock rate
CPU time(after) = 1.1 × No. instr × 1.05 × CPI/clock rate
CPU times(after)/CPU time(before) = 1.1 × 1.05 = 1.155 Thus, CPU time is
increased by 15.5%.
1.12.6 SPECratio = reference time/CPU time
SPECratio(after)/SPECratio(before) = CPU time(before)/CPU time(after) =
1/1.1555 = 0.86. Thus, the SPECratio is decreased by 14%.

Solution 1.13
1.13.1 CPI = (CPU time × clock rate)/No. instr
a.

CPI = 700 × 4 × 109/(0.85 × 2,389 × 109) = 1.37

b.

CPI = 620 × 4 × 109/(0.85 × 1,658 × 109) = 1.75

1.13.2 Clock rate ratio = 4 GHz/3 GHz = 1.33
a.

CPI @ 4 GHz = 1.37, CPI @ 3 GHz = 0.94, ratio = 1.45

b.

CPI @ 4 GHz = 1.75, CPI @ 3 GHz = 1.26, ratio = 1.38

They are different because although the number of instructions has been reduced
by 15%, the CPU time has been reduced by a lower percentage.
1.13.3
a.

700/750 = 0.933. CPU time reduction: 6.7%

b.

620/700 = 0.886. CPU time reduction: 11.4%

1.13.4 No. instr = CPU time × clock rate/CPI
a.

No. instr = 960 × 0.9 × 4 × 109/1.61 = 2,146 × 109

b.

No. instr = 690 × 0.9 × 4 × 109/1.79 = 1,387 × 109

1.13.5 Clock rate = no. instr × CPI/CPU time.
Clock ratenew = no. instr × CPI/0.9 × CPU time = 1/0.9 clock rateold = 3.33 GHz

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Chapter 1

Solutions

S15

1.13.6 Clock rate = no. instr × CPI/CPU time.
Clock ratenew = no. instr × 0.85 × CPI/0.80 CPU time = 0.85/0.80 clock rateold =
3.18 GHz

Solution 1.14
1.14.1 No. instr = 106
a.

T(P1) = 5 × 106 × 0.9/(4 × 109) = 1.125 × 10–3 s
T(P2) = 106 × 0.75/(3 × 109) = 0.25 × 10–3 s
clock rate (P1) > clock rate (P2), performance (P1) < performance (P2)

b.

T(P1) = 3 × 106 × 1.1/(3 × 109) = 1.1 × 10–3 s
T(P2) = 0.5 × 106 × 1/(2.5 × 109) = 0.2 × 10–3 s
clock rate (P1) > clock rate (P2), performance (P1) < performance (P2)

1.14.2
a.

106 instructions, T(P1) = No. Intr × CPI/clock rate
T(P1) = 2.25 × 10–4 s
T(P2) = N × 0.75/(3 × 109) then N = 9 × 105

b.

106 instructions, T(P1) = No. Intr × CPI/clock rate
T(P1) = 3.66 × 10–4 s
T(P2) = N × 1/(3 × 109) then N = 9.15 × 105

1.14.3 MIPS = Clock rate × 10−6/CPI
a.

MIPS(P1) = 4 × 109 × 10–6/0.9 = 4.44 × 103
MIPS(P2) = 3 × 109 × 10–6/0.75 = 4.0 × 103
MIPS(P1) > MIPS(P2), performance(P1) < performance(P2) (from 1.14.1)

b.

MIPS(P1) = 3 × 109 × 10–6/1.1 = 2.72 × 103
MIPS(P2) = 2.5 × 109 × 10–6/1 = 2.5 × 103
MIPS(P1) > MIPS(P2), performance(P1) < performance(P2) (from 1.14.1)

1.14.4 MFLOPS = No. FP operations × 10−6/T
a.

T(P1) = (5 × 105 × 0.75 + 4 × 105 × 1 + 10 × 105 × 1.5)/(4 × 109) = 5.86 × 10–4 s
MFLOPS(P1) = 4 × 105 × 10–6/(5.86 × 10–4 ) = 6.82 × 102
T(P2) = (2 × 106 × 1.25 + 2 × 106 × 0.8 + 1 × 106 × 1.25)/(3 × 109) = 1.78 × 10–3 s
MFLOPS(P1) = 3 × 105 × 10–6/(1.78 × 10–3) = 1.68 × 102

b.

T(P1) = (1.5 × 106 × 1.5 + 1.5 × 106 × 1 + 2 × 106 × 2)/(4 × 109) = 1.93 × 10–3 s
MFLOPS(P1) = 1.5 × 106 × 10–6/(1.93 × 10–3) = 0.77 × 102
T(P2) = (0.8 × 106 × 1.25 + 0.6 × 106 × 1 + 0.6 × 106 × 2.5)/(3 × 109) = 1.03 × 10–3 s
MFLOPS(P2) = 0.6 × 106 × 10–6/(1.03 × 10–3) = 5.82 × 102

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S16

Chapter 1

Solutions

1.14.5
a.

T(P1) = (5 × 105 × 0.75 + 4 × 105 × 1 + 10 × 105 × 1.5)/(4 × 109) = 5.86 × 10–4 s
CPI(P1) = 5.86 × 10–4 × 4 × 109/106 = 2.27
MIPS(P1) = 4 × 109/(2.27 ×106) = 1.76 × 103
T(P2) = (2 × 106 × 1.25 + 2 × 106 × 0.8 + 1 × 106 × 1.25)/(3 × 109) = 1.78 × 10–3 s
CPI(P2) = 1.78 × 10–3 × 3 × 109/(5 × 106) = 1.068 s
MIPS(P2) = 3 × 109/(1.068 × 106) = 2.78 × 103

b.

T(P1) = (1.5 × 106 × 1.5 + 1.5 × 106 × 1 + 2 × 106 × 2)/(4 × 109) = 1.93 × 10–3 s

CPI(P1) = 1.93 × 10–3 × 4 × 109/(5 × 106) = 1.54
MIPS(P1) = 4 × 109/(1.54 × 106) = 2.59 × 103
T(P2) = (0.8 × 106 × 1.25 + 0.6 × 106 × 1 + 0.6 × 106 × 2.5)/(3 × 109) = 1.03 × 10–3 s
CPI(P2) = 1.03 × 10–3 × 3 × 109/(2 ×106) = 1.54
MIPS(P1) = 3 × 109/(1.54 × 106) = 1.94 × 103

1.14.6
a.

T(P1) = 5.86 × 10–4 s (see problem 1.14.5)
performance(P1) = 1/T(P1) = 1.7 × 103
T(P2) = 1.78 × 10–3 s (see problem 1.14.5)
performance(P2) = 1/T(P2) = 5.6 × 102
perf(P1) > perf(P2), MIPS(P1) > MIPS(P2), MFLOPS(P1) < MFLOPS(P2)

b.

T(P1) = 1.93 × 10–3 s (see problem 1.14.5)
performance(P1) = 1/T(P1) = 5.1 × 102
T(P2) = 1.03 × 10–3 s (see problem 1.14.5)
performance(P2) = 1/T(P2) = 9.7 × 102
perf(P1) < perf(P2), MIPS(P1) < MIPS(P2), MFLOPS(P1) > MFLOPS(P2)

Solution 1.15
1.15.1
a.

Tfp = 70 × 0.8 = 56 s. Tnew= 56 + 85 + 55 + 40 = 236 s. Reduction: 5.6%

b.

Tfp = 40 × 0.8 = 32 s. Tnew= 32 + 90 + 60 + 20 = 202 s. Reduction: 3.8%

1.15.2
a.

Tnew = 250 × 0.8 = 200 s, Tfp + Tl/s + Tbranch = 165 s, Tint = 35 s. Reduction time INT: 58.8%

b.

Tnew = 210 × 0.8 = 168 s, Tfp + Tl/s + Tbranch = 120 s, Tint = 48 s. Reduction time INT: 46.6%

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Chapter 1

Solutions

S17

1.15.3
a.

Tnew = 250 × 0.8 = 200 s, Tfp + Tint + Tl/s = 210 s. NO

b.

Tnew = 210 × 0.8 = 168 s, Tfp + Tint + Tl/s = 190 s. NO

1.15.4
Clock cyles = CPIfp × No. FP instr. + CPIint × No. INT instr. + CPIl/s × No. L/S instr. +
CPIbranch × No. branch instr.
Tcpu = clock cycles/clock rate = clock cycles/2 × 109
a.

2 processors: clock cycles = 4,096 × 106; Tcpu = 2.048 s

b.

16 processors: clock cycles = 512 × 106; Tcpu = 0.256 s

To half the number of clock cycles by improving the CPI of FP instructions:
CPIimproved fp × No. FP instr. + CPIint × No. INT instr. + CPIl/s × No. L/S instr. +
CPIbranch × No. branch instr. = clock cycles/2
CPIimproved fp = (clock cycles/2 − (CPIint × No. INT instr. + CPIl/s × No. L/S instr. +
CPIbranch × No. branch instr.))/No. FP instr.
a.

2 processors: CPIimproved fp = (2,048 – 3,816)/280 < 0 ==> not possible

b.

16 processors: CPIimproved fp = (256 – 462)/50 < 0 ==> not possible

1.15.5 Using the clock cycle data from 1.15.4:
To half the number of clock cycles improving the CPI of L/S instructions:

CPIfp × No. FP instr. + CPIint × No. INT instr. + CPIimproved l/s × No. L/S instr. +
CPIbranch × No. branch instr. = clock cycles/2
CPIimproved l/s = (clock cycles/2 − (CPIfp × No. FP instr. + CPIint × No. INT instr. +
CPIbranch × No. branch instr.))/No. L/S instr.
a.

2 processors: CPIimproved l/s = (2,048 – 1,536)/640 = 0.8

b.

16 processors: CPIimproved l/s = (256 – 198)/80 = 0.725

1.15.6
Clock cyles = CPIfp × No. FP instr. + CPIint × No. INT instr. + CPIl/s × No. L/S instr. +
CPIbranch × No. branch instr.
Tcpu = clock cycles/clock rate = clock cycles/2 × 109

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S18

Chapter 1

Solutions

CPIint = 0.6 × 1 = 0.6; CPIfp = 0.6 × 1 = 0.6; CPIl/s = 0.7 × 4 = 2.8; CPIbranch = 0.7 × 2 = 1.4

a.

2 processors: Tcpu (before improv.) = 2.048 s; Tcpu (after improv.) = 1.370 s

b.

16 processors: Tcpu (before improv.) = 0.256 s; Tcpu (after improv.) = 0.171 s

Solution 1.16
1.16.1 Without reduction in any routine:
a.

total time 4 proc = 102 ms

b.

total time 32 proc = 18 ms

Reducing time in routines A, C, and E:
a.

4 proc: T(A) = 10.2 ms, T(C) = 5.1 ms, T(E) = 2.5 ms, total time = 98.8 ms ==> reduction = 3.1%

b.

32 proc: T(A) = 1.7 ns, T(C) = 0.85 ns, T(E) = 1.7 ms, total time = 17.2 ms ==> reduction = 4.4%

1.16.2
a.

4 proc: T(B) = 40.5 ms, total time = 97.5 ms ==> reduction = 4.4%

b.

32 proc: T(B) = 6.3 ms, total time = 17.3 ms ==> reduction = 3.8%

1.16.3
a.

4 proc: T(D) = 32.4 ms, total time = 98.4 ms ==> reduction = 3.5%

b.

32 proc: T(D) = 5.4 ms, total time = 17.4 ms ==> reduction = 3.3%

1.16.4

AQ 5

Computing Time
Ratio

Routing Time Ratio

131 ms

0.65

1.18

85 ms

0.65

1.31

16

56 ms

0.66

1.29

32

35 ms

0.62

1.05

64

18.5 ms

0.53

1.13

No. Processors

Computing Time

2

201 ms

4
8

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Chapter 1

Solutions

S19

1.16.5 Geometric mean of computing time ratios = 0.62. Multiplying this
by the computing time for a 64-processor system gives a computing time for a
128-processor system of 11.474 ms.
Geometric mean of routing time ratios = 1.19. Multiplying this by the routing time
for a 64-processor system gives a routing time for a 128-processor system of 30.9 ms.
1.16.6 Computing time = 201/0.62 = 324 ms. Routing time = 0, since no communication is required.

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Author Query
AQ 1: Page S2: As meant t/o?
AQ 2: Page S3: As meant t/o?
AQ 3: Page S4: Close up t/o?
AQ 4: Page S12: Inserted heading OK?
AQ 5: Page S18: Blank cells as meant?

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