Lecture Digital logic design - Lecture 20: Sequential circuits: Latches

0

0

Avoid

1 (set)

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Characteristic Table
° In order to remember previous inputs, sequential circuits
must have some sort of storage element. This storage
element is called “flip-flop”.
° Flip-flop depends on previous inputs to the circuit.
° The basic memory unit is called an SR flip-flop.
° We can describe flip-flops using characteristic table.
SR Flip-Flop operation (BUILT WITH NOR GATES)
Characteristic table

Excitation table

S

R

Action

0

0

0
1
1

Q(t)

Q(t+1)

S

R

Action

Keep state 0

0

0

X

No
change

1

Q=0

0

1

1

0

reset

0

Q=1

1

0

0

1

set

1

Unstable
combinati
on

1

1

X

0

race conditio

21


Review: Steering Gates
° The flow of logic can be controlled with a logic
gate.

1
Signal
10

°°10

1

Control

The NAND as a steering gate inverts the input.
22

Steering Gates
° A control input ‘0’ inhibits the signal.

01
1
Signal

°°10

1

Control 0

23


Steering Gates

Signal
01
1

Control

°°10
1

Signal

0
1

°°10

Output Enabled (inverted)

24


Steering Gates

Signal
10
Control

°°10

1

0

Signal
101

1
°°10

Output Disabled

25


An SR latch with a control input
° Here is an SR latch with a control input C
C

S

R

S’

R’

Q

0
1
1
1
1

x
0
0
1
1

x

0
1
0
1

1
1
1
0
0

1
1
0
1
0

No  c h ang e
No  c h ang e
0  ( r e s e t )
1 ( s e t )
A vo id !

° Notice the hierarchical design!
• The dotted blue box is the S’R’ latch from the previous slide
• The additional NAND gates are simply used to generate the correct
inputs for the S’R’ latch

° The control input acts just like an enable

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S-R Latch with NANDs
S

R

Q 

 S    R    Q     Q’

Q’

0
0
1
1

0
1
0
1

1
1
0
0
1

1
0
1
1
0

Disallowed
Set
Reset
Store

° Latch made from cross-coupled NANDs
° Sometimes called S’-R’ latch
° Usually S=1 and R=1
° S=0 and R=0 generates unpredictable results

27


S-R Latches

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S-R Latch with control
input

° Occasionally, desirable to avoid latch changes
° C = 0 disables all latch state changes
° Control signal enables data change when C = 1

° Right side of circuit same as ordinary S-R latch.
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NOR S-R Latch with Control Input
Latch
Latch is
is level-sensitive
level-sensitive,, in
in regards
regards to
to C
C
Only stores data if C’ = 0
R’

Q

C’

Latch
Latch operation
operation S’
enabled
enabled by
by
C
C
Input sampling
enabled by gates

Q’

Outputs
Outputs change
change
when
when C
C is
is low:
low:
RESET
RESET and
and SET
SET
Otherwise:
Otherwise: HOLD
HOLD
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Problems with SR Latch
° The problem with the SR Latch is that it requires
two inputs to store one value.
° A latch is needed where one input is applied to
store one value.
° A control input is also required to place the device
in a hold state.
° Moreover there is a race condition (undefined)

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D Latch
° Q0 indicates the previous state (the previously
stored value)
X
D 
S
Q 
C 
Q’

R

Y
 D     C      Q   Q’
0 1 0 1
1 1 1 0
X 0 Q0  Q0’ 

  X    Y     C    Q    Q’
0
0
1
1
X

0
1

0
1
X

1
1
1
1
0

Q0   Q0’  Store  
0 1 Reset
1 0 Set
1 1 Disallowed
Q0   Q0’  Store
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D Latch
X

D 

S
Q 

C 
Q’

Y

R

 D     C      Q    Q’
0 1 0 1
1 1 1 0
X 0 Q0   Q0’ 
° Input value D is passed to output Q when C is high
° Input value D is ignored when C is low
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D Latch
Latches on following 
edge of clock

    E 

x
E 

D 
C

Q 

z

x
z

° Z only changes when E is high
° If E is high, Z will follow X

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D Latch
Latches on following 
edge of clock

    E 

x
E 

D 
C

Q 

z

x
z

° The D latch stores data indefinitely, regardless of
input D values, if C = 0
° Forms basic storage element in computers
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Symbols for
Latches

° SR latch is based on NOR gates
° S’R’ latch based on NAND gates
° D latch can be based on either.

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Summary
° Latches are based on combinational gates (e.g. NAND,
NOR)
° Latches store data even after data input has been
removed
° S-R latches operate like cross-coupled inverters with
control inputs (S = set, R = reset)
° With additional gates, an S-R latch can be converted to
a D latch (D stands for data)
° D latch is simple to understand conceptually
• When C = 1, data input D stored in latch and output as Q
• When C = 0, data input D ignored and previous latch value output at Q

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