Tài liệu THE DIGITAL LOGIC LEVEL-3 ppt

3
THE DIGITAL LOGIC LEVEL
1
Collector
Base
+V
CC
V
out
V
in
Emitter
(a)
V
out
+V
CC
+V
CC
V
out
V
2
(b)
V
1
V
1
(c)
V
2

Figure 3-1. (a) A transistor inverter. (b) A
NAND
gate. (c) A
NOR
gate.
(b)
NAND
A
B
X
A B X
0 0 1
0 1 1
1 0 1
1 1 0
(c)
NOR
A
B
X
A B X
0 0 1
0 1 0
1 0 0
1 1 0
AND
A
B
X
(d)

A B X
0 0 0
0 1 0
1 0 0
1 1 1
OR
A
B
X
(e)
A B X
0 0 0
0 1 1
1 0 1
1 1 1
(a)
NOT
A
AX
X
0 1
1 0
Figure 3-2. The symbols and functional behavior for the five basic gates.
A B C
0 0 0
0 0 1
0 1 0
0 1 1
M
0

0
0
1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
1
1
(a) (b)
ABC
A
A
B
C
BC A
A
B C
ABC
ABC
ABC
M
1
4
8
5
6
7

B
2
C
3
Figure 3-3. (a) The truth table for the majority function of
three variables. (b) A circuit for (a).
A + B
A + B
A
A
B
B
AB
AB
A
A
A
A
(a)
(b) (c)
A
B
A
B
Figure 3-4. Construction of (a)
NOT
, (b)
AND
, and (c)
OR

gates using only
NAND
gates or only
NOR
gates.
C
B
A
A(B + C)
B + C
A
B
C
AB + AC
AB
AC
(a) (b)
A
B C AB AC AB + AC
0 0 0 0 00
0 0 1 0 00
0 1 0 0 00
0 1 1 0 00
1 0 0 0 00
1 0 1 0 11
1 1 0 1 01
1 1 1 1 11
A B C A B + C A(B + C)
0 0 0 0 00
0 0 1 0 10

0 1 0 0 10
0 1 1 0 10
1 0 0 1 00
1 0 1 1 11
1 1 0 1 11
1 1 1 1 11
Figure 3-5. Two equivalent functions. (a)
AB + AC
. (b)
A(B + C)
.
Identity law
Null law
Idempotent law
Inverse law
Commutative law
Associative law
Distributive law
Absorption law
De Morgan's law
1A = A
0A = 0
AA = A
AB = BA
(AB)C = A(BC)
A + BC = (A + B)(A + C)
A(A + B) = A A + AB = A
0 + A = A
1 + A = 1
A + A = A

A + B = B + A
(A + B) + C = A + (B + C)
A(B + C) = AB + AC
Name AND form OR form
AA = 0
AB = A + B
A + A = 1
A + B = AB
Figure 3-6. Some identities of Boolean algebra.
(a)
AB =
A + B
(c)
A + B
AB =
(b)
A + B = AB
AB
=
(d)
A + B
Figure 3-7. Alternative symbols for some gates: (a)
NAND
. (b)
NOR
.
(c)
AND
. (d)
OR

.
(a) (b)
A
B XOR
0 0 0
0 1 1
1 0 1
1 1 0
A
B
B
A
(d)(c)
A
B
B
A
A
B
B
A
Figure 3-8. (a) The truth table for the
XOR
function. (b)-(d)
Three circuits for computing it.
(a)
A
B
0
V

0
V
0
V
5
V
5
V
0
V
5
V
5
V
F
0
V
0
V
0
V
5
V
(b)
A
B
0 0
0 1
1 0
1 1

F
0
0
0
1
(c)
A
B
1 1
1 0
0 1
0 0
F
1
1
1
0
Figure 3-9. (a) Electrical characteristics of a device.
(b) Positive logic. (c) Negative logic.
Notch
11
V
CC
Pin 8
GND
10 9 8121314
4 5 6 7321
Figure 3-10. An SSI chip containing four gates.
F
D

0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ABC
AA
B CBC
Figure 3-11. An eight-input multiplexer circuit.
(a)
ABC
F
D
0
D
1
D
2
D
3

D
4
D
5
D
6
D
7
(b)
V
CC
ABC
F
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Figure 3-12. (a) An MSI multiplexer.. (b) The same multi-

plexer wired to compute the majority function.
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
A
C
B
A
B
C
B
C
A
Figure 3-13. A 3-to-8 decoder circuit.
A = B
A
0

B
0
A
1
B
1
A
2
B
2
A
3
B
3
EXCLUSIVE OR gate
Figure 3-14. A simple 4-bit comparator.
A
If this fuse is
blown, B is not
an input to AND
gate 1.
12 ϫ 2 = 24
input signals
24 input lines
6 outputs
50 input
lines
If this fuse is
blown, AND gate
1 is not an input

to OR gate 5.
B
L
149
0
1
5
0
Figure 3-15. A 12-input, 6-output programmable logic array.
The little squares represent fuses that can be burned out to
determine the function to be computed. The fuses are arranged
in two matrices: the upper one for the
AND
gates and the lower
one for the
OR
gates.
C
D
0
D
1
D
2
D
3
D
4
D
5

D
6
D
7
S
0
S
1
S
2
S
3
S
4
S
5
S
6
S
7
Figure 3-16. A 1-bit left/right shifter.
A
A
B
B Sum
Sum
Carry
Carry
Exclusive OR gate
0000

0110
1010
1101
Figure 3-17. (a) Truth table for 1-bit addition. (b) A circuit for a half adder.
B
A
B
Carry
in
Sum
Sum
Carry
out
0000
0110
1010
1
A
0
0
0
0 101
0010
0101
1001
1
1
1
1
1 111

Carry in
Carry out
(a) (b)
Figure 3-18. (a) Truth table for full adder. (b) Circuit for a full adder.
A
INVA
ENA
B
Logical unit
Carry in
AB
B
Enable
lines
F
0
F
1
Decoder
Output
Sum
Carry out
Full
adder
A + B
ENB
Figure 3-19. A 1-bit ALU.
Carry
in
Carry

out
1-bit
ALU
F
0
F
1
A
7
B
7
O
7
1-bit
ALU
A
6
B
6
O
6
1-bit
ALU
A
5
B
5
O
5
1-bit

ALU
A
4
B
4
O
4
1-bit
ALU
A
3
B
3
O
3
1-bit
ALU
A
2
B
2
O
2
1-bit
ALU
A
1
B
1
O

1
1-bit
ALU
INC
A
0
B
0
O
0
Figure 3-20. Eight 1-bit ALU slices connected to make an 8-
bit ALU. The enables and invert signals are not shown for sim-
plicity.
Delay
C1
C2
(a) (b)
A
B
C
(c)
Figure 3-21. (a) A clock. (b) The timing diagram for the
clock. (c) Generation of an asymmetric clock.
A B NOR
001
010
100
110
R
Q

S
0
0
1
0
0
1
Q
R
Q
S
0
1
0
0
1
0
Q
(a) (b) (c)
Figure 3-22. (a)
NOR
latch in state 0. (b)
NOR
latch in state 1.
(c) Truth table for
NOR
.
S
Q
Q

R
Clock
Figure 3-23. A clocked SR latch.
D
Q
Q
Figure 3-24. A clocked D latch.