QUARTUS II INTRODUCTION USING VERILOG DESIGN

QUARTUS II INTRODUCTION
QUARTUS II INTRODUCTION
USING VERILOG DESIGN
USING VERILOG DESIGN
VIETNAM NATIONAL UNIVERSITY OF HOCHIMINH CITY
INTEGRATED CIRCUIT DESIGN RESEARCH AND EDUCATION CENTER
(ICDREC)
FEB – 18 - 2007
By NGO DUC HOANG
DEPUTY DIRECTOR

A TYPICAL FPGA CAD FLOW
A TYPICAL FPGA CAD FLOW
Design Entry
Synthesis
Functional Simulation
Design correct?
Timing Analysis and Simulation
Timing requirements met?
Fitting (Place and Route)
Yes
No
Programming and Configuration
Yes
No

QUARTUS II DEVELOPMENT
QUARTUS II DEVELOPMENT
SYSTEM
SYSTEM




Fully-integrated Design Tool
Fully-integrated Design Tool


Multiple Design Entry Methods
Multiple Design Entry Methods



Logic Synthesis
Logic Synthesis



Place and Route
Place and Route



Simulation (functional and timing)
Simulation (functional and timing)



Timing and Power Analysis
Timing and Power Analysis


Device Programming and Configuration
Device Programming and Configuration

Design Entry (1 of 2)
Design Entry (1 of 2)
The desired circuit is specified by:
The desired circuit is specified by:

A schematic diagram
A schematic diagram

A hardware description language,
A hardware description language,
such as:
such as:

Verilog
Verilog

VHDL
VHDL



AHDL…
AHDL…

Design Entry (2 of 2)

Design Entry (2 of 2)

Design Entry by a schematic diagram
Design Entry by a schematic diagram

Design Entry by a hardware description
Design Entry by a hardware description
language
language

Synthesis
Synthesis

The entered design is synthesized into a
The entered design is synthesized into a
circuit that consists of the
circuit that consists of the
logic elements
logic elements


(
(
LEs
LEs
) provided in the FPGA chip
) provided in the FPGA chip
.
.


LE is the smallest unit of logic of Altera’s
LE is the smallest unit of logic of Altera’s
FPGA. It’s compact and provides advanced
FPGA. It’s compact and provides advanced
features with efficient logic ultilization.
features with efficient logic ultilization.

This course doesn’t cover the architecture
This course doesn’t cover the architecture
of Altera’s FPGA
of Altera’s FPGA

LE logic element
LE logic element

Fitting (placement and routing)
Fitting (placement and routing)

The placement of the LEs defined in the
The placement of the LEs defined in the
netlist into the LEs in an actual FPGA chip,
netlist into the LEs in an actual FPGA chip,
also choose routing wires in the chip to
also choose routing wires in the chip to
make the required connections between
make the required connections between
specific LEs
specific LEs

Timing Analysis

Timing Analysis

Analyze the propagation delays along the
Analyze the propagation delays along the
various paths in the fitted circuit
various paths in the fitted circuit

Timing Simulation
Timing Simulation

The fitted circuit is tested to verify both its
The fitted circuit is tested to verify both its
functional correctness and timing
functional correctness and timing

Programming and Configuration
Programming and Configuration

The design circuit is implemented in a
The design circuit is implemented in a
physical FPGA chip by programming the
physical FPGA chip by programming the
configuration switches that configure the
configuration switches that configure the
LEs and establish the required wiring
LEs and establish the required wiring
connections
connections

Quartus II Project Management

Quartus II Project Management

What is a Project ?
What is a Project ?


- A logic circuit or subcircuit
- A logic circuit or subcircuit


- A project is:
- A project is:


+ checked for design entry errors
+ checked for design entry errors


+ compiled
+ compiled


+ simulated (functional or timing)
+ simulated (functional or timing)


+ analyzed for timing
+ analyzed for timing

+ used to generate programming file
+ used to generate programming file

Quartus II works on one project at a time and
Quartus II works on one project at a time and
keeps all information for that project in a single
keeps all information for that project in a single
directory (folder).
directory (folder).

Quartus II Project –New Project
Quartus II Project –New Project
Select File > New Project Wizard
New Project Wizard help us create a new
project and preliminary project
settings, including the following:
•
Project name and directory
•
Name of the top-level design entity
•
Project files and libraries
•
Target device family and device
•
EDA tool settings
You can change or add the settings of the
project with the Settings command
(Assignment menu)
1

2

Quartus II Project – Directory, Name, Top-
Quartus II Project – Directory, Name, Top-
Level Entity
Level Entity
•
You can choose any
directory name if you
prefer. If we have not yet
created the directory of
the project, Quartus II
asking if it should create
the desired directory.
•
The project must have a
name, which is usually
the same as the top-level
design entity

Quartus II Project – Add Files
Quartus II Project – Add Files
To specify existing
files should be
included in the
project.
Click Next if we do
not have any existing
files.
3

Quartus II Project – Family and Device
Quartus II Project – Family and Device
Settings
Settings
To specify the type of
device in which the
designed circuit will be
implemented. In case of
DE2 board, we choose:
•
The device is
EP2C35F672C6 which
is the FPGA used on
DE2 board
•
The target device family
is Cyclone II

Quartus II Project – EDA Tools
Quartus II Project – EDA Tools
Settings
Settings
To specify any third-
party tools that
should be used. EDA
is means Electronic
Design Automation,
a commonly used
term for CAD

software for
electronic circuits.
4

Quartus II - Summary
Quartus II - Summary
5

Design Entry using Verilog – An
Design Entry using Verilog – An
example
example
module light(x1,x2,f);
input x1,x2;
output f;
assign f = (x1&~x2)|(~x1&x2);
endmodule

Design Entry using Verilog – Quartus II
Design Entry using Verilog – Quartus II
Text Editor (1 of 6)
Text Editor (1 of 6)
Select File >
New to get
the right
figure, then
choose
Verilog HDL
File, and
click OK

1
2
4
3

Design Entry using Verilog – Quartus II
Design Entry using Verilog – Quartus II
Text Editor (2 of 6)
Text Editor (2 of 6)
Quartus II open the
Text Window
Editor. The default
name of design file
is Verilog1.v. The
first step is to
specify a name for
the file that will be
created. Select File
> Save As

Design Entry using Verilog – Quartus II
Design Entry using Verilog – Quartus II
Text Editor (3 of 6)
Text Editor (3 of 6)
In the box labeled Save
as type choose Verilog
HDL File.
In the box labeled
File name , type light
Put a checkmark in the

box Add file to current
project
Click Save

Design Entry using Verilog – Quartus II
Design Entry using Verilog – Quartus II
Text Editor (4 of 6)
Text Editor (4 of 6)
Type the Verilog
code of our
design into Text
Editor.
Save the file
light.v by choose
File > Save.