Acer aspire 3100 5100 COMPAL LA 3151p HCW50 REV 0 3

A

B

C

D

E

1

1

Compal Confidential

2

2

HCW50 Schematics Document
AMD/Sempron/ATI RX485/SB460 W/s M52/54/56P
2006 / 02 / 28

Rev:0.3 (For PVT)

3

3

4

4

Compal Secret Data

Security Classification
2005/05/09

Issued Date

Deciphered Date

2006/03/08

B

C

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

D

Size Document Number
Custom 401412
Date:

,

09, 2006

Rev
B
Sheet
E

1

of

55


5

4

3

2

1

Compal confidential
Project Code: HCW50
File Name : LA-3151P

Thermal Sensor
ADM1032ARM

AMD Turion/Sempron CPU
Socket S1 638P

Clock Generator
ICS951462

DDRII

DDRII-SO-DIMM X2
page 9,10

page 5,6,7,8
page 7

D

Dual Channel DDR-II

page 15

D

H_A#(3..31)

H_D#(0..63)
HT 16x16 800MHZ

DVI-D Conn.

LCD CONN

page 30

page 29

CRT & TV-OUT

ATI-RX485M

page 28

465 BGA
page 11,12,13,14

A-Link Express
2 x PCIE

PCI-Express
ATI M52PG/M54P/M56P

USB conn x 2 / New card

USB 2.0

with 64/128/256MB VRAM
C

page 39

page 16,17,18,19,20,21

ATI-SB460

BT Conn

USB 2.0

page 34

549 BGA

PCI BUS

Audio CKT
ALC883

AC-LINK

Mini PCI Socket
Mini card / CAM
page 36

page 22,23,24,25,26

Realtek
RTL8100CL
RTL8110SCL

ENE Controller
CB714

page 31

1394 Controller
VT6311S

page 32

B

6in1 CardReader
page 38
Slot

page 38

page 45

MDC Conn.

page 34

page 40

page 37

Slot 0

AMP & Audio Jack

page 44

SATA HDD Conn.

SATA

RJ45 CONN

C

page 27

LPC BUS

1394
Conn.

B

page 40

PATA One Channel HDD Conn.

CDROM Conn.
page 27

Power On/Off CKT / LID switch / Power OK CKT
page 42

DC/DC Interface CKT.
page 46

SMsC LPC47N207
CIR/LED

RTC CKT.

page 43

ENE KB910

page 41

page 33

page 22

Power Circuit DC/DC

Int. KBD

FIR module

page 34

page 41

page 46~

Touch Pad
CONN.page 34

BIOS
page 35

A

Compal Secret Data

Security Classification
2005/03/08

Issued Date

2006/03/08

Deciphered Date

4

3

Title

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

A

2

Size Document Number
Custom 401412
Date:

,

R ev
B
Sheet

09, 2006
1

2

of

55


5

4

3

2

SIGNAL

STATE

Voltage Rails

D

C

Full ON

1

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

+VALW

+V

+VS

Clock

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

ON

Power Plane

Description

S0

S3

S5

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

VIN

Adapter power supply (19V)

N/A

N/A

N/A

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

+0.9V

0.9V switched power rail for DDRII terminator

ON

ON

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

+1.2V_HT

1.2V switched power rail

ON

OFF

OFF

+1.5VS

1.5V switched power rail

ON

OFF

OFF

+1.8V

1.8V power rail for DDRII

ON

ON

OFF

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+2.5VS

2.5V switched power rail

ON

OFF

OFF

Vcc
Ra/Rc/Re

+3VALW

3.3V always on power rail

ON

ON

ON*

Board ID

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON*

+1.2VS

1.2V switched power rail for PCIE

ON

OFF

OFF

+0.9VS

0.9V switched power rail for VRAM terminator

ON

OFF

OFF

+1.8VALW

1.8V switched power rail

ON

ON

ON*

0
1
2
3
4
5
6
7

+VDD_CORE

1.0~1.2V switched power rail for VGA

ON

OFF

OFF

D

Board ID / SKU ID Table for AD channel

Board ID
0
1
2
3
4
5
6
7

External PCI Devices
IDSEL#

Ca rdBus(SD)

REQ#/GNT#

Interrupts

AD20

2

PIRQE/PIRQH

1 394

AD16

0

PIRQE

LAN(10/100)

AD17

3

PIRQF

Mini-PCI(WLAN/TV-Tuner) AD18

1

PIRQG/PORQH

V AD_BID min

0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

BOARD ID Table

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Device

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%

18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

PCB Revision
0.1

BTO Item
VGA
UMA
UMA's DVI
LAN(10/100)
LAN(GIGA)
MINI CARD1
MINI CARD2
SATA-to-IDE
PATA
GRAPEVINE
G72MV Only
G73 Only
VRAM
VRAM 64M
VRAM 128M
VRAM 256M
MEDIA/B
CIR
FIR

GENEVA
LCM
Sub-woofer

Device

Address

Smart Battery

0001 011X b

EEPROM(24C16/02)

1010 000X b

GMT G781-1

1001 101X b

SKU ID Table

EC SM Bus2 address
Device
Fintek F75383M

SKU ID
0
1
2

3
4
5
6
7

Address
1001 100X b

SB460 SM Bus address

A

Device

Address

Clock Generator
(ICS9LPRS325AKLFT_MLF72)

1101 001Xb

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 010Xb

SKU
PM
GM

BOM Structure

B

A

Compal Secret Data

Security Classification
2005/03/08

Issued Date

2006/03/08

Deciphered Date

4

3

Title

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

C

BTO Option Table

B

EC SM Bus1 address

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

2

Size Document Number
Custom 401412
Date:

,

R ev
B
Sheet

09, 2006
1

3

of

55


5

4

3

2

+5V

BATTERY
CHARGER

BATTERY

+3.3VSUS_NTB
+VDC

MAIN PWR SW
REGULATOR

VCCA 2.5V

12V
+/-5%

+5V_NTB

+VIN_MEM
+5VSUS

5VSB
+/-5%

+5VALW_ATX

POWER SWITCH

SWITCH

CPU
PWR
12V
+/-5%

SWITCH

+3.3V_NTB

+3.3VALW

NB CORE 10A

+VIN

PCIE&SB SW
REGULATOR

VDDA_1V2(S0, S1)

PCI-E CORE
&PCI-E IO 3.5A
HTPLL (1.8V) 200mA

+5V

1.8V SW
REGULATOR

+1.8V(S0, S1)

PLL & DAC-Q(1.8V)
200mA
TRANSFORMER

400mA
DAC 300mA

+3.3V
+5V
+3.3V

AVDD (S0, S1)

+5VDUAL_ATX

SW

+5V_ATX
+3.3VALW LDO
REGULATOR

+5VSUS

DDRII SODIMMX2
+VIN

+3.3VALW_ATX
+5V

+3.3VDUAL_ATX

SW

CPU_VDDIO_SUS (S0, S1, S3)

1.8V VDD&VTT
SW REGULATOR

+5VSUS

VDD MEM 4A

CPU_VTT_SUS (S0, S1,S3)
VCC_SB (S0, S1)

5V
+/-5%

D

NB RS485

VCC_NB (S0, S1)

NB CORE SW
REGULATOR

+5V

+5VALW

3.3V
+/-5%

VLDT 1.2V 3A

HT VLDT 1.2V 1A

+VIN

+3.3VSUS

VDDCORE
0.375-1.500V 30A

VLDT_RUN (S0, S1)

VLDT 1.2V SW
REGULATOR

+5V

ATX POWER SUPPLY

CPU_VDD_RUN (S0, S1)

SW REGULATOR

+VIN

+5VSUS_NTB

D

+3.3V_ATX

-12V
+/-5%

C

AMD CPU

+VIN
+5V

+5VALW_NTB

SW

CPU_VDDA_RUN (S0, S1)

1.5V SW
REGULATOR

+3.3VALW_NTB

1

VTT_MEM 0.5A

C

SB SB600
X4 PCI-E 0.8A

ATA I/O 0.2A
ATA PLL 0.01A
PCI-E PVDD 80mA
SB CORE 0.6A

CONTROL SIGNAL:

+3.3VALW

1.2V LDO
REGULATOR

+1.2VALW

1.2V S5 PW 0.22A

MOBILE: BATTERY

+3.3V

DESKTOP: ATX

+3.3VALW

3.3V S5 PW 0.01A

+5V

USB CORE I/O 0.2A

B

3.3V I/O 0.45A

MINI PCI SLOT

GBIT ENTHENET

+3.3V

3.3V(S0, S1)1.5A

+5V

5V (S0, S1) 0.1A

3.3V 0.5A
(S0, S1, S3, S4, S5)

+3.3VALW

3.3V(S3, S5) 0.2A

+VIN

B

PCI-E CARD
1.5V (S0, S1) 0.7A
3.3V (S3, S5) 0.3A

+3.3V

3.3V (S0, S1) 1.3A

+5V
PCI Slot (per slot)
5V

5.0A

3.3V

7.6A

12V

0.5A

3.3Vaux

0.375A

-12V

0.1A

X1 PCIE per
3.3V
12V

3.0A
0.5A

3.3Vaux 0.1A

X16 PCIE
3.3V
12V

3.0A
5.5A

SUPER I/O

+5VALW

CNR CONNECTOR

+3.3VDUAL (S3) 0.01A

5V

1.0A

3.3V

1.0A

12V

0.5A

VDD

VDD

3.3Vaux

1.0A

5VDual

5VDual

-12V

0.1A

3.5A

1.0A

5VDual

0.5A

USB X7 FR

USB X2 RL

+3.3V (S0, S1) 0.01A

2XPS/2

+5V (S0, S1) 0.1A

5VDual
HD CODEC

1.0A

3.3V CORE 0.3A
5V ANALOG 0.1A

A

A

Compal Secret Data

Security Classification
2005/03/08

Issued Date

2006/03/08

Deciphered Date

4

3

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

2

Size Document Number
Custom 401412
Date:

,

R ev
B
Sheet

09, 2006
1

4

of

55


5

4

<11> H_CADIP[0..15]
<11> H_CADIN[0..15]

3

H_CADIP[0..15]
H_CADIN[0..15]

H_CADOP[0..15]
H_CADON[0..15]

2

1

H_CADOP[0..15] <11>
H_CADON[0..15] <11>

PROCESSOR HYPERTRANSPORT INTERFACE

D

D

VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

FAN1 Conn

+1.2V_HT
JP72A
VLDT_A3
VLDT_A2
VLDT_A1
VLDT_A0

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9

H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

N5
P5
M3
M4
L5
M5
K3
K4
H3
H4

G5
H5
F3
F4
E5
F5
N3
N2
L1
M1
L3
L2
J1
K1
G1
H1
G3
G2
E1
F1
E3
E2

L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12

L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0

H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0

J5
K5
J3
J2

L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0

H_CTLIP1
H_CTLIN1

P3
P4

H_CTLIP0
H_CTLIN0

N1
P1

2 C1
4.7U_0805_10V4Z

VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0

AE5
AE4
AE3
AE2

L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4

L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0

T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1

U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7

H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0

Y4
Y3
Y1
W1

H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0

H_CLKOP1
H_CLKON1
H_CLKOP0
H_CLKON0

L0_CTLIN_H1
L0_CTLIN_L1

L0_CTLOUT_H1
L0_CTLOUT_L1

T5
R5

L0_CTLIN_H0
L0_CTLIN_L0

L0_CTLOUT_H0
L0_CTLOUT_L0

R2
R3

H_CTLOP0
H_CTLON0

H_CTLOP0 <11>
H_CTLON0 <11>

1

+5VS
C2
1

+5VS

10U_0805_10V4Z
2

1

D4
D3
D2
D1

+1.2V_HT
R2 1
R3 1

<11>
<11>
<11>
<11>

H_CLKIP1
H_CLKIN1
H_CLKIP0
H_CLKIN0

2 51_0402_1%
2 51_0402_1%
<11> H_CTLIP0
<11> H_CTLIN0

B

<33> EN_DFAN1

GND
GND
GND
GND

D1
1SS355_SOD323

8
7
6
5

2

+VCC_FAN1
EN_DFAN1

VEN
VIN

VO
VSET

G993P1UF_SOP8

D2
1N4148_SOT23
1
2
C3
10U_0805_10V4Z
1
2

+3VS
1

C4
1000P_0402_50V7K
1
2
C

R1
10K_0402_5%

40mil
2

C

U2
1
2
3
4

JP73

+VCC_FAN1

1
2
3

<33> FAN_SPEED1
1

C5
1000P_0402_50V7K

ACES_85205-03001

2

<11>
<11>
<11>
<11>

B

Athlon 64 S1
Processor Socket

+1.2V_HT

1

2

C6

C8

10U_0805_10V4Z

1

C9

1

C10

1

2
2
2

0.22U_0603_10V7K
180P_0402_50V8J
0.22U_0603_10V7K

C11

1

2

180P_0402_50V8J

LAYOUT: Place bypass cap on topside of board
NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS

A

A

Compal Secret Data

Security Classification
2005/10/11

Issued Date

2006/10/11

Deciphered Date

4

3

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

2

Size Document Number
Custom 401412
Date:

,

R ev
B
Sheet

09, 2006
1

5

of

55


B

C

DDR_A_MA[0..15]

<9> DDR_A_MA[0..15]

DDR_B_DQS#[0..7]

<10> DDR_B_DQS#[0..7]

<10> DDR_B_D[0..63]

JP72C

+0.9VREF_CPU
+0.9V

1

JP72B

AE10
AF10

VTT_SENSE
M_ZN
M_ZP

R5
39.2_0402_1%~D
DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9

D10
C10
B10

AD10
W10
AC10
AB10
AA10
A10
DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1

V19
J22
V22
T19

MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0

MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1

Y16
AA16
E16
F16

<10> DDR_CS3_DIMMB#
<10> DDR_CS2_DIMMB#
<10> DDR_CS1_DIMMB#

DDR_CS3_DIMMB# Y26
DDR_CS2_DIMMB# J24
DDR_CS1_DIMMB# W24
DDR_CS0_DIMMB# U23

MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0

MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1

AF18 DDR_B_CLK2
AF17 DDR_B_CLK#2
A17 DDR_B_CLK1
A18 DDR_B_CLK#1

<10>
<10>
<9>
<9>

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

H26
J23
J20
J21

MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0

MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0

W23
W26
V20
U19

DDR_B_ODT1
DDR_B_ODT0
DDR_A_ODT1
DDR_A_ODT0

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

K19
K20
V24
K24
L20
R19
L19
L22
L21
M19
M20
M24
M22

N22
N21
R21

MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0

MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7

MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0

J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24

DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11

DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

<9> DDR_A_BS#2
<9> DDR_A_BS#1
<9> DDR_A_BS#0

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

K22
R20
T22

MA_BANK2
MA_BANK1
MA_BANK0

MB_BANK2
MB_BANK1

MB_BANK0

K26 DDR_B_BS#2
T26 DDR_B_BS#1
U26 DDR_B_BS#0

DDR_B_BS#2 <10>
DDR_B_BS#1 <10>
DDR_B_BS#0 <10>

<9> DDR_A_RAS#
<9> DDR_A_CAS#
<9> DDR_A_WE#

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

T20
U20
U21

MB_RAS_L
MB_CAS_L
MB_WE_L

U24 DDR_B_RAS#
V26 DDR_B_CAS#
U22 DDR_B_WE#

DDR_B_RAS# <10>
DDR_B_CAS# <10>
DDR_B_WE# <10>

<9>
<9>
<9>
<9>

2

1

2

Y10
M_ZN
M_ZP

M_VREF

DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

PLACE THEM CLOSE TO <10> DDR_CS0_DIMMB#
CPU WITHIN 1"
DDR_CKE1_DIMMB
DDR_CKE0_DIMMB

DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

3

MA_RAS_L
MA_CAS_L
MA_WE_L

DDR_A_CLK2 <9>
DDR_A_CLK#2 <9>
DDR_A_CLK1 <9>
DDR_A_CLK#1 <9>
DDR_B_CLK2 <10>
DDR_B_CLK#2 <10>
DDR_B_CLK1 <10>
DDR_B_CLK#1 <10>
DDR_B_ODT1 <10>
DDR_B_ODT0 <10>
DDR_A_ODT1 <9>
DDR_A_ODT0 <9>
DDR_B_MA[0..15] <10>

Athlon 64 S1
Processor
Socket

<10> DDR_B_DM[0..7]

DDR_A_CLK2

DDR_B_CLK2
1

DDR_A_CLK#2

2

1
C12
1.5P_0402_50V8C
DDR_B_CLK#2

DDR_A_CLK1

C13
1.5P_0402_50V8C

2

1
C14
1.5P_0402_50V8C
DDR_B_CLK#1

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

2

2

DDR_B_CLK1
1

DDR_A_CLK#1

To reverse SODIMM socket

W17
R4
39.2_0402_1%~D

2

DDR_A_DQS[0..7]

<9> DDR_A_DQS[0..7]

DDR_A_DQS#[0..7]

<9> DDR_A_DQS#[0..7]

+1.8V
4

E

Processor DDR2 Memory Interface

DDR_B_DQS[0..7]

<10> DDR_B_DQS[0..7]

VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

D

C15
1.5P_0402_50V8C

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50

DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20

DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0

AD11
AF11
AF14
AE14
Y11
AB11
AC12
AF13
AF15

AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24
G24
G23
D26
C26
G26
G25
E24

E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11

MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60

MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30

MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

AD12
AC16
AE22
AB26
E25
A22
B16
A12

MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0

DDR_B_DQS7
DDR_B_DQS#7

DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

AF12
AE12
AE16
AD16
AF21
AF22
AC25
AC26
F26
E26
A24
A23
D16
C16
C12

B12

MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53

MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23

MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

AA12
AB12
AA14
AB14
W11
Y12

AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21

J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12

DDR_A_D63

DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33

DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3

DDR_A_D2
DDR_A_D1
DDR_A_D0

MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

Y13
AB16
Y19
AC24
F24
E19
C15
E12

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0

MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0

W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21

G16
G15
G13
H13

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_D[0..63] <9>

4

To normal SODIMM socket

A

3

DDR_A_DM[0..7] <9>

2

DDR: DATA
Athlon 64 S1
Processor Socket

ATI check ,Use +0.9V PWR , can delete or not

A1

A26

+1.8V

1

Athlon 64 S1g1

R6
1K_0402_1%

uPGA638

+0.9VREF_CPU
2

Top View

1
1

1

2

+0.9VREF_CPU

2
1000P_0402_50V7K

C16

C18

1

1

2

2

C19

1

C20

AF1

R7
1K_0402_1%

0.1U_0402_16V4Z

2

1U_0402_6.3V4Z

1

1000P_0402_50V7K

VDD_VREF_SUS_CPU

LAYOUT:PLACE CLOSE TO CPU

Compal Secret Data

Security Classification
Issued Date

2005/10/11

Deciphered Date

2006/10/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

Size Document Number
Custom 401412
Date:

,

Rev
B

09, 2006

Sheet
E

6

of

55


4

3

2

1

ATHLON Control and Debug

+1.8V

1

LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.

R8

+2.5VS

1

1

C22

2
4.7U_0805_10V4Z

D

2

F8
F9

1

C23

2
0.22U_0603_10V7K

CPU_HT_RESET#
CPU_ALL_PWROK
CPU_LDTSTOP#

C24

3300P_0402_50V7K

R10 1

SB460 ONLY

R12
R13

+1.2V_HT

CPU_SIC_R

2 300_0402_5%
1
1

CPU_HTREF1
CPU_HTREF0

2 44.2_0603_1%
2 44.2_0603_1%

place them to CPU within 1"

1

+1.8VS

+1.8V

PAD
PAD

R15

1

5
P

2

3

A

C27 1

<15> CPUCLK#

G

1

<23> CPU_PWRGD

CPU_ALL_PWROK

4

Y

NC7SZ08P5X_NL_SC70-5

R806 1

VDDIOFB_H
VDDIOFB_L

T1
T2

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

2

3900P_0402_50V7K
R16
169_0402_1%

2

0.1U_0402_16V4Z

2

4.7K_0402_5%
U49

@
2 B

C25 1

<15> CPUCLK

C26
1

R14
300_0402_5%

2

+3VS

CPU_VCC_SENSE
CPU_VSS_SENSE

<54> CPU_VCC_SENSE
<54> CPU_VSS_SENSE

2

1

A

5

2

B

1

0.1U_0402_16V4Z

T13
T15
T17
T19
T20

CPU_LDTSTOP#

4

3

G

Y

PAD
PAD

T23
T25

PAD
PAD

T28
T30

CPU_THERMDC
CPU_THERMDA

NC7SZ08P5X_NL_SC70-5

2 @ 0_0402_5%

C29

AC6

CPU_PRESENT#

A3

PSI#

D

<54>
<54>
<54>
<54>

<54>
<54>

PSI# <54>

DBREQ_L

E10

CPU_DBREQ#

TDO

AE9

CPU_TDO

C9
C8

Place within 0.5" from CPU
25mil/6mil/6mil/6mil/25mil
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

TEST25_H
TEST25_L
TEST19
TEST18
TEST13

TEST9
TEST17
TEST16
TEST15
TEST14
TEST12

TEST29_H
TEST29_L

TEST24
TEST23
TEST22
TEST21
TEST20

AE7
AD7
AE8
AB8
AF7

T14 PAD
T16 PAD
T18 PAD
CPU_TEST21_SCANEN

C3
AA6
W7

W8
Y6
AB6

TEST7
TEST6
THERMDC
THERMDA
TEST3
TEST2

TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8

J7
H8
AF8
AE6
K8
C4

T24 PAD
T26 PAD
T27 PAD
CPU_TEST26_BURNIN#

P20
P19
N20
N19

RSVD0
RSVD1
RSVD2
RSVD3

RSVD8
RSVD9

H16
B18

RSVD10
RSVD11

B3
C1

RSVD12
RSVD13
RSVD14

H6
G6
D5

RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

R24
W18
R23
AA8
H18
H19

R17
1
2
80.6_0402_1%

ROUTE AS 80 Ohm DIFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"

T21 PAD

C

T29 PAD
T31 PAD

1

2

LDT_RST#

E

3

Q47
NC7SZ08P5X_NL_SC70-5

B

A

R845
@ 4.7K_0402_5%

@ 10K_0402_5%
CPU_HT_RESET#

4

R26
R25
P22
R22

2

Y

1

<22> LDT_RST#

0.1U_0402_16V4Z

P

B

R844

2

G

2

U51
2

5

1

VID5
VID4
VID3

VID2
VID1
VID0

E9
E8
G9
H10
AA7
C2
D7
E7
F7
C7
AC8

+3VS

1

+1.8V

R19
300_0402_5%

2

1

+1.8VS

PSI_L

VID5
VID4
VID3
VID2
VID1
VID0

A5
C6
A6
A4
C5
B5

CLKIN_H
CLKIN_L

TMS
TCK
TRST_L
TDI

PAD
PAD
PAD
PAD
PAD

VID5
VID4
VID3
VID2
VID1
VID0

AF6 H_THERMTRIP_S#
AC7 CPU_PROCHOT#_1.8

VDDIO_FB_H
VDDIO_FB_L

DBRDY

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

+1.8VS

0_0402_5% SB_PWROK_R

W9
Y9

THERMTRIP_L
PROCHOT_L

CPU_PRESENT_L

AA9
AC9
AD9
AF9

Modify 11/22

2

VDD_FB_H
VDD_FB_L

CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

2

R807 1

R8041

HTREF1
HTREF0

F6

E6

P

U50
2

P6
R6

A9
A8

C28

<13,23> LDT_STOP#

SIC
SID

G10

+1.8V
1

AF4
AF5

C PU_DBRDY

+1.8VS

R18
300_0402_5%

RESET_L
PWROK
LDTSTOP_L

3900P_0402_50V7K

2 @ 0_0402_5%

VDDA2
VDDA1

B7
A7
F10

2

+VDDA_25V

1

1

2

300_0402_5%

2

JP72D

50mil width(600mA)

FBM-L11-321611-260-LMT_1206

<23,42> SB_PWRGD

R9

300_0402_5%
L1

C

1

5

RSVD4
RSVD5
RSVD6
RSVD7

3V_LDT_RST#

C

3
1
@ MMBT3904_SOT23

R808 1

AMD NPT S1 SOCKET
Processor Socket

2 @ 0_0402_5%

1

+3VALW
1

+3VALW

Q1
3
1H_THERMTRIP#
MMBT3904_SOT23

3

Q2
@ MMBT3904_SOT23
1

MAINPWON <47,48,50>

+1.8V
1

H_THERMTRIP_S#

B

10K_0402_5%

H_THERMTRIP# <23>

R29
10K_0402_5%

+3VS

+1.8V

2 300_0402_5%

CPU_PRESENT#
R33
CPU_TEST25_H_BYPASSCLK_H R34

1
1

2 1K_0402_5%

2 510_0402_5%

CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST21_SCANEN

1
1
1
1

2
2
2
2

CPU_PROCHOT#_1.8

3
1
MMBT3904_SOT23

EC_THERM# <23,33>

C

1

E

R32

B

Q3
CPU_TEST26_BURNIN#

R30
4.7K_0402_5%
2

@ SAMTEC_ASP-68200-07

1

CPU_PH_G 2

3V_LDT_RST#

2

NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.

300_0402_5%

2
4
6

8
10
12
14
16
18
20
22
24
26

R23

2

1
3
5
7
9
11
13
15
17
19
21
23

R21
@ 1K_0402_5%

2

1K_0402_5%
R22

JP74

2

+1.8V

1

1

R20

2 2

+1.8V

2

R28 1@ 220_0402_5%

R27 1@ 220_0402_5%

R26 1@ 220_0402_5%

R25 1@ 220_0402_5%

+1.8V

HDT Connector

2

2

2

CPU_DBREQ#
C PU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

2

B

2

R24 1@ 220_0402_5%

+1.8V

+3VS
C30
0.1U_0402_16V4Z
1
2

C31
2200P_0402_50V7K
A

U4

1
1
2

CPU_THERMDA

2

CPU_THERMDC

3
4

SCLK

8

EC_SMB_CK2 <33>

D+

SDATA

7

EC_SMB_DA2 <33>

D-

ALERT#

6

GND

5

VDD

THERM#

R42
R43
R44
R35

510_0402_5%
300_0402_5%

300_0402_5%
300_0402_5%
A

ADM1032ARMZ-2REEL_MSOP8
F75383M_MSOP8

SMBus Address: 1001110X (b)

Compal Secret Data

Security Classification
Issued Date

2005/03/08

Deciphered Date

2006/03/08

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

Size
C

Document Number

Date:

,

Rev
B

401412
09, 2006

Sheet
1

7

of

55

5

4

3

2

1

D

D

BOTTOMSIDE DECOUPLING
+CPU_CORE

1
JP72F

C

+CPU_CORE
JP72E
AC4 VDD1
AD2 VDD2
G4 VDD3
H2 VDD4

J9 VDD5
J11 VDD6
J13 VDD7
K6 VDD8
K10 VDD9
K12 VDD10
K14 VDD11
L4 VDD12
L7 VDD13
L9 VDD14
L11 VDD15
L13 VDD16
M2 VDD17
M6 VDD18
M8 VDD19
M10 VDD20
N7 VDD21
N9 VDD22
N11 VDD23
P8 VDD24
P10 VDD25
R4 VDD26
R7 VDD27
R9 VDD28
R11 VDD29
T2 VDD30
T6 VDD31
T8 VDD32
T10 VDD33
T12 VDD34

T14 VDD35
U7 VDD36
U9 VDD37
U11 VDD38
U13 VDD39
V6 VDD40
V8 VDD41
V10 VDD42

AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11

AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4

F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4

+CPU_CORE
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54

V12

V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18

VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23

T25
U17
V18
V21
V23
V25
Y25

+1.8V

Athlon 64 S1
Processor Socket

B

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45

VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74

VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104

VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

2

J6
J8

J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7

P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21

Y23
N6

1

C32
10U_0805_10V4Z

2

1

C33
10U_0805_10V4Z

2

1

C34
10U_0805_10V4Z

2

1

C35
10U_0805_10V4Z

2

1

C36
10U_0805_10V4Z

+CPU_CORE

1

2

1

2

0.22U_0603_10V7K

0.01U_0402_16V7K

1

C37
22U_0805_6.3V6M

2

1

C38

22U_0805_6.3V6M

2

1

C39
22U_0805_6.3V6M

2

C40
22U_0805_6.3V6M

+1.8V

1

C41

C923

2

1

2

2

1

C42
0.22U_0603_10V7K

2

1

C43
0.22U_0603_10V7K

2

1

C44
0.22U_0603_10V7K

2

1
C45
22U_0805_6.3V6M

1
C46
22U_0805_6.3V6M

2

2

1

C47
0.22U_0603_10V7K

2

C48
0.22U_0603_10V7K

C924
180P_0402_50V8J
C

DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE
+1.8V

1

2

1

C49
4.7U_0805_10V4Z

2

1

C50
4.7U_0805_10V4Z

2

1

C51
4.7U_0805_10V4Z

2

1

C52
4.7U_0805_10V4Z

2

1

C53
0.22U_0603_10V7K

2

1

C54
0.22U_0603_10V7K

2

C55
0.22U_0603_10V7K

1
1

2

1

C56
0.22U_0603_10V7K

CPU

2

1

C57
0.01U_0402_16V7K

2

C58
0.01U_0402_16V7K

1

2

C59
180P_0402_50V8J

left-hand side

1

2

+ C795

C60
180P_0402_50V8J

2

220U_D2_4VM

CPU right-hand side

+0.9V

+0.9V
B

1

2

C61
4.7U_0805_10V4Z

1

2

1

C68
0.22U_0603_10V7K

2

1

C63
4.7U_0805_10V4Z

2

C65
0.22U_0603_10V7K

+CPU_CORE

1

1

+ C796

45@

1

+ C797

Athlon 64 S1
Processor Socket

1

+ C798

1

2

820U_E9_2.5V_M_R7

2

820U_E9_2.5V_M_R7

2

330U_D2E_2.5VM_R9

C69

1

1

C74

1

C71

C76

+ C799

45@
2

2

330U_D2E_2.5VM_R9

A1

1000P_0402_50V7K

2

180P_0402_50V8J

2

1000P_0402_50V7K

2

180P_0402_50V8J

A26

PROCESSOR POWER AND GROUND
Athlon 64 S1g1
uPGA638
Top View
A

A

AF1

Compal Secret Data

Security Classification

Issued Date

2005/03/08

Deciphered Date

2006/03/08

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

Size
C

Document Number

Date:

,

Rev
B

401412
09, 2006

Sheet
1

8

of

55


5

4

3

+1.8V

+1.8V

2

+DIMM_VREF

+1.8V
DDR_A_D[0..63]

DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11

4.7U_0805_10V4Z

2

1
1

2

+ C802
C88

C87

C86

2

220U_D2_4VM

2

1

2

1

2

1
1

+

2

C925
2

150U_D2_6.3VM

C103

C102

C101

C100

C99

C98

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

2
1

DDR_A_ODT0 <6>
+0.9V

DDR_CS3_DIMMA#

DDR_CS3_DIMMA# <6>

DDR_A_D36
DDR_A_D37

DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

R69
R70

1
1

2 47_0402_5%
2 47_0402_5%

DDR_A_D60
DDR_A_D61

DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

R71
R72
R73
R74

1
1
1
1

2
2
2
2

DDR_A_ODT1
DDR_A_ODT0

R75

R76

1
1

2 47_0402_5%
2 47_0402_5%

DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
R77
R78

1
1

2 10K_0402_5%
2 10K_0402_5%

2005/10/11

3

2

2

1

2

Layout Note:
Place one 0.1uF cap close to every 2 pullup
resistors terminated to +0.9V

47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
A

Compal Secret Data

Security Classification

2

1

C933

DDR_A_D54
DDR_A_D55

2

1

C932

2 47_0402_5%
2 47_0402_5%
2 47_0402_5%

2

1

0.1U_0402_16V4Z

1
1
1

DDR_A_CLK2 <6>
DDR_A_CLK#2 <6>

2

1

C931

R66
R67
R68

DDR_A_CLK2

DDR_A_CLK#2

2

1

0.1U_0402_16V4Z

DDR_A_DM6

DDR_A_CAS#
DDR_A_WE#
DDR_A_RAS#

DDR_A_D52
DDR_A_D53

+0.9V

1

C930

2 47_0402_5%
2 47_0402_5%
2 47_0402_5%

DDR_A_D46
DDR_A_D47

1

+1.8V
0.1U_0402_16V4Z

1
1
1

DDR_A_DQS#5
DDR_A_DQS5

11/3 Modify

C929

R63
R64
R65

DDR_A_D44
DDR_A_D45

0.1U_0402_16V4Z

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

DDR_A_D38

DDR_A_D39

B

C928

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_16V4Z

1
1
1
1
1

1
1
1
1
1
1
1
1
1
1
1

DDR_A_DM4

47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%

C927

R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62

0.1U_0402_16V4Z

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8

DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

2006/10/11

Deciphered Date

Title

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

4.7U_0805_10V4Z

2

1

C97

5

2

1

C

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

DDR_A_BS#1 <6>
DDR_A_RAS# <6>
DDR_CS0_DIMMA# <6>

Issued Date

P-TWO_A5692C-A0G16

C85

C104

4.7U_0805_10V4Z

1

2

1

C926

SB_CK_SDAT
SB_CK_SCLK
+3VS

2

0.1U_0402_16V4Z

<10,15,23> SB_CK_SDAT
<10,15,23> SB_CK_SCLK

1

0.1U_0402_16V4Z

DDR_A_D58

DDR_A_D59

2

1

0.1U_0402_16V4Z

A

2

1

C96

DDR_A_DM7

4.7U_0805_10V4Z

DDR_A_D56
DDR_A_D57

DDR_A_ODT0
DDR_A_MA13

2

1

C95

DDR_A_D50
DDR_A_D51

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

2

1

0.1U_0402_16V4Z

DDR_A_DQS#6
DDR_A_DQS6

2

C84

DDR_A_D48
DDR_A_D49

4.7U_0805_10V4Z

DDR_A_D42
DDR_A_D43

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

1

C94

DDR_A_DM5

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

0.1U_0402_16V4Z

DDR_A_D40
DDR_A_D41

C83

DDR_A_D34
DDR_A_D35

2

1

11/01 modify

DDR_CKE1_DIMMA <6>

DDR_A_MA15
DDR_A_MA14

C93

DDR_A_DQS#4
DDR_A_DQS4

1

+0.9V

0.1U_0402_16V4Z

B

2

C82

DDR_A_D32
DDR_A_D33

4.7U_0805_10V4Z

<6> DDR_A_ODT1

DDR_CKE1_DIMMA

C92

DDR_A_ODT1

DDR_A_D30
DDR_A_D31

0.1U_0402_16V4Z

DDR_A_CAS#
DDR_CS1_DIMMA#

DDR_A_DQS#3
DDR_A_DQS3

C91

<6> DDR_A_CAS#
<6> DDR_CS1_DIMMA#

2

1

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

DDR_A_D28

DDR_A_D29

C90

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

<6> DDR_A_BS#0
<6> DDR_A_WE#

2

1

DDR_A_D22
DDR_A_D23

C89

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

2

1

0.1U_0402_16V4Z

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_DM2

1

0.1U_0402_16V4Z

DDR_CS2_DIMMA#
DDR_A_BS#2

DDR_A_D20
DDR_A_D21

0.1U_0402_16V4Z

<6> DDR_CS2_DIMMA#
<6> DDR_A_BS#2

+1.8V

DDR_A_CLK1 <6>
DDR_A_CLK#1 <6>

DDR_A_D14
DDR_A_D15

0.1U_0402_16V4Z

<6> DDR_CKE0_DIMMA

DDR_CKE0_DIMMA

1K_0402_1%

C81

DDR_A_D26
DDR_A_D27

D

4.7U_0805_10V4Z

DDR_A_DM3

DDR_A_DQS#[0..7]

R46

4.7U_0805_10V4Z

C

DDR_A_MA[0..15]

<6> DDR_A_DQS#[0..7]

DDR_A_DM1
DDR_A_CLK1
DDR_A_CLK#1

DDR_A_DQS[0..7]

<6> DDR_A_MA[0..15]

C80

DDR_A_D24
DDR_A_D25

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74

76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134

136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194

196
198
200

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7

A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46

DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

DDR_A_D12
DDR_A_D13

1K_0402_1%

2

4.7U_0805_10V4Z

DDR_A_D18
DDR_A_D19

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2

VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS

DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

DDR_A_D6
DDR_A_D7

2

1

C79

DDR_A_DQS#2
DDR_A_DQS2

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79

81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139

141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DDR_A_DM0

1

4.7U_0805_10V4Z

DDR_A_D16
DDR_A_D17

DDR_A_D4
DDR_A_D5

R45

2

DDR_A_D2
DDR_A_D3

2
4
6
8
10
12
14
16
18
20

22
24
26
28
30
32
34
36
38
40

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15

VSS

4.7U_0805_10V4Z

DDR_A_DQS#0
DDR_A_DQS0

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

DDR_A_DM[0..7]

<6> DDR_A_DM[0..7]
<6> DDR_A_DQS[0..7]

C78

D

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

0.1U_0402_16V4Z

DDR_A_D0
DDR_A_D1

C77

1

<6> DDR_A_D[0..63]

JP1

1

2

Size Document Number
Custom 401412
Date:

,

Rev
B
Sheet

09, 2006
1

9

of

55


5

4

3

+1.8V

+1.8V

2

1

+DIMM_VREF
DDR_B_D[0..63]

<6> DDR_B_D[0..63]

DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

1

2

C116

4.7U_0805_10V4Z

2

C115

2

1

2

1

2

1

2

1

2

1

2

1

2
C131

C130

C129

C128

C127

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

1

+0.9V

DDR_CS3_DIMMB# <6>

DDR_B_D38
DDR_B_D39

2 47_0402_5%
2 47_0402_5%

R103
R104
R105
R106

DDR_B_D60
DDR_B_D61

2
2
2
2

DDR_B_DQS#7

DDR_B_DQS7

DDR_B_ODT1
DDR_B_ODT0

R107 1
R108 1

DDR_B_D62
DDR_B_D63

1
1
1
1

2

2

1

2
C941

R101 1
R102 1

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#

DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

2

1

C940

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB

2

1

0.1U_0402_16V4Z

DDR_B_D54
DDR_B_D55

2

1

C939

2 47_0402_5%
2 47_0402_5%
2 47_0402_5%

2

1

0.1U_0402_16V4Z

R98 1
R99 1
R100 1

2

1

C938

DDR_B_CAS#
DDR_B_WE#
DDR_B_RAS#

+0.9V

1

0.1U_0402_16V4Z

2 47_0402_5%
2 47_0402_5%
2 47_0402_5%

1

+1.8V

C937

1
1
1

11/3 Modify
0.1U_0402_16V4Z

R95
R96
R97

B

C936

DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0

DDR_B_DM6

47_0402_5%
47_0402_5%

47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%

C935

DDR_B_CLK2 <6>
DDR_B_CLK#2 <6>

2
2
2
2
2
2
2
2
2
2

2
2
2
2
2
2

C934

DDR_B_D52
DDR_B_D53

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0.1U_0402_16V4Z

DDR_B_D46
DDR_B_D47

R79
R80
R81
R82
R83
R84
R85
R86
R87
R88
R89
R90
R91
R92
R93
R94

0.1U_0402_16V4Z

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12

DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

0.1U_0402_16V4Z

DDR_B_D44
DDR_B_D45

2 10K_0402_5%
2 10K_0402_5%

2

DDR_B_ODT0 <6>

DDR_B_DM4

R109 1
R110 1

2

1

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

DDR_B_BS#1 <6>
DDR_B_RAS# <6>
DDR_CS0_DIMMB# <6>

DDR_B_D36
DDR_B_D37

DDR_B_CLK2
DDR_B_CLK#2

2

1

0.1U_0402_16V4Z

DDR_CS3_DIMMB#

2

1

Layout Note:
Place one 0.1uF cap close to every 2 pullup
resistors terminated to +0.9V

47_0402_5%
47_0402_5%
47_0402_5%
47_0402_5%
A

2 47_0402_5%
2 47_0402_5%

+3VS

Compal Secret Data

Security Classification
2005/10/11

2006/10/11

Deciphered Date

3

Title

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

4.7U_0805_10V4Z

DDR_B_ODT0
DDR_B_MA13

2

1

0.1U_0402_16V4Z

DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C114

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

1

C126

5

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

C125

2

DDR_CKE1_DIMMB <6>

DDR_B_MA15
DDR_B_MA14

Issued Date

P-TWO_A5652C-A0G16

2

1

C

0.1U_0402_16V4Z

C132

C113

1

4.7U_0805_10V4Z

SB_CK_SDAT
SB_CK_SCLK
+3VS

2

1

+0.9V

C124

<9,15,23> SB_CK_SDAT
<9,15,23> SB_CK_SCLK

1

0.1U_0402_16V4Z

DDR_B_D58
DDR_B_D59

4.7U_0805_10V4Z

DDR_B_DM7
A

DDR_CKE1_DIMMB

C123

DDR_B_D56
DDR_B_D57

2

0.1U_0402_16V4Z

DDR_B_D50
DDR_B_D51

1
C112

DDR_B_DQS#6

DDR_B_DQS6

4.7U_0805_10V4Z

DDR_B_D48
DDR_B_D49

DDR_B_D30
DDR_B_D31

C122

DDR_B_D42
DDR_B_D43

DDR_B_DQS#3
DDR_B_DQS3

0.1U_0402_16V4Z

DDR_B_DM5

2

C111

DDR_B_D40
DDR_B_D41

1

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

DDR_B_D28
DDR_B_D29

C121

DDR_B_D34
DDR_B_D35

2

0.1U_0402_16V4Z

DDR_B_DQS#4
DDR_B_DQS4

1
C110

DDR_B_D32
DDR_B_D33
B

4.7U_0805_10V4Z

<6> DDR_B_ODT1

2

C120

DDR_B_ODT1

1

0.1U_0402_16V4Z

DDR_B_CAS#
DDR_CS1_DIMMB#

2

C119

<6> DDR_B_CAS#
<6> DDR_CS1_DIMMB#

1

DDR_B_D22
DDR_B_D23

C118

DDR_B_MA10
DDR_B_BS#0

DDR_B_WE#

<6> DDR_B_BS#0
<6> DDR_B_WE#

2

C117

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_DM2

1

0.1U_0402_16V4Z

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DDR_B_D20
DDR_B_D21

0.1U_0402_16V4Z

DDR_CS2_DIMMB#
DDR_B_BS#2

+1.8V

DDR_B_CLK1 <6>
DDR_B_CLK#1 <6>

DDR_B_D14
DDR_B_D15

0.1U_0402_16V4Z

<6> DDR_CS2_DIMMB#
<6> DDR_B_BS#2

DDR_B_CLK1
DDR_B_CLK#1

0.1U_0402_16V4Z

<6> DDR_CKE0_DIMMB

DDR_CKE0_DIMMB

D

DDR_B_DM1

C109

DDR_B_D26

DDR_B_D27

DDR_B_DQS#[0..7]

DDR_B_D12
DDR_B_D13

4.7U_0805_10V4Z

DDR_B_DM3

DDR_B_MA[0..15]

<6> DDR_B_DQS#[0..7]

4.7U_0805_10V4Z

C

<6> DDR_B_DQS[0..7]
<6> DDR_B_MA[0..15]

C108

DDR_B_D24
DDR_B_D25

42
44
46

48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106

108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166

168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29

VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36

DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS

DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

DDR_B_DM[0..7]
DDR_B_DQS[0..7]

2

4.7U_0805_10V4Z

DDR_B_D18
DDR_B_D19

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24

DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS

DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57

VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

DDR_B_D6
DDR_B_D7

2

C107

DDR_B_DQS#2
DDR_B_DQS2

41
43
45
47
49
51
53
55
57
59

61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119

121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179

181
183
185
187
189
191
193
195
197
199

DDR_B_DM0

4.7U_0805_10V4Z

DDR_B_D16
DDR_B_D17

DDR_B_D4
DDR_B_D5

1

C106

DDR_B_DQS#0
DDR_B_DQS0

VSS
DQ4

DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

C105

D

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0

VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

1

0.1U_0402_16V4Z

DDR_B_D0
DDR_B_D1

2
4
6
8
10
12
14
16
18

20
22
24
26
28
30
32
34
36
38
40

4.7U_0805_10V4Z

JP2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

31
33
35
37
39

<6> DDR_B_DM[0..7]

2

Size Document Number
Custom 401412
Date:

,

Rev
B
Sheet

09, 2006
1

10

of

55

5

4

3

2

1

D

D

H_CADOP[0..15]
H_CADON[0..15]

H_CADOP[0..15] <5>
H_CADON[0..15] <5>

<5> H_CADIP[0..15]
<5> H_CADIN[0..15]

H_CADIP[0..15]
H_CADIN[0..15]

U58A
R19
R18
R21

R22
U22
U21
U18
U19
W19
W20
AC21
AB22
AB20
AA20
AA19
Y19

HT_RXCAD15P
HT_RXCAD15N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD8P
HT_RXCAD8N

H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

T24
R25
U25
U24
V23
U23
V24
V25
AA25
AA24
AB23
AA23

AB24
AB25
AC24
AC25

HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD0P
HT_RXCAD0N

<5> H_CLKOP1
<5> H_CLKON1

H_CLKOP1
H_CLKON1

W21
W22

HT_RXCLK1P
HT_RXCLK1N

<5> H_CLKOP0
<5> H_CLKON0

H_CLKOP0
H_CLKON0

Y24
W25

HT_RXCLK0P
HT_RXCLK0N

P24
P25

HT_RXCTLP
HT_RXCTLN

C

<5> H_CTLOP0
<5> H_CTLON0

B

+1.2V_HT

R111 1
R113 1

H_CTLOP0
H_CTLON0
2 49.9_0402_1%
2 49.9_0402_1%

HT_RXCALP
HT_RXCALN

A24
C24

PART 1 OF 5

HYPER TRANSPORT CPU
I/F

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11

H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8

HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N

P21
P22
P18
P19
M22
M21

M18
M19
L18
L19
G22
G21
J20
J21
F21
F22

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8

HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N

N24
N25
L25
M24
K25
K24
J23
K23
G25
H24
F25
F24
E23
F23
E24

E25

H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

HT_TXCLK1P
HT_TXCLK1N

L21
L22

H_CLKIP1
H_CLKIN1

H_CLKIP1 <5>
H_CLKIN1 <5>

HT_TXCLK0P
HT_TXCLK0N

J24
J25

H_CLKIP0
H_CLKIN0

H_CLKIP0 <5>
H_CLKIN0 <5>

HT_TXCTLP
HT_TXCTLN

N23
P23

HT_TXCALP
HT_TXCALN

C25
D24

HT_RXCALP
HT_RXCALN

C

H_CTLIP0
H_CTLIN0
HT_TXCALP
HT_TXCALN

H_CTLIP0 <5>
H_CTLIN0 <5>

B

1 R112
2
100_0402_1%

215NSA4ALA11FG RS485M_BGA465

A

A

Compal Secret Data

Security Classification
2005/03/08

Issued Date

2006/03/08

Deciphered Date

4

3

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

2

Size Document Number
Custom 401412
Date:

,

R ev
B
Sheet

09, 2006
1

11

of

55


5

4

2

PCIE_GTX_C_MRX_P[0..15]

<16> PCIE_GTX_C_MRX_P[0..15]

1

<16> PCIE_MTX_C_GRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]

<16> PCIE_GTX_C_MRX_N[0..15]

D

3

<16> PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
D

U58B

C

G5
G4
J8
J7
J4
J5
L8
L7
L4
L5
M8
M7
M4
M5
P8
P7
P4
P5
R4
R5

R7
R8
U4
U5
W4
W5
Y4
Y5
V9
W9
AB7
AB6

<39> PCIE_MRX_PTX_P0
<39> PCIE_MRX_PTX_N0

R114 1
R115 1

2 0_0402_5%
2 0_0402_5%

PCIE_MRX_PTX_P0_R
PCIE_MRX_PTX_N0_R

W11
W12

<36> PCIE_MRX_PTX_P1
<36> PCIE_MRX_PTX_N1

R116 1
R117 1

2 0_0402_5%
2 0_0402_5%

PCIE_MRX_PTX_P1_R
PCIE_MRX_PTX_N1_R

AA11
AB11

<22> A_MRX_STX_P0
<22> A_MRX_STX_N0
<22> A_MRX_STX_P1
<22> A_MRX_STX_N1
B

R214:

10KOhm FOR RS485
1.47KOhm FOR RS690

R213:

8.25KOhm FOR RS485
DNI FOR RS690

R118 1

R120 1

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N

GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

PART 2 OF 5

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P

GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

PCIE I/F GFX

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8

PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N

PCIE I/F GPP

2 0.1U_0402_16V7K

C136 1

2 0.1U_0402_16V7K

C138 1

2 0.1U_0402_16V7K

C140 1

2 0.1U_0402_16V7K

C142 1

2 0.1U_0402_16V7K

C144 1

2 0.1U_0402_16V7K

C146 1

2 0.1U_0402_16V7K

C148 1

2 0.1U_0402_16V7K

C150 1

2 0.1U_0402_16V7K

C152 1

2 0.1U_0402_16V7K

C154 1

2 0.1U_0402_16V7K

C156 1

2 0.1U_0402_16V7K

C158 1

2 0.1U_0402_16V7K

C160 1

2 0.1U_0402_16V7K

C162 1

2 0.1U_0402_16V7K

C164 1

2 0.1U_0402_16V7K

GPP_TX0P
GPP_TX0N

C165 1

2 0.1U_0402_16V7K

GPP_TX1P
GPP_TX1N

AD7 PCIE_MTX_PRX_P1
AE7 PCIE_MTX_PRX_N1

C167 1

2 0.1U_0402_16V7K

GPP_RX2P
GPP_RX2N

GPP_TX2P
GPP_TX2N

AD4
AE5

AB9
AA9

GPP_RX3P
GPP_RX3N

GPP_TX3P
GPP_TX3N

AD5

AD6

A_MRX_STX_P0
A_MRX_STX_N0

W14
W15

SB_RX0P
SB_RX0N

A_MRX_STX_P1
A_MRX_STX_N1

AB12
AA12

SB_RX1P
SB_RX1N

AA14
AB14

PCEH_ISET
PCEH_TXISET

2 10K_0402_1%
2 8.25K_0402_1%

C134 1

AD8 PCIE_MTX_PRX_P0
AE8 PCIE_MTX_PRX_N0

Y7
AA7

PCIE I/F SB

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P10

PCIE_MTX_GRX_N10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15

J1
H2
K2
K1
K3
L3
L1
L2
N2
N1
P2
P1
P3
R3
R1
R2
T2
U1

V2
V1
V3
W3
W1
W2
Y2
AA1
AA2
AB2
AB1
AC1
AE3
AE4

SB_TX0P
SB_TX0N

AE9 A_MTX_SRX_P0
AD10 A_MTX_SRX_N0

C169 1

2 0.1U_0402_16V7K

SB_TX1P
SB_TX1N

AC8 A_MTX_SRX_P1
AD9 A_MTX_SRX_N1

C171 1

2 0.1U_0402_16V7K

PCEH_PCAL
PCEH_NCAL

AD11
AE11

215NSA4ALA11FG RS485M_BGA465

R119 1
R121 1

2
2

150 Ohm FOR RS485
562 Ohm FOR RS690

R121:

100 Ohm FOR RS485
2KOhm FOR RS690

2 0.1U_0402_16V7K

C135 1

2 0.1U_0402_16V7K

C137 1

2 0.1U_0402_16V7K

C139 1

2 0.1U_0402_16V7K

C141 1

2 0.1U_0402_16V7K

C143 1

2 0.1U_0402_16V7K

C145 1

2 0.1U_0402_16V7K

C147 1

2 0.1U_0402_16V7K

C149 1

2 0.1U_0402_16V7K

C151 1

2 0.1U_0402_16V7K

C153 1

2 0.1U_0402_16V7K

C155 1

2 0.1U_0402_16V7K

C157 1

2 0.1U_0402_16V7K

C159 1

2 0.1U_0402_16V7K

C161 1

2 0.1U_0402_16V7K

C163 1

2 0.1U_0402_16V7K

C166 1

2 0.1U_0402_16V7K

PCIE_MTX_C_PRX_P0
PCIE_MTX_C_PRX_N0

PCIE_MTX_C_PRX_P0 <39>
PCIE_MTX_C_PRX_N0 <39>

C168 1

2 0.1U_0402_16V7K

PCIE_MTX_C_PRX_P1
PCIE_MTX_C_PRX_N1

PCIE_MTX_C_PRX_P1 <36>
PCIE_MTX_C_PRX_N1 <36>

C170 1

2 0.1U_0402_16V7K

A_MTX_C_SRX_P0
A_MTX_C_SRX_N0

A_MTX_C_SRX_P0 <22>
A_MTX_C_SRX_N0 <22>

2 0.1U_0402_16V7K

A_MTX_C_SRX_P1
A_MTX_C_SRX_N1

A_MTX_C_SRX_P1 <22>
A_MTX_C_SRX_N1 <22>

C172 1

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10

PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

C

B

150_0402_1%
100_0402_1%

R119:

C133 1

+1.2V_HT

ATI side check , use +1.2V or not

A

A

Compal Secret Data

Security Classification
2005/03/08

Issued Date

2006/03/08

Deciphered Date

4

3

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

2

Size Document Number

Custom 401412
Date:

,

R ev
B
Sheet

09, 2006
1

12

of

55


5

4

3

2

1

ATI check , CRT / TV/ LVDS can delete or not when I use RX485

D

D

Modify 11/29

U58C

@ 1U_0402_6.3V4Z
+1.8VS
+1.8VS

2

R847
2 0_0603_5%
1
C948

1

PLLVDD
L63

@ 1U_0402_6.3V4Z

1
2
MBK1608800YZF_0805 1

C173

2

1

2

2
C174
4.7U_0805_10V4Z

10U_0805_10V4Z

Modify : 11/07

+1.8VS
HTPVDD

C

1

C176
4.7U_0805_10V4Z

1

HTPVDD

<16,22,27,33,36,41> NB_RST#
Q4
<42> NB_PWRGD
3
1
<22> ALLOW_LDTSTOP
MMBT3904_SOT23
E

2
10U_0805_10V4Z

R125
1K_0402_5%

B

2

C175

2

MBK1608800YZF_0805 1

Modify : 11/07

PLLVDD

R810

10K_0402_5%

2

2 2

1

+3VS

1

L67

R126 1

0_0402_5%
2
LDT_STOP#_NB

C

<7,23> LDT_STOP#

R127 2

1 10K_0402_5%

<15> HTREFCLK

<15> NB_OSC

LOAD_ROM#: LOAD ROM STRAP ENABLE

AVDDQ
AVSSQ

C21
C20
D19

C_R
Y_G
COMP_B

E19
F19
G19
C6
A5

RED
GREEN
BLUE
DACVSYNC
DACHSYNC

A10
B10

PLLVDD
PLLVSS

B24
B25

HTPVDD
HTPVSS

C10
C11
C5
B5

SYSRESET#
POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP

C23
B23

HTTSTCLK
HTREFCLK

C2

TVCLKIN

B11

A11

OSCIN
OSCOUT
GFX_CLKP
GFX_CLKN

G1
G2

SB_CLKP
SB_CLKN

D6
D7
C8
C7
B8
A8

DFT_GPIO0
DFT_GPIO1
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

R128 1
2
@ 3K_0402_5%

R130
R131
R132
R133

2 @ 2.7K_0402_5%

1
1
1
1

2
2
2
2

@ 2.7K_0402_5%
@ 2.7K_0402_5%
@ 2.7K_0402_5%
@ 2.7K_0402_5%

2

1N4148_SOT23
PAD T11
PAD T7

PAD

PAD

T8
T9

PAD

T10

B2
A2
B4
AA15
AB15
C14
B3
C3
A3

B14
B15
B13
A13
H14
G14
D17
E17

TXOUT_U0P
TXOUT_U0N

TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

A15
B16
C17
C18
B17
A17
A18
B18

TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN

E15
D15
H15
G15

LPVDD
LPVSS

D14

E14

LVDDR18D_1
LVDDR18D_2
LVDDR18A_1
LVDDR18A_2

A12
B12
C12
C13

LVSSR1
LVSSR3
LVSSR5
LVSSR6
LVSSR7
LVSSR8

A16
A14
D12
C19
C15
C16

LVSSR12
LVSSR13

F14

F15

LVDS_DIGON
LVDS_BLON
LVDS_BLEN

E12
G12
F12

DVO_D0
DVO_D1
DVO_D2
DVO_D3
DVO_D4
DVO_D5
DVO_D6
DVO_D7
DVO_D8
DVO_D9
DVO_D10
DVO_D11

AD14
AD15
AE15
AD16
AE16
AC17
AD18

AE19
AD19
AE20
AD20
AE21

DVO_VSYNC
DVO_DE
DVO_HSYNC
DVO_IDCKP
DVO_IDCKN

AD13
AC13
AE13
AE17
AD17

BMREQb
I2C_CLK
I2C_DATA
THERMALDIODE_P
THERMALDIODE_N
TMDS_HPD
DDC_DATA
TESTMODE
STRP_DATA

Modify 11/29

+1.8VS
R848
1
1

2

2
0_0603_5%

C949
@ 1U_0402_6.3V4Z
C

+1.8VS
R849
1

2
0_0603_5%
R850
1
2
0_0603_5%

C950
@ 1U_0402_6.3V4Z

T4
T5

T6

1

1

2

2

C951
@ 1U_0402_6.3V4Z

PAD
PAD
PAD

B

1

<22> BMREQ#

1D33

DFT_GPIO0
LOAD_ROM#
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4

DFT_GPIO5

TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

DACSCL
DACSDA

<15> SBLINK_CLKP
<15> SBLINK_CLKN
1

PART 3 OF 5

RSET

F2
E1

Low, LOAD ROM STRAP ENABLE

B

A21

A22

<15> NBSRC_CLKP
<15> NBSRC_CLKN

R129

High, LOAD ROM STRAP DISABLE

AVDD1
AVDD2
AVSSN1
AVSSN2
AVDDDI
AVSSDI

B21
2
@ 715_0402_1%
B6
A6

1
R123
+1.8VS

B22
C22
G17
H17

A20
B20

CRT/TVOUT

2
0_0603_5%

PM PLL PWR

1
R809

+3VS

CLOCKs

R846
2 0_0603_5%
1
C947

1

MIS.

+1.8VS

R134
4.7K_0402_5%

2

215NSA4ALA11FG RS485M_BGA465

A

A

Compal Secret Data

Security Classification
2005/03/08

Issued Date

2006/03/08

Deciphered Date

4

3

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

Title

2

Size Document Number
Custom 401412
Date:

,

R ev
B
Sheet

09, 2006
1

13

of

55


5

4

3

2

1

NB RS485 POWER STATES

D

Power Signal

S0

S1

S3

VDDHT

ON

ON

OFF OFF

S4/S5

G3
OFF

VDDR

ON

ON

OFF OFF

OFF

VDD18

ON

ON

OFF OFF

OFF

VDDC

ON

ON

OFF OFF

OFF

VDDA18

ON

ON

OFF OFF

OFF

VDDA12

ON

ON

OFF OFF

OFF

AVDD

ON

ON

OFF OFF

OFF

AVDDDI

ON

ON

OFF OFF

OFF

PLLVDD

ON

ON

OFF OFF

OFF

HTPVDD

ON

ON

OFF OFF

OFF

VDDR3

ON

ON

OFF OFF

OFF

LPVDD

ON

ON

OFF OFF

OFF

LVDDR18D

ON

ON

OFF OFF

OFF

LVDDR18A

ON

ON

OFF OFF

OFF

D

U58E

+1.2V_HT

+VDDA_12

C

+VDD_HT
2
1

U58D

10U_0805_10V4Z
1
1

C183
C184
C185

1

C186

1

1

C187

C188

1

KC FBM-L11-201209-221LMAT_0805
2
2

2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
10U_0805_10V4Z

1U_0402_6.3V4Z
1U_0402_6.3V4Z
VDD18

+1.8VS
L2
1
2
MBK1608800YZF_0805

1

RS690: VDDA18=1.2V
RS485: VDDA18=1.8V

2

1

C190
2.2U_0603_6.3V6K

2

AE24
AD24
AD22
AB17
AE23
Y17

W17
AC18
AD21
AC19
AC20
AB19
AD23
AA17
AE25

C189
1U_0402_6.3V4Z

C191
2.2U_0603_6.3V6K

+1.8VS

J14
J15

VDDA18
L64
1

3A bead
2

KC FBM-L11-201209-221LMAT_0805
10U_0805_10V4Z

+3VS

1

C198

2

1

C199

1

C200

1

C201

1

C202

1

C203

1

C204

2
2
2
2
2
2
10U_0805_10V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z
VDDR3 1U_0402_6.3V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z

L3
1
2
MBK1608800YZF_0805

1

B

2

C208

+1.8VS

VDDR

L4
1
2
MBK1608800YZF_0805
@

1U_0402_6.3V4Z

+VDDA_12

1

2

C209

1

2
2
@ 1U_0402_6.3V4Z
@ 1U_0402_6.3V4Z

4.7U_0805_10V4Z

Modify 11/07 for EMI

C213

1

E11
D11

VDDR3_2
VDDR3_1

+1.2V_HT

D22
M1
AC11

+1.2V_HT
+1.2V_HT
+1.2V_HT

1

1

VDDA18_1
VDDA18_2
VDDA18_3
VDDA18_4
VDDA18_5
VDDA18_6
VDDA18_7
VDDA18_8

E7
F7
F9
G9

1
C210 C211

2

L69

4 OF 5 VDDA_12_1
VDDA_12_2
VDDA_12_3
VDDA_12_4
VDDA_12_5
VDDA_12_6
VDDA_12_7
VDDA_12_8
VDDA_12_9
VDDA_12_10
VDDA_12_11
VDDA_12_12

VDD18_1
VDD18_2

AE2
AB3

U7
W7
AB4
AC3
AD2
AE1

AC12
AD12
AE12

4.7U_0805_10V4Z

VDD_HT1 PART
VDD_HT2
VDD_HT5
VDD_HT6
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15
VDD_HT16
VDD_HT17
VDD_HT18
VDD_HT19

POWER

+1.2V_HT
L70
1

VDDR_1
VDDR_2
VDDR_3
VDDA12/VDDPLL_1
VDDA12/VDDPLL_2
VSSA12/VSSPLL_1
VSSA12/VSSPLL_2
VDDHT_PKG
VDDA12_PKG1
VDDA12_PKG2

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14

VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32

D1
G7
E2
C1
E3
D2
M9
F4
B1
D3
L9

E6
L11
L13
L15
M12
R15
M14
N11
N13
N15
J11
H11
P12
P14
R11
R13
A19
B19
U11
U14
P17
L17
J19
D20
G20
A9
B9
C9
D9
A7

A4
U12
U15

1U_0402_6.3V4Z 10U_0805_10V4Z
1
1
1
1
C178
C179
C180
C181
2
2
1U_0402_6.3V4Z

1
1

C182

2

KC FBM-L11-201209-221LMAT_0805

2
2
2
1U_0402_6.3V4Z

10U_0805_10V4Z

+1.2V_HT
10U_0805_10V4Z
1U_0402_6.3V4Z
1
1
1
1
1
C192
C193
C194
C195
C196
2
10U_0805_10V4Z
1

2

2
2
1U_0402_6.3V4Z
1

C205

1

1

2
2
1U_0402_6.3V4Z
C206

1

C197
1U_0402_6.3V4Z

C207

+ C803
2

220U_D2_4VM

2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z

215NSA4ALA11FG RS485M_BGA465

C212
10U_0805_10V4Z

C214

Close to U58.M1
2

2

1U_0402_6.3V4Z

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20

VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50

VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59

PAR 5 OF 5

GROUND

CURRENT MEASUREMENT

A25
F11
D23
E9
G11
Y23
P11
R24
AE18
M15
J22
G23
J12
L12

L14
L20
L23
M11
M20
M23
M25
N12
N14
B7
L24
P13
P20
P15
R12
R14
R20
W23
Y25
AD25
U20
H25
W24
Y22
AC23
D25
G24
AC14
H12
AC22

R23
C4
AE22
T23
T25
AE14
R17
H23
M17
A23
AC15
F17
D4
AC16
M13

VSSA1
VSSA2
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
VSSA8
VSSA9
VSSA10
VSSA11
VSSA12
VSSA13
VSSA14

VSSA15
VSSA16
VSSA17
VSSA18
VSSA19
VSSA20
VSSA21
VSSA22
VSSA23
VSSA24
VSSA25
VSSA26
VSSA27
VSSA28
VSSA29
VSSA30
VSSA31
VSSA32
VSSA33
VSSA34
VSSA35
VSSA36
VSSA93
VSSA94
VSSA95
VSSA37
VSSA38
VSSA39
VSSA40
VSSA41

VSSA42
VSSA43
VSSA44
VSSA45

M3
V12
V11
V14
F3
V15
A1
H1
G3
J2
H3
AE10
J6
AE6
F1
L6
M2
M6
J3
P6
T1
N3
P9
R6
U2

T3
U3
U6
AC4
Y1
Y15
W6
AC2
Y3
Y9
Y11
Y12
Y14
AA3
R9
AD1
AC5
AC6
AC7
AD3
AC9
AC10
G6

C

B

215NSA4ALA11FG RS485M_BGA465

RS485: 0 Ohm RESISTOR
RS690: 220 Ohm 500mA FERRITE BEAD
A

A

Compal Secret Data

Security Classification
2005/03/08

Issued Date

2006/03/08

Deciphered Date

4

3

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

2

Size Document Number
Custom 401412
Date:

,

R ev
B
Sheet

09, 2006
1

14

of

55


5

4

3

2

1

+3VS
CLK_VDD
L5
1
2
MBK2012121YZF_0805

1

10U_0805_10V4Z
1
C215
C216

1

1

C217

1

C218

1

C219

1

C220

1

C221

C222

1

2
2

2

2

2

2

2

2

2

2
1

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

D

+3VS
L6
1
2
MBK2012121YZF_0805

CLK_VDDA

C223

1

C224
0.1U_0402_16V4Z

2

C225
10U_0805_10V4Z
D

+3VS
L7
1
2
MBK2012121YZF_0805
1
C226

U8

R173
475_0402_1%
1

Voh = 0.71V @ 60 ohm

IREF

57
32
33

R158 1
R171 1

48MHz_1
48MHz_0

7
6

CLK_48M_SIO_R
CLK_48M_USB_R

FS1/REF1
FS0/REF0
FS2/REF2
HTTCLK0

63
64
62
59

2 33_0402_1%
2 33_0402_1%

<36,39> ICH_SMBDATA
<36,39> ICH_SMBCLK

2

0_0402_5% SB_CK_SDAT

ICH_SMBCLK

R193 1

2

0_0402_5% SB_CK_SCLK

R177

R180 1
R182 1
R184 1

2 8.2K_0402_5%
2 8.2K_0402_5%
2 8.2K_0402_5%

2 49.9_0402_1%

2 49.9_0402_1%

2 49.9_0402_1%

1 R168

1 R169

1 R170

2 49.9_0402_1%

R178

R179

2.2K_0402_5%

2.2K_0402_5%
R181 2
R183 2
R185 2

SB_OSCIN_R

R186 1

2 33_0402_1%

SB_OSCIN <23>

FS0

R187 1

2 33_0402_1%

CLK_14M_SIO <41>

NB_OSCIN_R

R188 1

2 33_0402_1%

NB_OSC <13>

HTREFCLK_R

R190 1

2 33_0402_1%

HTREFCLK <13>

1 @ 0_0402_5%
1 @ 0_0402_5%
1 @ 0_0402_5%

B

1

B

R192 1

CLK_SD_48M <37>
CLK_USB_48M <23>

C

2.2K_0402_5%

CLK_VDD
R175 1
R176 1

ICS951462AGLFT_TSSOP64
ICH_SMBDATA

EXP_CLKREQ# <39>
MINI1_CLKREQ# <36>

2 49.9_0402_1%

0_0402_5%
0_0402_5%

1 R167

2
2

SBSRC_CLKP <22>
SBSRC_CLKN <22>
CLK_PCIE_CARD <39>
CLK_PCIE_CARD# <39>
CLK_PCIE_MINI1 <36>
CLK_PCIE_MINI1# <36>

1

Ioh = 5 * Iref
(2.32mA)

2

48

CLKREQA#
CLKREQB#
CLKREQC#

33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%

2

SMBCLK
SMBDAT

2
2
2
2

2
2

2 49.9_0402_1%

9
10

1
1
1
1
1
1

1 R166

SB_CK_SCLK
SB_CK_SDAT

R149
R150
R151
R152
R155
R156

1 R165

C230

0.1U_0402_16V4Z
@
<9,10,23> SB_CK_SCLK
<9,10,23> SB_CK_SDAT

SBLINK_CLKP <13>
SBLINK_CLKN <13>
NBSRC_CLKP <13>
NBSRC_CLKN <13>
CLK_PCIE_VGA <16>
CLK_PCIE_VGA# <16>

1

2

33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%
33_0402_1%

2

RESET_IN#
NC

1

2
2
2
2
2
2

1

11
61

1
1
1
1
1
1

2

X2

SBSRC_CLKP_R
SBSRC_CLKN_R
GPP_CLK4P_R
GPP_CLK4N_R
GPP_CLK0P_R
GPP_CLK0N_R

R142
R143
R144
R145
R146
R147

2 49.9_0402_1%

4

SBLINK_CLKP_R
SBLINK_CLKN_R
NBSRC_CLKP_R
NBSRC_CLKN_R
GFX_CLKP_R
GFX_CLKN_R

2 49.9_0402_1%

1

1 0_0402_5%

2

R153
10K_0402_5%

X1

16
17
41
40
37
36
35
34
30
31
18
19
20
21
24
25
26
27
47
46
43
42
12
13

CPUCLK <7>
CPUCLK# <7>

1 R164

2

1
C

33P_0402_50V8J
1M_0402_5%
R154 2
1
2
C229
14.31818MHz_20P_1BX14318BE1A

3

SRCCLKT6
SRCCLKC6
ATIGCLKT0
ATIGCLKC0
ATIGCLKT1
ATIGCLKC1
ATIGCLKT2
ATIGCLKC2
ATIGCLKT3
ATIGCLKC3
SRCCLKT5
SRCCLKC5
SRCCLKT4
SRCCLKC4

SRCCLKT3
SRCCLKC3
SRCCLKT2
SRCCLKC2
SRCCLKT0
SRCCLKC0
SRCCLKT1
SRCCLKC1
SRCCLKT7
SRCCLKC7

2 47_0402_1%
2 47_0402_1%

2 49.9_0402_1%

R148
@

Y1

CPUCLK_EXT_R R140 1
CPUCLK#_EXT_R R141 1

1 R163

2

2

33P_0402_50V8J

1

C228 1
CLK_VDD

56
55
52
51

2 49.9_0402_1%

Parallel Resonance Crystal

GNDCPU
GNDSRC
GNDSRC
GNDSRC
GNDSRC
GND48
GNDATIG
GNDREF
GNDHTT

CPUCLK8T0
CPUCLK8C0
CPUCLK8T1
CPUCLK8C1

1 R162

2

53
15
22
29
45
8
38
1
58

50
49

2 49.9_0402_1%

2.2U_0603_6.3V6K

R139
261_0402_1%
1
2

VDDA
GNDA

1 R161

2
L8
1
2
MBK2012121YZF_0805
1
C227

VDDCPU
VDDSRC
VDDSRC
VDDSRC
VDDSRC
VDD48
VDDATIG
VDDREF
VDDHTT

2 49.9_0402_1%

+3VS 2.2U_0603_6.3V6K

54
14
23
28
44
5

39
2
60

1 R160

2- PUT DECOUPLING CAPS CLOSE TO U800
POWER PIN

CLK_VDD

1 R159

1- PLACE ALL SERIAL TERMINATION
RESISTORS CLOSE TO U800

2

R191
51.1_0402_1%

EXT CLK FREQUENCY SELECT TABLE(MHZ)

A

FS2 FS1 FS0

CPU

SRCCLK

[2:1]

0

0

0

Hi-Z

100.00

0

0

1

X

100.00

0

1

0

180.00

100.00

0

1

1

220.00

100.00

1

0

0

100.00

1

0

1

1

1

1

COMMENT

PCI

USB

Hi-Z

Hi-Z

48.00

Reserved

X/3

X/6

48.00

Reserved

60.00

30.00

48.00

Reserved

36.56

73.12

48.00

Reserved

100.00

66.66

33.33

48.00

Reserved

133.33

100.00

66.66

33.33

48.00

Reserved

200.00

100.00

66.66

33.33

48.00

Normal ATHLON64 operation

5

HTT

A

Compal Secret Data

Security Classification
2005/03/08

Issued Date

4

2006/03/08

Deciphered Date

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

2

Size Document Number
Custom 401412
Date:

,

R ev
B
Sheet

09, 2006
1

15

of

55


5

4

3

U9A

D

C2321

2 0.1U_0402_16V7K
C2311
2 0.1U_0402_16V7K
C2331
2 0.1U_0402_16V7K
C2351
2 0.1U_0402_16V7K
C2371
2 0.1U_0402_16V7K
C2391
2 0.1U_0402_16V7K
C2411

2 0.1U_0402_16V7K
C2431
2 0.1U_0402_16V7K
C2451
2 0.1U_0402_16V7K
C2471
2 0.1U_0402_16V7K
C2491
2 0.1U_0402_16V7K
C2521
0.1U_0402_16V7K
2
C2541
2 0.1U_0402_16V7K
C2561
0.1U_0402_16V7K
2
C2581
2 0.1U_0402_16V7K
C2601
0.1U_0402_16V7K
2
C2621

C2341
C2361
C2381
C2401
C2421
C2441

C2461
C2481
C2511
C2531
C2551
C2571
C2591
C2611
C2631

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

C

PCIE_GTX_C_MRX_P[0..15]

<12> PCIE_GTX_C_MRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15]

<12> PCIE_GTX_C_MRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]

<12> PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]

<12> PCIE_MTX_C_GRX_N[0..15]

+3VS
+3VS

2

1

Thermal sensor
R210
2.2K_0402_5%
THM@

1

VDD

2

D+

SCLK

8

SDATA

7

THERM_SDA

2

D+
DC264
1
2

B

R211
THERM_SCL

3

D-

4

OVERT#

6

ALERT#

1
R212

2
0_0402_5%
THM@

5

GND

1

U10

2.2K_0402_5%
THM@
THER_ALERT#

AL28
AK28

PCIE_REFCLKP
PCIE_REFCLKN

PCIE_GTX_MRX_N15
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N10
PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N8
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N7
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N5
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N4
PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N3
PCIE_GTX_MRX_P3

PCIE_GTX_MRX_N2
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_P0

AK27
AJ27
AJ25
AH25
AH28
AG28
AG27
AF27
AF25
AE25
AE28
AD28
AD27
AC27
AC25
AB25
AB28
AA28
AA27
Y27
Y25
W25
W28

V28
V27
U27
U25
T25
T28
R28
R27
P27

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N

PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N7

PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P0

AJ31
AH31
AH30
AG30
AG32
AF32
AF31
AE31
AE30
AD30
AD32
AC32
AC31
AB31

AB30
AA30
AA32
Y32
Y31
W31
W30
V30
V32
U32
U31
T31
T30
R30
R32
P32
P31
N31

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P

PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N

+1.2VS

R2211

U11

REF

5

1

XIN MODOUT

4

8

XOUT

NC

3

PD#

6

VDD

Memory Interface SS

1
R226

2 OSC_SPREAD
22_0402_5%
SSC@

R2241
R2251

4.7K_0402_5%
2
2
4.7K_0402_5%

OSC_IN 1
R227

AG12

DPLUS

D-

AH12

DMINUS

AE12
AF12

DDC3DATA
DDC3CLK

THERM_SDA
THERM_SCL

2

2

2
121_0402_1%

VSS

1
1K_0402_5%
2

R230

1
2
C266
0.1U_0402_16V4Z
X1
4 VDD
OUT
1

OE

GND
27MHZ_15P

5

XTALIN
XTALOUT

R198 1

2@ 10K_0402_5%

NC_DVOVMODE_0
NC_DVOVMODE_1

AK4
AL4

DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10

DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

AF2
AF1
AF3
AG1
AG2
AG3
AH2
AH3
AJ2
AJ1
AK2
AK1
AK3
AL2
AL3
AM3

AE6
AF4
AF5
AG4
AJ3
AH4
AJ4
AG5
AH5
AF6
AE7
AG6

MEMID0
MEMID1
MEMID2
TP4

AK24
AM24
AL24

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

AJ23
AJ22

CRT_HSYNC

CRT_VSYNC

CRT

R
G
B
HSYNC
VSYNC

R199 1
TP1
R200 1
R201 1
R202 1

@ 2 10K_0402_5%
@ 2 10K_0402_5%
X76@ 2 10K_0402_5%
X76@ 2 10K_0402_5%

POWER_SEL
OSC_SPREAD
THER_ALERT#
R203 2
R204 1

XTAL

GPIO[1]

0: TX de-emphasis disable
1: TX de-emphasis enable

Debug Access

GPIO[4]

0: OFF Pad must be available
1: ON

PLL_IBIAS_RD

GPIO[6,5] Default : 01

ROM ID Config

GPIO[9,
13:11]

000X: No ROM,
AP_SIZE=00 128M share
Memory
001X: No ROM,
AP_SIZE=01 256M share
Memory
010X: No ROM,
AP_SIZE=10 64M share
Memory
011X: No ROM,

AP_SIZE=11 Reserved

D

C

+3VS
TP2
TP3

R2051
R2061
R207 1
R208 1
R209 1

2 4.7K_0402_5%
2 4.7K_0402_5%
I2C_DAT
I2C_CLK
2 10K_0402_5% X76@
2 10K_0402_5% X76@
10K_0402_5%
X76@
2

CRT_HSYNC <28>
CRT_VSYNC <28>

2 4.7K_0402_5%

2 4.7K_0402_5%

Need Level Shift

+3VS

GENERICA
GENERICB

AK22
AF23

GENERICA NC,GENERICB Grounded -->Internal SS
R216 2
1K_0402_5%
LVDS Bus
1

RSET

AL22

R219 2

499_0402_1%

1

R2
G2

B2

AK15
AM15
AL15

H2SYNC
V2SYNC

AF15
AG15

Y
C
COMP

AJ15
AJ13
AH15

VGA_TV_Y
VGA_TV_C
VGA_TV_COMP

R2SET

AK14

R223 2

R228 2

I2C_DAT <29>
I2C_CLK <29>
+3VS

VGA_CRT_R <28>
VGA_CRT_G <28>
VGA_CRT_B <28>

VGA_CRT_DAT
VGA_CRT_CLK

AG14
AG22

Transmitter
de-emphasis enable

POWER_SEL <53>

AH22
AH23

PLLTEST
TESTEN

0: 50% TX output swing
1: Full TX output swing

Low -> VDDC=1.2V
High -> VDDC=1.0V

DDC1DATA
DDC1CLK

ROMCS#

GPIO[0]

+3VS
499_0402_1%
1
499_0402_1%
2
C250 1
2
0.1U_0402_16V4Z

R2131
R2141

AC7

Transmitter power
saving enable

1

VGA_CRT_DAT <28>

VGA_CRT_CLK <28>

B

Vedio Memory Config. (VGA Internal PD)
MEMID[2:0] Size

VGA_TV_Y <28>
VGA_TV_C <28>
VGA_TV_COMP <28>
715_0402_1%

1

Need Level Shift

0
0
0
0
1
1
1
1

0
0
1
1
0

0
1
1

0
1
0
1
0
1
0
1

Size

Vender Chips VGA

64MB

16M16

64MB

16M16 Samsung

128MB 16M16

Hynix

Frequence

2

Hynix

2
4

128MB 16M16 Samsung

4

256MB 32M16

4

Hynix

256MB 32M16 Samsung

A-test
A-test

4

Resreved
Resreved

1K_0402_5%

R229

ASM3P1819N-SR_SO8
SSC@
Minimize distance from X1 pin3 to U3 pin1

M56P
M56@

71.5_0402_1%

A

2

+3VS

AL26
AM26

2@ 10K_0402_5%
2 10K_0402_5%

AC8

TV

D+

1

1
C265
SSC@

PCIE_TEST
PERST#_MASK

+3VS

7

0.1U_0402_16V4Z

PERST#

AA24
AF24

Spread spectrum

R222

0_0603_5%
2
1

SSC@

+3VS

AG24

2 10K_0402_5%

R196 1
R197 1

VREFG

PCIE_CALRN
PCIE_CALRP
PCIE_CALI

2 0_0402_5%

2 10K_0402_5%
2 10K_0402_5%

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7_BLON
GPIO_8
GPIO_9
GPIO_10

GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
NC

GPIO

THERMAL

R220 1

<13,22,27,33,36,41> NB_RST#

A

2 2K_0402_1%
AE24
2 562_0603_1% AD24
2 1.47K_0603_1% AB24

R194 1
R195 1

AD4
AD2
AD1

AD3
AC1
AC2
AC3
AB2
AC6
AC5
AC4
AB3
AB4
AB5
AD5
AB8
AA8
AB7
AB6

THM@ 2200P_0402_50V7K THM@ MAX6649MUA_8UMAX
R2151
R2171
R2181

1

Straps: (Internal pull down)

+3VS

CLK_PCIE_VGA
CLK_PCIE_VGA#

PCI EXPRESS

<15> CLK_PCIE_VGA
<15> CLK_PCIE_VGA#

VIP HOST/ EXTERNAL TMDS

PCIE Lane Reversal
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N5

PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P0

2

TBD
Compal Secret Data

Security Classification
3

OSC_IN

Issued Date

2

Keep away from other signal at last 25mils
4

2005/09/10

Deciphered Date

2006/09/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

Title

Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P

Size Document Number
Custom
401412
Date:

|,

09, 2006

Rev
B
Sheet

1

16

of

55


5

4

3

2

1

U9F

C

100mA

+VDD25

1
C267
0.1U_0402_16V4Z

1
C268

2

2

BBP
BBP
BBP
BBP

L10
K22
AA10

VDD25
VDD25
VDD25

AL18
AM18
AL19
AK19
AM20
AL20
AM21
AL21
AJ18

AK18

VARY_BL
DIGON
GENERICD

AD12
AE11
AD23

VGA_LVDSACVGA_LVDSAC+
VGA_LVDSA0+
VGA_LVDSA0VGA_LVDSA1+
VGA_LVDSA1VGA_LVDSA2+
VGA_LVDSA2-

VGA_LVDSBC+ <29>
VGA_LVDSBC- <29>
VGA_LVDSB0+ <29>
VGA_LVDSB0- <29>
VGA_LVDSB1+ <29>
VGA_LVDSB1- <29>
VGA_LVDSB2+ <29>
VGA_LVDSB2- <29>

VGA_LVDSAC- <29>
VGA_LVDSAC+ <29>
VGA_LVDSA0+ <29>
VGA_LVDSA0- <29>
VGA_LVDSA1+ <29>

VGA_LVDSA1- <29>
VGA_LVDSA2+ <29>
VGA_LVDSA2- <29>
ENBKL <33> To EC

0.1U_0402_16V4Z

R2311

2 10K_0402_5%
ENVDD
ENVDD <29>
10/20/05"

TXCM
TXCP

AL9
AM9

DVI_TXC-_L R629 2
DVI_TXC+_L R630 2

1 0_0402_5% DVI@ DVI_TXC1 0_0402_5% DVI@ DVI_TXC+

TX0M
TX0P

AK10
AL10

DVI_TX0-_L R631 2
DVI_TX0+_L R632 2

1 0_0402_5% DVI@ DVI_TX01 0_0402_5% DVI@ DVI_TX0+

TX1M
TX1P

AL11
AM11

DVI_TX1-_L R633 2
DVI_TX1+_L R634 2

1 0_0402_5% DVI@ DVI_TX11 0_0402_5% DVI@ DVI_TX1+

TX2M
TX2P

AL12
AM12

DVI_TX2-_L R635 2
DVI_TX2+_L R636 2

1 0_0402_5% DVI@ DVI_TX21 0_0402_5% DVI@ DVI_TX2+

TX3M
TX3P

AK9
AJ9

TX4M
TX4P

AK11
AJ11

TX5M
TX5P

AK12
AJ12

DDC2DATA
DDC2CLK

AH13
AG13

2 6.8K_0402_5%
2 6.8K_0402_5%
VGA_DVI_DAT
VGA_DVI_CLK

AF11

VGA_DVI_DET

HPD1

11/07/05"

+3VS
R2361
R2371

Need Level
Shift
VGA_DVI_DAT <30>
VGA_DVI_CLK <30>
VGA_DVI_DET <30>

M56P
M56@

CRT GND

AC14
M23
V10
K18

TXCLK_LN
TXCLK_LP
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P

TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

VGA_LVDSBC+
VGA_LVDSBCVGA_LVDSB0+
VGA_LVDSB0VGA_LVDSB1+
VGA_LVDSB1VGA_LVDSB2+
VGA_LVDSB2-

TV GND

BBN
BBN
BBN
BBN

AJ21
AK21
AG18
AH18
AK20
AJ20
AG20
AH20
AH21
AG21

TXVSSR
TXVSSR
TXVSSR
TXVSSR
TXVSSR

AJ7
AK7
AL7
AM7
AK8

TPVSS

AL8

AVSSQ
AVSSN
AVSSN

AK23
AK25
AJ24

VSS1DI

AL23

A2VSSQ
A2VSSN

A2VSSN

AK13
AM17
AL17

VSS2DI

AJ17

PVSS
PLL GND

Y23
K15
R10
AC17

EXPAND GPIO
LVDS

GENERICC

TXCLK_UP
TXCLK_UN
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P

TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

PCIE GND

+VDD_CORE

AE23

INTERGRATED TMDS

100mA

GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30

GPIO_31
GPIO_32
GPIO_33
GPIO_34

FOREARD
COMPATIBILITY

D

AE13
AF13
AF9
AG7
AE10
AE9
AF7
AF8
AH6
AF10
AG10
AH9
AJ8
AH8
AG9
AH7
AG8

AH27
AC23

AL27
R23
P25
R25
T26
U26
Y26
AB26
AC26
AD25
AE26
AF26
AD26
AG25
AH26
AC28
Y28
U28
P28
AH29
AF28
V29
AC29
W27
AB27
V26
AJ26
AJ32
AK29
P26

P29
R29
T29
U29
W29
Y29
AA29
AB29
AD29
AE29
AF29
AG29
AJ29
AK26
AK30
AG26
N30
R31
AF30
AC30
V31
P30
AA31
U30
AD31
AK32
AJ28
Y30
AJ30
AK31

LVDS PLL&I/O GND

U9B

TMDS GND

U9G

B1
H1
L1
P1
U1
Y1
AD7
AE8
AL1
A2
AM2
AD10
E8
H5
K10
M8
T10
E12
AC9
AF14
AD8

C5
F10
J3
L6
M6
P6
AA4
AG11
V3
AG16
R3
C6
C9
F6
H7
J6
AD16
AA6
P7
P5
M3
M9
L7
M7
AD17
AH11
A8
U7
C10
E9

F3
J9
N7
N3
Y5
AM13
AC10
Y6
U6
E5
AL13
A11
U8
U9
U10
R6
AD6
V6
AD14
AD13
D11
J12
K12
A13
F13
E13
F15
K16
W18

Use 15mils trace
connect to GND

AH14

MPVSS

A5

LPVSS

AE18

LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR
LVSSR

AK17
AJ19
AF18
AH17
AG17
AG19

AH19
AF22
AF17
AF21

PCIE_PVSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

W23
AB23
P24

R24
T24
U24
V24
W24
Y24
AC24
AH24
V25
AA25
R26
AA26
T27
AE27
AG31
W26
N24
AA23

M56P
M56@
B

R2321

2 180_0402_5% DVI@

R2331

2 180_0402_5% DVI@

R2341

2 180_0402_5% DVI@

R2351

2 180_0402_5% DVI@

DVI_TXCDVI_TXC+
DVI_TX0DVI_TX0+
DVI_TX1DVI_TX1+
DVI_TX2DVI_TX2+

DVI_TXC- <30>
DVI_TXC+ <30>
DVI_TX0- <30>
DVI_TX0+ <30>

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CORE
GND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS

C27
E32
H28
J30
K17
K27
M32
A22
C20
E19
H20
J24
M28
J28
J16
F30
L29
A31
B32
E30
AE15
AG23
AD9
AF16
AH10
AJ10
AD15

AH16
K23
U18
AE16
AE17
A19
H32
F19
G19
N8
Y7
T19
V19
G21
C21
F21
AE14
AK16
U5
F22
F18
K30
C24
F24
M24
A25
D30
E25
G25
G20

G22
F27
E28
H21
J21
H16
T15
V17
C15
C4
U14
P15
A16
E16
G13
G16
P17
R16
R14
W16
C18
F16

D

C

B

M56P

M56@

DVI_TX1- <30>
DVI_TX1+ <30>
DVI_TX2- <30>
DVI_TX2+ <30>

10/20/05"
Close to connector

A

A

Compal Secret Data

Security Classification
Issued Date

2005/09/10

Deciphered Date

2006/09/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P

Size Document Number
Custom
401412
Date:

|,

09, 2006

Rev
B
Sheet
1

17

of

55


5

4

3

2

1

U9D
U9C

D26
F28
D28
D25
E24
E26
D27
F25
C26
B26
D29
B27
B25
C25

E27
E29
H31
J29
J26
G23
E21
B15
D14
J17

QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7

J31
K29
K25
F23
D20
B16
D16
H15

QSA_0#

QSA_1#
QSA_2#
QSA_3#
QSA_4#
QSA_5#
QSA_6#
QSA_7#

K31
K28
K26
G24
D21
C16
D15
J15

CLKA0
CLKA0#

D31
E31

CKEA0

B30

RASA0#

B28

CASA0#

C29

WEA0#

B31

CSA0#_0
CSA0#_1

B29
C28

CLKA1
CLKA1#

B20
C19

CKEA1

C22

RASA1#

B24

CASA1#

B22

WEA1#

B21

FBC_BA1

<20,21> FBC_BA1

FBCCLK1

R637
2
R638
2

56_0402_5%
1
56_0402_5%
1

R639
2
R640
2

64BIT@
56_0402_5%

1
56_0402_5%
164BIT@

C804

1

2

470P_0402_50V7K

C805

1

+1.8VS

+1.8VS

R238
100_0402_1%

R239
100_0402_1%

Modify 11/22

CSA1#_0
CSA1#_1

1

1

(15mils)

1

R242
100_0402_1%

C270

B23
C23

+MVREFD_1
(15mils)
C269
0.1U_0402_16V4Z

B

MVREFD_0
MVREFS_0

1

C31

C30

2
2

T32
T33

2

470P_0402_50V7K
64BIT@

10/20/05"
Close to Memory Side

0.1U_0402_16V4Z

PAD
PAD

B3
C3

FBC_BA0

<20,21> FBC_BA0

FBCCLK0#

+MVREFD_1
+MVREFS_1

FBCDQM#[0..7]

<20,21> FBCDQM#[0..7]

1

F29
D24

FBCDQS#[0..7]

<20,21> FBCDQS#[0..7]

FBCCLK1#

ODTA0
ODTA1

FBCDQS[0..7]

<20,21> FBCDQS[0..7]

FBCCLK0

B12
C12
B11

C11
C8
B7
C7
B6
F12
D12
E11
F11
F9
D8
D7
F7
G12
G11
H12
H11
H9
E7
F8
G8
G6
G7
H8
J8
K8
L8
K9
L9
K5

L4
K4
L5
N5
N6
P4
R4
P2
R2
T3
T2
W3
W2
Y3
Y2
T4
R5
T5
T6
V5
W5
W6
Y4
R8
T8
R7
T7
V7
W7
W8

W9

FBCA[0..12]

<20,21> FBCA[0..12]

2
2

DQMA#_0
DQMA#_1
DQMA#_2
DQMA#_3
DQMA#_4
DQMA#_5
DQMA#_6
DQMA#_7

FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11

FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41

FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63

FBCD[0..63]

<20,21> FBCD[0..63]

2

C

MEMORY A

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15

2

D

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5

DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35

DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

1

M31
M30
L31
L30
H30
G31
G30
F31
M27
M29
L28
L27
J27
H29
G29
G27
M26
L26
M25
L25
J25
G28
H27
H26
F26
G26
H25
H24
H23

H22
J23
J22
E23
D22
D23
E22
E20
F20
D19
D18
B19
B18
C17
B17
C14
B14
C13
B13
D17
E18
E17
F17
E15
E14
F14
D13
H18
H17
G18

G17
G15
G14
H14
J14

R240
100_0402_1%

R241 1
4.7K_0402_5%
R243 1
4.7K_0402_5%
R244 1
4.7K_0402_5%
R245 1
243_0603_1%

DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11

DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41

DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63

MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6

MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
MAB_15

G4
E6
E4
H4
J5
G5
F4
H6
G3
G2
D4
F2
H2
H3
F5
D5

FBCA0
FBCA1
FBCA2

FBCA3
FBCA4
FBCA5
FBCA6
FBCA7
FBCA8
FBCA9
FBCA10
FBCA11
FBC_BA0
FBC_BA1
FBCA12

DQMB#_0
DQMB#_1
DQMB#_2
DQMB#_3
DQMB#_4
DQMB#_5
DQMB#_6
DQMB#_7

B8
D9
G9
K7
M5
V2
W4
T9

FBCDQM#0
FBCDQM#1
FBCDQM#2
FBCDQM#3
FBCDQM#4
FBCDQM#5
FBCDQM#6
FBCDQM#7

QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7

B9
D10
H10
K6
N4
U2
U4
V8

FBCDQS0
FBCDQS1

FBCDQS2
FBCDQS3
FBCDQS4
FBCDQS5
FBCDQS6
FBCDQS7

QSB_0#
QSB_1#
QSB_2#
QSB_3#
QSB_4#
QSB_5#
QSB_6#
QSB_7#

B10
E10
G10
J7
M4
U3
V4
V9

FBCDQS#0
FBCDQS#1
FBCDQS#2
FBCDQS#3
FBCDQS#4

FBCDQS#5
FBCDQS#6
FBCDQS#7

ODTB0
ODTB1

D6
J4

FBCODT0
FBCODT1

CLKB0
CLKB0#

B4
B5

FBCCLK0
FBCCLK0#

MEMORY B

CKEB0

C2

FBC_CKE0

RASB0#

E2

FBCRAS0#

CASB0#

D3

FBCCAS0#

WEB0#

B2

FBCWE0#

CSB0#_0
CSB0#_1

D2
E3

FBCCS0#

CLKB1
CLKB1#

N2

P3

FBCCLK1
FBCCLK1#
FBC_CKE1

MVREFD_1
MVREFS_1

CKEB1

L3

AA3

DRAM_RST

RASB1#

J2

FBCRAS1#

2

AA5

TEST_MCLK

CASB1#

L2

FBCCAS1#

2

AA2

TEST_YCLK

WEB1#

M2

FBCWE1#

MEMTEST
2
(15mil)

AA7

MEMTEST

CSB1#_0
CSB1#_1

K2
K3

FBCCS1#

2

MEM_RST

D

C

FBCODT0 <20>
FBCODT1 <21>
FBCCLK0 <20>
FBCCLK0# <20>
FBC_CKE0 <20>
FBCRAS0# <20>
FBCCAS0# <20>
FBCWE0# <20>
FBCCS0# <20>

FBCCLK1 <21>
FBCCLK1# <21>
FBC_CKE1 <21>

B

FBCRAS1# <21>
FBCCAS1# <21>
FBCWE1# <21>

FBCCS1# <21>

M56P
M56@

M56P
M56@

A

A

GDDR2
5

Compal Secret Data

Security Classification
Issued Date

2005/09/10

Deciphered Date

2006/09/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P

Size Document Number
Custom
401412
Date:

|,

09, 2006

Rev
B
Sheet
1

18

of

55

5

4

3

2

1

+1.8VS
C271
1

10/20/05"

22U_0805_6.3V6M

C281
1

C282
1

C283
1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

22U_0805_6.3V6M

C284
1

C285
1

C286
1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C294
1

C295
1

C296
1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C297
1

C298
1

C299
1

2

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C304
1

C305
1

C306
1

2

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C311

1

C312
1

C313
1

2

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C318
1

C319
1

C320
1

2

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C324
1

C325
1

C326
1

2

0.1U_0402_16V4Z

+3VS
C331
1

2

0.1U_0402_16V4Z

400mA

2

22U_0805_6.3V6M
C337
1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C339
1

C340
1

2

50mA

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C345
1

C346
1

2

0.1U_0402_16V4Z

2

100mA

0.1U_0402_16V4Z

B

L12
+VDDRH0
1
2
BLM18PG121SN1D_0603
2

0.1U_0402_16V4Z

2
C354

22U_0805_6.3V6M

+2.5VS

1

+2.5VS

1

?mA
+VDDRH1

C355

1

100mA
L15
BLM15AG121SN1D_0402
1
2+VDD1DI 50mA
+2.5VS
2
1
C360
0.1U_0402_16V4Z

120mA
22U_0805_6.3V6M
+A2VDD
2
2
+AVDD

C358

1
0.1U_0402_16V4Z

L17
1
2
BLM15AG121SN1D_0402

C364

1

C365

1
0.1U_0402_16V4Z

+1.8VS
A

AJ5

AM5
AL5
AK5

VDDR4
VDDR4
VDDR4
VDDR4

AE2
AE3
AE4
AE5

VDDR5
VDDR5
VDDR5
VDDR5

VDD25
VDD25
VDD25

AC13
AC16
AC18

100mA

AC15

60mA

A27
F1

VDDRH0
VDDRH1

A28
E1

VSSRH0
VSSRH1

VDDPLL
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

1

AE19

LVDDR/VDDL0
LVDDR/VDDL0

LVDDR/VDDL0

AF20
AE20
AF19

LVDDR/VDDL1
LVDDR/VDDL1
LVDDR/VDDL1

AC21
AC22
AD22

LVDDR/VDDL2
LVDDR/VDDL2
LVDDR/VDDL2

AE21
AD21
AE22

1

+VDD1DI
C370

0.1U_0402_16V4Z

50mA

2

1

AL25
AM25
AM23
AM16
AL16

AVDD
AVDD
VDD1DI

TPVDD
TXVDDR
TXVDDR
TXVDDR
TXVDDR

A2VDD
A2VDD
NC_A2VDDQ

AJ16

VDD2DI

MPVDD

C287

1

C288

C289

1
1
22U_0805_6.3V6M

+VDD_CORE
C300
1

D

R641
0.1U_0402_16V4Z 0.1U_0402_16V4Z +PCIE_VDDR 0.1U_0402_16V4Z
1
2
0_0805_5%
2
2
2
2
2
C290

C291

1
1
1U_0402_6.3V4Z

VDDC+VDDCI=18A
C301
1

2

+VDD_CORE
C302
1

2

C292

C293

1
1
0.1U_0402_16V4Z

C806

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C308
1

C309
1

C310
1

2

2

22U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C314
1

C315
1

C316

1

C317
2

2

2

10/20/05"

2

0.1U_0402_16V4Z

2

1

+VDD_CORE
C303
1

2

C307
1

2

C807

1
0.1U_0402_16V4Z

22U_0805_6.3V6M

2

22U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C321
1

C322
1

C323
1

2

2

1

0.1U_0402_16V4Z

C327
1

C328
1

C329
1

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

220U_D2_4VM
C

0.1U_0402_16V4Z

2

@

2

22U_0805_6.3V6M

2

0.1U_0402_16V4Z
+VDD25
22U_0805_6.3V6M
2
2

L10

2

L9
1
2
MBK1608301YZF_0603

+VDDPLL
C333
C334
C335
1
2
+1.2VS
0.1U_0402_16V4Z
2
2 BLM15AG121SN1D_0402
1
1
1

@
C808
C338
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
22U_0805_6.3V6M
L11
+VDDCI
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
2
2
2
2 BLM18PG121SN1D_0603

+LPVDD
20mA
300mA

C341
C347 2

1

1

C342

C343

1
1
0.1U_0402_16V4Z

+2.5VS

+VDD_CORE

C344

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

Modify 11/18

B

L71

2

0.1U_0402_16V4Z
2
2

C348

C349

0.1U_0402_16V4Z
+LVDDR
2
2
2
C350

1
1
1
22U_0805_6.3V6M 0.1U_0402_16V4Z

C351

1

1
2
+2.5VS
BLM18PG121SN1D_0603

C352

C353
0.1U_0402_16V4Z

1
1
0.1U_0402_16V4Z

L14
1
2
BLM15AG121SN1D_0402

AM8 60mA
AJ6 150mA
AK6
AL6
AM6

1

22U_0805_6.3V6M
2
2
C361

+2.5VS

2
C362

AJ14 160mA
A6 240mA
2

1
22U_0805_6.3V6M

1

2

C363
0.1U_0402_16V4Z
1

1
0.1U_0402_16V4Z
L18
+MPVDD 1
2
+VDD_CORE
2 BLM15AG121SN1D_0402
C368

M56P
M56@

L need close to chip

1
1
1U_0402_6.3V4Z 22U_0805_6.3V6M

1U_0402_6.3V4Z
2
2

1

PVDD

AL14

For PCIE_PVDD_12 only

+1.2VS
22U_0805_6.3V6M
2
2

W10 500mA
T14
W17
P16
T23
K14
U19

LPVDD/VDDL0

1
1
1U_0402_6.3V4Z

+LPVDD

L13
1
2 22U_0805_6.3V6M
BLM15AG121SN1D_0402 2
2
C357

VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

AC11
AC12
P14
U15
W14
W15
R17
R15
V15
V16
T16
U16
T17
U17
V14
R18
T18

V18
P18
P19
R19
W19
AD11

TM DS

+1.8VS

AB9
AB10
AA9
AC19
AD18
AC20
AD19
AD20

PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12

AL31
AM31
AM30
AL32
AL30
AM28
AL29
AM29
AM27

+3VS
C332
1

2

0.1U_0402_16V4Z
C336
1

2

0.1U_0402_16V4Z

N29 1500mA
N28
N27
N26
N25

PLL

C330
1

2

0.1U_0402_16V4Z

I/O

2

PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12
PCIE_VDDR_12

I/O INTERNAL

2

LVDS PLL, I/O

2

PCIE_PVDD_12
PCIE_PVDD_12
PCIE_PVDD_12

L47
1U_0402_6.3V4Z 1U_0402_6.3V4Z +PCIE_PVDD
1
2
V23 100mA 1U_0402_6.3V4Z
BLM18PG121SN1D_0603
N23
2
2
2
2
2
2
P23
C275
C276
C277
C278
C279
C280
U23

POWERPCIE_PVDD_12

P CI EXPRESS

0.1U_0402_16V4Z

VDDR1

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

MEMORY I/O

0.1U_0402_16V4Z

C1
J1
M1
R1
V1
AA1
A3
P9
J10
N9
P10
A9

Y10
P8
R9
Y9
J11
A21
M10
N10
Y8
J18
J19
K21
A12
H13
A15
J20
J13
K11
K19
A18
L23
K20
K24
L24
H19
A24
K13
J32
A30
C32

F32
L32

+

C

2

C RT

D

C273
1

2

+1.2VS

TV

C272
1

U9E

+1.8VS

CO RE

+

1000mA for GDDR1
2400mA for GDDR3
C274
1
2

MEM I/O
CLOCK

220U_D2_4VM@
2

2

L16
+PVDD
1
2
+2.5VS
2 BLM15AG121SN1D_0402
C366

1
22U_0805_6.3V6M

C369
0.1U_0402_16V4Z

+2.5VS

C359
0.1U_0402_16V4Z

1

C367
0.1U_0402_16V4Z

A

L60
+VDDRH1
1
2
BLM18PG121SN1D_0603 2
2
C922
22U_0805_6.3V6M

1

1

C356
0.1U_0402_16V4Z

Compal Secret Data

Security Classification
Issued Date

2005/09/10

Deciphered Date

2006/09/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
SCHEMATIC, M/B LA-3151P

Size Document Number
Custom
401412

Date:

|,

09, 2006

Rev
B
Sheet
1

19

of

55


5

4

3

2

11/03/05' SWAP NET
11/04/05' SWAP NET
11/08/05' SWAP NET

11/03/05' SWAP NET

U12
FBC_BA0
FBC_BA1

L2
L3

BA0
BA1

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBCA5
FBCA4
FBCA3
FBCA2
FBCA1
FBCA0

R2
P7
M2
P3

P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

FBCCLK0#
FBCCLK0

K8
J8

CK
CK

FBC_CKE0

K2

CKE

D

C

FBCCS0#

L8

CS

FBCWE0#

K3

WE

FBCRAS0#

K7

RAS

FBCCAS0#

L7

CAS

FBCDQM#1
FBCDQM#3

F3
B3

LDM
UDM

FBCODT0

K9

ODT

FBCDQS1
FBCDQS#1

F7
E8

LDQS
LDQS

FBCDQS3
FBCDQS#3

B7
A8

UDQS
UDQS

J2

VREF

(SSTL-1.8) VREF = .5*VDDQ

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

R247
1K_0402_1%

1

2

+VRAM_VREFC

R248
1K_0402_1%

1

C375
0.047U_0402_16V4Z

2

2

Close to U12

U13
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2

VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9

R1

VDDL
VSSDL

J1
J7

FBCD26
FBCD30
FBCD24
FBCD29
FBCD28
FBCD27
FBCD31
FBCD25
FBCD11
FBCD14
FBCD9
FBCD15
FBCD13
FBCD10
FBCD12
FBCD8

+1.8VS

1

C371

0.1U_0402_16V4Z

2

1

+1.8VS

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5

1

A3
E3
J3
N1

P9

BA0
BA1

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBCA5
FBCA4
FBCA3
FBCA2
FBCA1
FBCA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7

M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

FBCCLK0#
FBCCLK0

K8
J8

CK
CK

FBC_CKE0

K2

CKE

FBCCS0#

L8

CS

FBCWE0#

K3

WE

FBCRAS0#

K7

RAS

FBCCAS0#

L7

CAS

FBCDQM#0
FBCDQM#2

F3

B3

LDM
UDM

K9

ODT

FBCDQS0
FBCDQS#0

F7
E8

LDQS
LDQS

FBCDQS2
FBCDQS#2

B7
A8

UDQS
UDQS

J2

VREF

(SSTL-1.8) VREF = .5*VDDQ

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+VRAM_VREFC

1

L2
L3

FBCODT0

C372
1U_0402_6.3V4Z

2

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

FBC_BA0
FBC_BA1

C376
0.047U_0402_16V4Z

2

Close to U13

X76@ HY5PS561621AFP-25

B9
B1
D9
D1
D3
D7

C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3

G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9

VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

FBCD20
FBCD17
FBCD18
FBCD23
FBCD22

FBCD19
FBCD21
FBCD16
FBCD7
FBCD0
FBCD6
FBCD3
FBCD2
FBCD5
FBCD1
FBCD4

D

2
2
0.01U_0402_16V7K

2
2
1U_0402_6.3V4Z

2
2
0.1U_0402_16V4Z

C384
0.01U_0402_16V7K

1

2
2
1000P_0402_50V7K

2
2
0.01U_0402_16V7K

2
2
1U_0402_6.3V4Z

FBCDQS#[0..7]

<18,21> FBCDQS#[0..7]

FBCDQM#[0..7]

<18,21> FBCDQM#[0..7]

FBC_BA0

<18,21> FBC_BA0

FBC_BA1

<18,21> FBC_BA1

FBCODT0

<18> FBCODT0

FBC_CKE0

<18> FBC_CKE0

FBCRAS0#

<18> FBCRAS0#

+1.8VS

FBCCAS0#

<18> FBCCAS0#

FBCWE0#

<18> FBCWE0#

FBCCS0#

<18> FBCCS0#

FBCCLK0

<18> FBCCLK0

FBCCLK0#

<18> FBCCLK0#
1

1

C373
0.1U_0402_16V4Z

C

C374
1U_0402_6.3V4Z

2

+0.9VS

0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
C386
C387
C388

C389
C390
C391

C385

FBCDQS[0..7]

<18,21> FBCDQS[0..7]

+1.8VS

1

FBCA[0..12]

<18,21> FBCA[0..12]

DDR2 BGA MEMORY

0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
1

C377
C378
C379
C380
C381
C382
C383

FBCD[0..63]

<18,21> FBCD[0..63]

X76@ HY5PS561621AFP-25

+1.8VS

2
2
1000P_0402_50V7K

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6

DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

2

DDR2 BGA MEMORY

B

1

1

C392
0.01U_0402_16V7K

2
2
0.1U_0402_16V4Z

M56@
FBCODT0
2
M56@
FBC_CKE0
2

M56@
FBCRAS0#
2
M56@
FBCCAS0#
2
M56@
FBCWE0#
2
M56@
FBCCS0#
2
M56@
FBC_BA0
2
M56@
FBC_BA1
2
M56@
FBCA12
2
M56@
FBCA11
2
M56@
FBCA10
2
M56@
FBCA9
2

M56@
FBCA8
2
M56@
FBCA7
2
M56@
FBCA6
2
M56@
FBCA5
2
M56@
FBCA4
2
M56@
FBCA3
2
M56@
FBCA2
2
M56@
FBCA1
2
M56@
FBCA0
2

R249 56_0402_5%
1

R250 56_0402_5%
1
R251 56_0402_5%
1
R252 56_0402_5%
1
R253 56_0402_5%
1
R254 56_0402_5%
1
R255 56_0402_5%
1
R256 56_0402_5%
1
R257 56_0402_5%
1
R258 56_0402_5%
1
R259 56_0402_5%
1
R260 56_0402_5%
1
R261 56_0402_5%
1
R262 56_0402_5%
1
R263 56_0402_5%
1
R264 56_0402_5%
1

R265 56_0402_5%
1
R266 56_0402_5%
1
R267 56_0402_5%
1
R268 56_0402_5%
1
R269 56_0402_5%
1

B

A

A

M56 Only

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

SCHEMATIC, M/B LA-3151P
Size Document Number
Custom

Rev
B

401412

Date:

,

Sheet

09, 2006
1

20

of

55


5

4

3

2

11/03/05' SWAP NET

11/03/05' SWAP NET

U14
FBC_BA0
FBC_BA1

L2
L3

BA0
BA1

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBCA5
FBCA4
FBCA3
FBCA2
FBCA1
FBCA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3

M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

FBCCLK1#
FBCCLK1

K8
J8

CK
CK

K2

CKE

D

FBC_CKE1

FBCCS1#

L8

FBCWE1#

K3

WE

FBCRAS1#

K7

RAS

FBCCAS1#
FBCDQM#6
FBCDQM#4

C

F3
B3

CAS
LDM

UDM

FBCODT1

K9

ODT

FBCDQS6
FBCDQS#6

F7
E8

LDQS
LDQS

R270
1K_0402_1%
64BIT@

FBCDQS4
FBCDQS#4

B7
A8

UDQS
UDQS

J2

VREF

(SSTL-1.8) VREF = .5*VDDQ

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

1

2

+VRAM_VREFD

1

2

2

R271
1K_0402_1%
64BIT@

C397
0.047U_0402_16V4Z
64BIT@

Close to U14

U15
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1

C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

FBCD32
FBCD39
FBCD34

FBCD37
FBCD38
FBCD33
FBCD36
FBCD35
FBCD49
FBCD55
FBCD50
FBCD53
FBCD54
FBCD48
FBCD52
FBCD51

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5

FBC_BA0
FBC_BA1

L2
L3

BA0
BA1

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBCA5
FBCA4
FBCA3
FBCA2
FBCA1
FBCA0

R2
P7
M2
P3
P8
P2
N7

N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

FBCCLK1#
FBCCLK1

K8
J8

CK
CK

K2

CKE

FBC_CKE1
+1.8VS
FBCCS1#

L8

FBCWE1#

K3

WE

FBCRAS1#

K7

RAS

FBCCAS1#

L7

FBCDQM#5
FBCDQM#7
1

2

1

+1.8VS

L7

CS

C393
0.1U_0402_16V4Z
64BIT@

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

1

2

2

CAS
LDM
UDM

K9

ODT

FBCDQS5
FBCDQS#5

F7
E8

LDQS
LDQS

FBCDQS7
FBCDQS#7

B7
A8

UDQS
UDQS

J2

VREF

(SSTL-1.8) VREF = .5*VDDQ

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+VRAM_VREFD

A3
E3
J3
N1
P9

CS

FBCODT1

C394

1U_0402_6.3V4Z
64BIT@

1

F3
B3

C398
0.047U_0402_16V4Z
64BIT@

Close to U15

X76@ HY5PS561621AFP-25

B

1

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6

DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6

VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4

VSS5

A3
E3
J3
N1
P9

FBCD62
FBCD58
FBCD63
FBCD56
FBCD57
FBCD61
FBCD59
FBCD60
FBCD45
FBCD41
FBCD47
FBCD42
FBCD43
FBCD46
FBCD40
FBCD44

D

FBCD[0..63]

<18,20> FBCD[0..63]

FBCA[0..12]

<18,20> FBCA[0..12]

FBCDQS[0..7]

<18,20> FBCDQS[0..7]

FBCDQS#[0..7]

<18,20> FBCDQS#[0..7]

FBCDQM#[0..7]

<18,20> FBCDQM#[0..7]

FBC_BA0

<18,20> FBC_BA0

FBC_BA1

<18,20> FBC_BA1
+1.8VS

FBCODT1

<18> FBCODT1

FBC_CKE1

<18> FBC_CKE1

FBCRAS1#

<18> FBCRAS1#

FBCCAS1#

<18> FBCCAS1#

FBCWE1#

<18> FBCWE1#

1

2

1

C395
0.1U_0402_16V4Z
64BIT@

2

FBCCLK1

<18> FBCCLK1

C396
1U_0402_6.3V4Z
64BIT@

C

FBCCS1#

<18> FBCCS1#

FBCCLK1#

<18> FBCCLK1#

X76@ HY5PS561621AFP-25

DDR2 BGA MEMORY

B

DDR2 BGA MEMORY

+1.8VS
+1.8VS
1

0.01U_0402_16V7K
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
1
1
1
1
1
C400
C401
C402
C403
C404
C405

C399

2
2
1000P_0402_50V7K

2
2
0.01U_0402_16V7K

2
2
1U_0402_6.3V4Z

1

2
2
0.1U_0402_16V4Z

C406
0.01U_0402_16V7K

+0.9VS

0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
1
C407
C408
C409
C410
C411
C412
C413
2
2
1000P_0402_50V7K

2
2
0.01U_0402_16V7K

2
2
1U_0402_6.3V4Z

1

M56@
FBCRAS1#
2
M56@
FBC_CKE1
2
M56@
FBCODT1
2
M56@
FBCCAS1#
2
M56@
FBCWE1#
2
M56@
FBCCS1#
2

C414

0.01U_0402_16V7K

2
2
0.1U_0402_16V4Z

R273 56_0402_5%
1
R274 56_0402_5%
1
R275 56_0402_5%
1
R276 56_0402_5%
1
R277 56_0402_5%
1
R278 56_0402_5%
1

M56 Only

A

A

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

SCHEMATIC, M/B LA-3151P
Size Document Number
Custom

Rev
B

401412

Date:

,

Sheet

09, 2006
1

21

of

55


5

4

3

PLACE THESE PCIE AC COUPLING
CAPS CLOSE TO U600

10U_0805_10V4Z

F27

F28
F29
G26
G27
G28
G29
J27
J29
L25
L26
L29
N29

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7
PCIE_VDDR_8
PCIE_VDDR_9
PCIE_VDDR_10
PCIE_VDDR_11
PCIE_VDDR_12
PCIE_VDDR_13

1U_0402_6.3V4Z

2

1

PCIE_VDDR

2

C608 AND C609 CLOSE
TO U600.U29

+1.8VS

C

PCIE_VDDR
L20

1

2

KC FBM-L11-201209-221LMAT_0805

1

1

C423

C424

1

C425

1

1

C426

C427

1

2
2
2
2
2
2
22U_0805_6.3V6M 1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z

C428
1U_0402_6.3V4Z

R303

20M_0603_5%
2
1
C429
10P_0402_50V8K
1
2

2

R298
20M_0603_5%

1
1

32K_X1
Y2

4

OUT

NC

3

1

IN

NC

2

32.768KHZ_12.5PF_6H03200468
32K_X2

2

C430
10P_0402_50V8K

INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

B

<13> ALLOW_LDTSTOP
RP1
+3VS

1
2
3
4

8

7
6
5

+1.2V_HT

PCI_SERR#
PCI_TRDY#
PCI_FRAME#
PCI_STOP#

R777 1

2 @ 10K_0402_5%
<7> LDT_RST#
FOR SB460, THIS BALL
IS LDT_RST# ONLY

AC26
W26
W24
W25
AA24
AA23
AA22
AA26
Y27
AA25
AH9
B24

W23
AC25

X2

CPU_PG
INTR/LINT0
NMI/LINT1
INIT#
SMI#
NC
IGNNE#
A20M#
FERR#
STPCLK#/ALLOW_LDTSTP
CPU_STP#/DPSLP_3V#
NC
DPRSLPVR
LDT_RST#/DPRSTP#/PROCHOT#
218S4RASA11GS SB460_BGA549

LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#
BMREQ#
SERIRQ

L PC

C1

AD3
AF1
AF4
AF3

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

1
PM_CLKRUN# <31,36,41>

2

A_RST#

2

I

R292
8.2K_0402_5%
PCI_CBE#[3..0]

2 @
2
2
2
2
2

1
1
1
1
1
1

22_0402_5%
22_0402_5%
22_0402_5%
22_0402_5%
22_0402_5%
22_0402_5%

AG24
AG25
AH24
AH25

AF24
AJ24
AH26
W22
AF23

RTCCLK
RTC_IRQ#/ACPWR_STRAP
VBAT
RTC_GND

E1
D1

C419
2 0.1U_0402_16V4Z
U17

4

O

2NB_RST#
33_0402_5%

1
R279

NB_RST# <13,16,27,33,36,41>
C

74LVC1G125GW_SOT3535

PCI_CBE#[3..0] <31,36,37,40>
R645 1

2 @ 0_0402_5%

+3VALW
PCI_FRAME# <31,36,37,40>
PCI_DEVSEL# <31,36,37,40>
PCI_IRDY# <31,36,37,40>
PCI_TRDY# <31,36,37,40>
PCI_PAR <31,36,37,40>
PCI_STOP# <31,36,37,40>
PCI_PERR# <31,36,37,40>
PCI_SERR# <31,36,37>
PCI_REQ#0 <40>
PCI_REQ#1 <36>
PCI_REQ#2 <37>
PCI_REQ#3 <31>
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3

12/26:Modify
C420
2 0.1U_0402_16V4Z

1

PCIRST#

2

I

R297

U18

O

4

R288

2 PCI_RST#
33_0402_5%

1

R646 1

2 @ 0_0402_5%

RP2

1

2
3
4

<37,40>
<31>
<36>
<36,37>

RP3

8
7
6
5

PCI_PLOCK#
PCI_I RDY#
PCI_PERR#
PCI_DEVSEL#

1
2
3
4

+3VS

8.2K_1206_8P4R_5%

LPC_AD0 <33,41>
LPC_AD1 <33,41>
LPC_AD2 <33,41>
LPC_AD3 <33,41>
LPC_FRAME# <26,33,41>
LPC_DRQ#0 <41>

8.2K_1206_8P4R_5%

1

+
1

RP4

1
2
3
4

+3VS

+RTCBATT

PCI_REQ#3
PCI_REQ#0
PCI_REQ#2
PCI_REQ#1

8
7
6
5

8.2K_1206_8P4R_5%

+RTCBATT

D3

RTCBATT

RP5

BAS40-04_SOT23
+RTCVCC
R307 2
1K_0603_5%

C432
0.1U_0402_16V4Z
2
2
1U_0402_6.3V4Z
JOPEN1

1
2
3

4

+3VS

1

+CHGRTC

2

PM_CLKRUN#
PCI_PAR

8.2K_1206_8P4R_5%

1
R308
0_0603_5%

PCI_REQ#4

8
7
6
5

C434
0.1U_0402_16V4Z

R812 1

2

BMREQ#

10K_0402_5%

1

1

8.2K_1206_8P4R_5%

BATT1 45@

2

BMREQ# <13>
SERIRQ <33,37,41>

VBAT_IN

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQH#
PCI_PIRQG#

8
7
6

5

B

RTC_CLK <26>
RTC_IRQ# <26>

C431

PCI_RST# <31,36,37,39,40>

74LVC1G125GW_SOT3535

8.2K_0402_5%

<40>
<36>
<37>
<31>
+3VS

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
LPC_DRQ#1
BMREQ#

1

CLK_PCI_LAN
CLK_PCI_LPC
CLK_PCI_MINI
CLK_PCI_PCM
CLK_PCI_1394
CLK_PCI_SIO

12/26:Modify

RTC Battery

D3
F5

RTC

32K_X2

X1

C PU

FOR SB600, CONNECT TO CPU_PG/LDT_PG
FOR SB460, CONNECT TO SSMUXSEL/GPIO0

D2

XTAL

32K_X1

PLACE THESE COMPONENTS CLOSE TO U600, AND
USE GROUND GUARD FOR 32K_X1 AND 32K_X2

PM_CLKRUN#
PCI_PLOCK#

1 C944
1U_0402_6.3V4Z

5

NC

C422

1

PCIE_PVDD

U28

1

P

C421

OE#

U29

2

R835
R836
R837
R838
R840
R841

G

1

R8391
2
10K_0402_5%

3

PCIE_CALI

5

E27

1

2 4.12K_0402_1%

P

1

OE#

R296

CLK_PCI_LAN_R

G

PCIE_CALRP
PCIE_CALRN

3

E29
E28

EMI 11/2 Modify
R834
10K_0402_5%
U59
@
CLKOUT1
8 DLY CNTRL CLKOUT1 2

CLKOUT2
1 CLKIN
CLKOUT2 6
CLKOUT3
3 VDD
CLKOUT3 7
CLKOUT4
13 VDD
10
CLKOUT4
CLKOUT5
9 SSON
11
CLKOUT5
CLKOUT6
4 SS%
14
CLKOUT6
5 GND
CLKOUT7 15
12 GND
CLKOUT8 16
R842
ASM3P623S00EF-16-TR_TSSOP16
+3VALW
10K_0402_5%
1

1

2 150_0402_1%
2 150_0402_1%

L68
FBM-L11-160808-800LMT_0603

2

1
1

+3VS

3

R294
R295

+3VS

1

2
2
2
2

W7
Y1
W8

W5
AA5
Y3
AA6
AC5
AA7
AC3
AC7
AJ7
AD4
AB11
AE6
AC9
AA3
AJ4
AB1
AH4
AB2
AJ3
AB3
AH3
AC1
AH2
AC2
AH1
AD2
AG2
AD1
AG1
AB9

AF9
AJ5
AG3
AA2
AH6
AG5
AA1
AF7
Y2
AG8
AC11
AJ8
AE2
AG9
AH8
AH5
AD11
AF2
AH7
AB12
AG4
AG7
AF6

2

1
1
1
1

L19
KC FBM-L11-201209-221LMAT_0805

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N

D

PCI_AD[31..0] <26,31,36,37,40>

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12

PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
PCI_FRAME#
PCI_DEVSEL#
PCI_I RDY#
PCI_TRDY#
PCI_PAR
PCI_STOP#
PCI_PERR#

PCI_SERR#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3

1

PCIE_VDDR
+1.8VS

T25
T26
T22
T23
M25
M26
M22
M23

CLK_PCI_LAN_R <26>
CLK_PCI_LPC_R <26>
CLK_PCI_MINI_R <26>
CLK_PCI_PCM_R <26>
CLK_PCI_1394_R <26>

CLK_PCI_SIO_R <26>

PCIRST#
PCI_AD[31..0]

AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11
AD8/ROMA9
AD9/ROMA8
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7
AD24

AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#/ROMA10
CBE1#/ROMA1
CBE2#/ROMWE#
CBE3#
FRAME#
DEVSEL#/ROMA0
IRDY#
TRDY#/ROMOE#
PAR/ROMA19
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/PDMA_REQ0#
REQ4#/PLL_BP33/PDMA_REQ1#
GNT0#
GNT1#
GNT2#
GNT3#/PLL_BP66/PDMA_GNT0#
GNT4#/PLL_BP50/PDMA_GNT1#
CLKRUN#

LOCK#

CLK_PCI_LAN_R
CLK_PCI_LPC_R
CLK_PCI_MINI_R
CLK_PCI_PCM_R
CLK_PCI_1394_R
CLK_PCI_SIO_R

CLK_PCI_LAN <31>
CLK_PCI_LPC <33>
CLK_PCI_MINI <36>
CLK_PCI_PCM <37>
CLK_PCI_1394 <40>
CLK_PCI_SIO <41>
PCI_CLK6 <26>
SB_SPDIFO <26>

2

R289
R290
R291
R293

A_MTX_C_SRX_P0
A_MTX_C_SRX_N0
A_MTX_C_SRX_P1
A_MTX_C_SRX_N1
@ 49.9_0402_1% SB_TX2P

@ 49.9_0402_1% SB_TX2N
@ 49.9_0402_1% SB_TX3P
@ 49.9_0402_1% SB_TX3N

AJ9

22_0402_5%
@ 22_0402_5%
@ 22_0402_5%
@ 22_0402_5%
@ 22_0402_5%
@ 22_0402_5%
22_0402_5%
0_0402_5%

2
2
2
2
2
2
2
2

2

R294 CALRP: SB600=562R 1%, SB460=150R 1%
R295 CALRN: SB600=2.05K 1%, SB460=150R 1%
R296 CALRN: SB600=0R 1%, SB460=4.12K 1%

A_MTX_C_SRX_P0
A_MTX_C_SRX_N0
A_MTX_C_SRX_P1
A_MTX_C_SRX_N1

PCIRST#

1
1
1
1
1
1
1
1

1

<12>
<12>
<12>
<12>

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P

PCIE_TX3N

CLK_PCI_LAN_R R280
CLK_PCI_LPC_R R281
CLK_PCI_MINI_R R282
CLK_PCI_PCM_R R283
CLK_PCI_1394_R R284
CLK_PCI_SIO_R R285
PCI_CLK6_R
R286
R287

2

D

P29
P28
M29
M28
K29
K28
H29
H28

U2
T2
U1
V2
W3

U3
V1
T1

2

A_MRX_C_STX_P0
A_MRX_C_STX_N0
A_MRX_C_STX_P1
A_MRX_C_STX_N1

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
SPDIF_OUT/GPIO41

1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

PCIE_RCLKP
PCIE_RCLKN

2

C415 1
C416 1
C417 1
C418 1

Part 1 of 4

PCI CLKS

A_MRX_STX_P0
A_MRX_STX_N0
A_MRX_STX_P1
A_MRX_STX_N1

A_MRX_STX_P0
A_MRX_STX_N0
A_MRX_STX_P1
A_MRX_STX_N1

SB460
A_RST#

PCI INTERFACE

J24
J25

PCI EXPRESS INTERFACE

AG10

<15> SBSRC_CLKP
<15> SBSRC_CLKN

FOR SB600 VCC_SB= 1.2V
FOR SB460 VCC_SB= 1.8V

1

U16A
A_RST#

<12>
<12>
<12>
<12>

2

2

+3VS

SB460 ONLY

A

LPC_DRQ#0

LPC_DRQ#1
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
SERIRQ

R299
R300
R301
R302
R304
R305
R306

1
1
1
1
1
1
1

2
2
2
2
2
2
2

2

1

1

Modify 11/07

C942
15P_0402_50V8J
A

@ JUMP_43X39

10K_0402_5%
10K_0402_5%
100K_0402_5%
100K_0402_5%
100K_0402_5%
100K_0402_5%
10K_0402_5%

Please Closed RAM
Door

Compal Secret Data

Security Classification
Issued Date

LPC PULL UPS

2005/03/08

Deciphered Date

2006/03/08

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

2

4

3

2

Title

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

Size Document Number
Custom 401412

Date:

¬P

,

Re v
B
Sheet

09, 2006
1

22

of

55


5

4

1 10K_0402_5% LPC_SMI#
1 10K_0402_5% EC_FLASH#_R
SB_INT_FLASH_SEL#
1 10K_0402_5%

R318

R320
R322
R323
R324
R325
R326

2
2
2
2
2
2
2

1
1
1
1
1
1
1

10K_0402_5%
10K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
10K_0402_5%
10K_0402_5%

EC_SWI#
SB_PCIE_WAKE#
PM_SLP_S5#
PM_SLP_S3#
S3_STATE_R
EC_SCI#
BLINK/GPM6#

1
1
1
1
1
1

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

EC_SMI#
USB_OC#0
USB_OC#1
USB_OC#3
CP_PE#
USB_OC#6

2
2
2
2
2
2

R319 2
R321 2

1 10K_0402_5%
1 10K_0402_5%
EC_GA20
<33> EC_GA20
EC_KBRST#
Modify : 11/07 <33> EC_KBRST#
LPC_PME#
LPC_SMI#
S3_STATE_R
2
1
<33> S3_STATE
R813
@ 0_0402_5% SYS_RESET#
SB_PCIE_WAKE#
<36,39> SB_PCIE_WAKE#
BLINK/GPM6#
H_THERMTRIP#
<7> H_THERMTRIP#
EC_RSMRST#

<33> EC_RSMRST#

SB_OSC_INT

<15> SB_OSCIN

R830 2

<35> EC_FLASH#

1

+3VS

0_0402_5%

R334 2
R335 2
R336 2

<35> SB_INT_FLASH_SEL#
<44> SB_SPKR
<9,10,15> SB_CK_SCLK
<9,10,15> SB_CK_SDAT
+3VS
R337
R338
R647
R831

2
2
2
2

1
1
1
1

2.2K_0402_5%
2.2K_0402_5%
10K_0402_5%
10K_0402_5%

SB_CK_SCLK
SB_CK_SDAT
R339 2
R340 2

SB_CK_SCLK
SB_CK_SDAT
GPIO13
IDE_HRESET#

EC_SMI#
USB_OC#6
AZ_RST#
CP_PE#

USB_OC#3
EC_LID_OUT#
USB_OC#1
USB_OC#0

<39> CP_PE#
1 @ 0_0402_5%
<33> EC_LID_OUT#
<39> USB_OC#0

2

<44> ICH_BITCLK_AUDIO

R342 1

2

<34> ICH_SYNC_MDC

R343 1

2

<44> ICH_SYNC_AUDIO

R346 1

2

<34> ICH_RST_MDC#

R347 1

2

<44> ICH_RST_AUDIO#

R348 1

2

R349 1

2

R350 1

2

<34> ICH_SDOUT_MDC
<44> ICH_SDOUT_AUDIO

AZ_BIT_CLK
AZ_SDATA_OUT

AZ_BIT_CLK
33_0402_1%

AZ_SY NC

33_0402_1%
AZ_SY NC
33_0402_1%
<26> AC_SDATA_OUT
<44> ICH_AC_SDIN0
<34> ICH_AC_SDIN1

33_0402_1%
AZ_RST#
33_0402_1%

AC_SDATA_OUT
ICH_AC_SDIN0
ICH_AC_SDIN1
ICH_AC_SDIN2
AC_RST#

33_0402_1%
AZ_SDATA_OUT

R814 2
1 10K_0402_5%
IDE_HRESET#
<27> IDE_HRESET#
GPIO13

33_0402_1%

PAD
ICH_AC_SDIN2

ICH_AC_SDIN1
ICH_AC_SDIN0

2
2
2

1 @ 10K_0402_5%
1 @ 10K_0402_5%
1 @ 10K_0402_5%

R355
R356
R357
R358
R648

2
2
2
2
2

10K_0402_5% AZ_RST#
1
1 @ 10K_0402_5% AZ_SY NC
1 @ 10K_0402_5% AZ_SDATA_OUT
1 @ 10K_0402_5% AZ_BIT_CLK
10K_0402_5% AC_RST#
1

B23

14M_OSC

C28
A26
B29
A23
B27
D23
B26
C27
B28
C3
F3
D26
C26
A27
A4
C6
C5
C4
B4
B6
A6
C8
C7
B8
A8

OSC / RST

NC
ROM_CS#/GPIO1
GHI#/GPIO6
VGATE/GPIO7
GPIO4
GPIO5
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
NC
NC
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LDT_PG/SSMUXSEL/GPIO0
NC

AZ_BITCLK
AZ_SDOUT
NC
AZ_SYNC
NC

L1
L2
L4
J2
J4

M3
L5

AC_BITCLK/GPIO38
AC_SDOUT/GPIO39
ACZ_SDIN0/GPIO42
ACZ_SDIN1/GPIO43
ACZ_SDIN2/GPIO44
AC_SYNC/GPIO40
AC_RST#/GPIO45

<7,33> EC_THERM#
<7,13> LDT_STOP#

EC_THERM#
R353 2

T12
1 0_0402_5%

E23
AC21
AD7
AE7
AA4
T4
D4
AB19

A17

CLK_USB_48M

CLK_USB_48M <15>

USB_RCOMP

A14 R312 2

1 11.3K_0402_1%

USB_ATEST1
USB_ATEST0

A11
A10

NC
NC

H12
G12

NC
NC

E12
D12

USB_HSDP7+

USB_HSDM7-

E14
D14

USB_HSDP6+
USB_HSDM6-

G14
H14

USB20_P6
USB20_N6

USB20_P6 <43>
USB20_N6 <43>

USB_HSDP5+
USB_HSDM5-

D16
E16

USB20_P5
USB20_N5

USB20_P5 <34>
USB20_N5 <34>

USB_HSDP4+

USB_HSDM4-

D18
E18

USB20_P4
USB20_N4

USB20_P4 <36>
USB20_N4 <36>

USB_HSDP3+
USB_HSDM3-

G16
H16

USB20_P3
USB20_N3

USB20_P3 <43>
USB20_N3 <43>

USB_HSDP2+
USB_HSDM2-

G18
H18

USB20_P2

USB20_N2

USB20_P2 <39>
USB20_N2 <39>

USB_HSDP1+
USB_HSDM1-

D19
E19

USB20_P1
USB20_N1

USB20_P1 <39>
USB20_N1 <39>

USB_HSDP0+
USB_HSDM0-

G19
H19

USB20_P0
USB20_N0

USB20_P0 <39>
USB20_N0 <39>

AVDDTX_0

AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4

B9
B11
B13
B16
B18
A9
B10
B12
B14
B17

AVDDC

A12

AVSSC

A13

AVSS_USB_1

AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24
AVSS_USB_25
AVSS_USB_26
AVSS_USB_27
AVSS_USB_28
AVSS_USB_29
AVSS_USB_30
AVSS_USB_31

AVSS_USB_32
AVSS_USB_33

A16
C9
C10
C11
C12
C13
C14
C16
C17
C18
C19
C20
D11
D21
E11
E21
F11
F12
F14
F16
F18
F19
F21
G11
G21
H11
H21

J11
J12
J14
J16
J18
J19

D

01/03/05" modify

SB600 ONLY
(NC for SB460)

AVDD_USB

+3VALW

C

L21

NC
NC
USB_OC7#/GEVENT7#
USB_OC6#/GEVENT6#
USB_OC5#/AZ_RST#/GPM5#
USB_OC4#/GPM4#
USB_OC3#/GPM3#
USB_OC2#/FANOUT1/LLB#/GPM2#

USB_OC1#/GPM1#
USB_OC0#/GPM0#

N2
M2
K2
L3
K3

SB460 ONLY

33_0402_1%

R351
R352
R354

RSMRST#

BALLS(C6 AND C5) ARE FOR SB600 ONLY (NC FOR SB460)

EC_FLASH# R832 2

R341 1

1 10K_0402_5%
1 10K_0402_5%
CPU_PWRGD

<7> CPU_PWRGD

<33> EC_SMI#

<34> ICH_BITCLK_MDC

1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%
EC_FLASH#_R
SB_INT_FLASH_SEL#

E2

USB PWR

R328
R329
R330
R331
R332
R333

SYS_RESET#
LPC_PME#
EC_KBRST#
PBTN_OUT#

USBCLK

USB INTERFACE

1 10K_0402_5%
1 10K_0402_5%
1 @10K_0402_5%
1 10K_0402_5%

PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
NC
TEST1
TEST0
GA20IN
KBRST#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#

ACPI / WAKE UP EVENTS

2
2

2
2

A3
B2
F7
A5
E3
B5
B3
F9
E9
G9
AF26
AG26
D7
C25
D9
F4
E7
C2
G7

GPIO

R313
R314
R315
R316

Part 4 of 4

SB460
EC_SWI#
EC_SCI#
PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
SB_PWRGD
SUS_STAT#

<33> EC_SWI#
<33> EC_SCI#
<33> PM_SLP_S3#
<33> PM_SLP_S5#
<33> PBTN_OUT#
<7,42> SB_PWRGD
<35> SUS_STAT#

+3VALW

B

1

U16D

USB OC

2

2
2

AZALIA

R309
R310
R644

C

2

AC97

+3VS

D

3

SB460 ONLY

FANOUT0/GPIO3
GPIO31
GPIO13
DPSLP_OD#/GPIO37
GPIO14
TALERT#/GPIO10
SLP#/LDT_STP#

NC

TEST POINT TP602 FOR
SB460_FANOUT0

1
1

C435

1

C436

1

C437

1

C438

1

C439

1

C440

1

C441

1

2

C442 KC FBM-L11-201209-221LMAT_0805

0.1U_0402_16V4Z
2
2
2
2
2
2
2
2
10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z0.1U_0402_16V4Z
+3.3V_AVDDC

+3VALW
L22
1

1

1

C443

1

C445

2

KC FBM-L11-201209-221LMAT_0805

C444
2
0.1U_0402_16V4Z

2

2

1U_0402_6.3V4Z

2.2U_0603_6.3V6K

PLACE C443,C444 AND
C445 CLOSE TO U16

B

218S4RASA11GS SB460_BGA549

ICH_BITCLK_MDC
1

2

A

ICH_BITCLK_AUDIO
1

C945
@ 10P_0402_50V8K

2

C946
@ 10P_0402_50V8K
A

Modify 11/27

Compal Secret Data

Security Classification
2005/03/08

Issued Date

2006/03/08

Deciphered Date

4

3

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

2

Size Document Number
Custom 401412
Date:

,

R ev
B
Sheet

09, 2006

1

23

of

55


5

4

3

2

1

PLACE SATA AC COUPLING
CAPS CLOSE TO U16

D

2

SATA@

2

R360 2

1

1

C451

R778
0_0402_5%
PATA@

SATA@

1

1
2
MBK2012121YZF_0805
SATA@

XTLVDD_ATA

1

1

L61

C649 CLOSE TO THE

BALL OF U600

R779
0_0402_5%
PATA@
2
22U_0805_6.3V6M
2
SATA@

2
2
0.1U_0402_16V4Z
SATA@

B

1 R781

2
2

SATA_X2

R780
0_0402_5%
PATA@

2

1

1

R363
10M_0603_5%
SATA@

C458

1U_0402_6.3V4Z
2
2 SATA@
0.1U_0402_16V4Z
SATA@

PATA@ 0_0402_5%
C459 1
2

SATA_X1

1

1

_0402_16V4Z
1
1
1

C455
C456
C457

2

C454

SATA_RX1SATA_RX1+

AH13
AH14

SATA_TX2+
SATA_TX2-

AH16
AJ16

SATA_RX2SATA_RX2+

AJ11
AH11

SATA_TX3+
SATA_TX3-

AH12
AJ13

SATA_RX3SATA_RX3+

AF12

SATA_CAL

SATA_X1

AD16

SATA_X1

SATA_X2

AD18

SATA_X2

27P_0402_50V8J
SATA@

Y3
25MHZ_20PF_6X25000017
SATA@
C460 1

R362

1

R361 2
1 0_0402_5% AC12
SATA@
AD14
2
PLLVDD_ATA
4.7K_0402_5%
AJ10

2

27P_0402_50V8J
SATA@

VCC_SB=1.2V WHEN SB600
VCC_SB 1.8V WHEN SB460

SB460
Part 2 of 4

ATA 66/100

SATA_TX1+
SATA_TX1-

AH17
AJ17

C452
2

@2.2U_0603_6.3V6K

R360 IS 1K 1% FOR 25MHz
XTAL, 4.99K 1% FOR 100MHz
INTERNAL CLOCK

AVDD_SATA

L62 SATA@
1
2
KC FBM-L11-201209-221LMAT_0805 1

AH18
AJ18

SATA@
1K_0402_1% SATA_CAL

NOTE:

C453

1U_0402_6.3V4Z
2 SATA@

+1.8VS

1

SATA_LED#

<33> SATA_LED#
+3VS

+1.8VS

SATA_RX0SATA_RX0+

PIDE_IORDY
PIDE_IRQ
PIDE_A0
PIDE_A1
PIDE_A2
PIDE_DACK#
PIDE_DRQ
PIDE_IOR#
PIDE_IOW#
PIDE_CS1#
PIDE_CS3#

AB29
AA28
AA29
AB27
Y28
AB28
AC27
AC29
AC28

W28
W27

IDE_IOR DY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DREQ
IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

PIDE_D0
PIDE_D1
PIDE_D2
PIDE_D3
PIDE_D4
PIDE_D5
PIDE_D6
PIDE_D7
PIDE_D8
PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14

PIDE_D15

AD28
AD26
AE29
AF27
AG29
AH28
AJ28
AJ27
AH27
AG27
AG28
AF28
AF29
AE28
AD25
AD29

IDE_D0
IDE_D1
IDE_D2
IDE_D3
IDE_D4
IDE_D5
IDE_D6
IDE_D7
IDE_D8
IDE_D9
IDE_D10

IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15

D

IDE_IORDY <27>
IDE_IRQ <27>

IDE_DACK# <26,27>
IDE_DREQ <27>
IDE_IOR# <27>
IDE_IOW# <27>
IDE_CS1# <27>
IDE_CS3# <27>

C

SATA_ACT#
PLLVDD_SATA_1
PLLVDD_SATA_2

XTLVDD_ATA

AC16

XTLVDD_SATA

AVDD_SATA

AE14
AE16
AE18
AE19
AF19
AF21
AG22
AG23
AH22
AH23
AJ12
AJ14
AJ19
AJ22
AJ23

AVDD_SATA_1
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_4
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7
AVDD_SATA_8
AVDD_SATA_9
AVDD_SATA_10
AVDD_SATA_11
AVDD_SATA_12

AVDD_SATA_13
AVDD_SATA_14
AVDD_SATA_15

AB14
AB16
AB18
AC14
AC18
AC19
AD12
AD19
AD21
AE12
AE21
AF11
AF14
AF16
AF18
AG11
AG12
AG13
AG14
AG16
AG17
AG18
AG19
AG20
AG21
AH10

AH19

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20
AVSS_SATA_21
AVSS_SATA_22
AVSS_SATA_23
AVSS_SATA_24
AVSS_SATA_25
AVSS_SATA_26
AVSS_SATA_27

SPI ROM

SATA@

C450

1U_0402_6.3V4Z

C650 CLOSE TO THE
BALL OF U600

1U_0402_6.3V4Z

C

1

AH20
AJ20

HW MONITOR

PLLVDD_ATA
L23
1
2
MBK2012121YZF_0805

SATA_TX0+
SATA_TX0-

SATA_DTX_SRX_N0
SATA_DTX_SRX_P0

PLACE SATA_CAL
RES & CAP VERY
CLOSE TO BALL
OF U16

2

+1.8VS

AH21
AJ21

SERIAL ATA

<27> SATA_DTX_C_SRX_N0
<27> SATA_DTX_C_SRX_P0

SATA_STX_DRX_P0
SATA_STX_DRX_N0

SERIAL ATA POWER

SATA_STX_C_DRX_P0 SATA@ 0.01U_0402_16V7K
1
2 C446
SATA_STX_C_DRX_N0

C447
1
2
SATA@ 0.01U_0402_16V7K
SATA_DTX_C_SRX_N0 SATA@ 0.01U_0402_16V7K
1
2 C448
SATA_DTX_C_SRX_P0
C449
1
2
SATA@ 0.01U_0402_16V7K

IDE_A[0..2]

<27> IDE_A[0..2]

U16B
<27> SATA_STX_C_DRX_P0
<27> SATA_STX_C_DRX_N0

IDE_D[0..15]

<27> IDE_D[0..15]

NC
NC
NC
NC
NC

J3
J6
G3
G2
G6

NC
NC

C23
G5

NC
NC
NC

M4
T3
V4

NC
NC
NC

N3
P2
W4

NC

NC
NC
NC
NC

P5
P7
P8
T8
T7

NC
NC
NC
NC
NC
NC
NC
NC

V5
L7
M8
V6
M6
P4
M7
V7

NC

N1

NC

M1

B

218S4RASA11GS SB460_BGA549

A

A

Compal Secret Data

Security Classification
2005/03/08

Issued Date

2006/03/08

Deciphered Date

4

3

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

2

Size Document Number
Custom 401412
Date:

,

R ev
B
Sheet

09, 2006
1

24

of

55


5

4

3

2

+3VS

1

U16C

1

D

1

+ C461
2

C468
0.1U_0402_16V4Z

C462

C463

1

C464

1

C465

1

C466

1

C467

220U_D2_4VM

2
2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z

1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z

1

2

1

C469

1

C470

1

1

2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z

+1.8VS

2

C471

0.1U_0402_16V4Z

VCC_SB=1.8V WHEN SB460

M13
M17
N12
N15
N18
R13
R17
U12
U15
U18
V13
V17

1

1
1
1
1
C473
C474
C475
C476
C472
22U_0805_6.3V6M
1U_0402_6.3V4Z

2
2
2
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z

C

+3VALW

C477
22U_0805_6.3V6M
+1.8VALW

R815

1

2

+USB_PHY_18
1

C478

1

C479

1

2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z

2
0_0805_5%
C480
22U_0805_6.3V6M

1

2

C481

1

C482

1

C483

1

C484

1

CPU_PWR=1.2V WHEN SB460
+5VS

R364
1K_0402_5%
1
2

+3VS

D4
CH751H-40_SC76
2
1

B

+1.2V_HT
V5_VREF

2

C485

C486

L24
+1.8VS

0.1U_0402_16V4Z

1
2
MBK1608800YZF_0805

2

1

1
1U_0402_6.3V4Z

1

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6

G4
H1
H2
H3

S5_1.8V_1
S5_1.8V_2
S5_1.8V_3
S5_1.8V_4

C487
2.2U_0603_6.3V6K

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22

VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52

VSS_53
VSS_54
VSS_55
VSS_56
VSS_57

Part 3 of 4

USB_PHY_1.8V_1
USB_PHY_1.8V_2
USB_PHY_1.8V_3
USB_PHY_1.8V_4
USB_PHY_1.8V_5

AA27

CPU_PWR

AE11

V5_VREF

A24

AVDDCK

A22

NC

B22

AVSSCK

V29
V28
V27
V26
V25
V24
V23
V22
U27
T29
T28
T27
T24
T21
P27

PCIE_VSS_42
PCIE_VSS_41
PCIE_VSS_40
PCIE_VSS_39
PCIE_VSS_38
PCIE_VSS_37
PCIE_VSS_36
PCIE_VSS_35
PCIE_VSS_34
PCIE_VSS_33

PCIE_VSS_32
PCIE_VSS_31
PCIE_VSS_30
PCIE_VSS_29
PCIE_VSS_28

2

SB460

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12

A2
A7
F1
J5
J7
K1

A18
A19
B19
B20
B21

2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15

VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28

POWER

A25
A28
C29
D24
L9
L21
M5
P3
P9
T5
V9
W2
W6
W21

W29
AA12
AA16
AA19
AC4
AC23
AD27
AE1
AE9
AE23
AH29
AJ2
AJ6
AJ26

PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15

PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27

A1
A20
A21
A29
B1
B7
B25
C21
C22
C24
D6
E24
F2
F23
G1
J1
J8

L6
L8
M9
M12
M15
M18
N13
N17
P1
P6
P21
R12
R15
R18
T6
T9
U13
U17
V3
V8
V12
V15
V18
V21
W1
W9
Y29
AA11
AA14
AA18

AC6
AC24
AD9
AD23
AE3
AE27
AG6
AJ1
AJ25
AJ29

D

C

D27
D28
D29
F26
G23
G24
G25
H27
J23
J26
J28
K27
L22
L23
L24

L27
L28
M21
M24
M27
N27
N28
P22
P23
P24
P25
P26

B

218S4RASA11GS SB460_BGA549

A

A

Compal Secret Data

Security Classification
2005/03/08

Issued Date

2006/03/08

Deciphered Date

4

3

Compal Electronics, inc.
SCHEMATIC, M/B LA-3151P

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

2

Size Document Number
Custom 401412
Date:

,

R ev
B
Sheet

09, 2006

1

25

of

55