Acer aspire 3690 5630 5650 5680 COMPAL LA 2921p HBL50 REV 0 3

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Compal Confidential
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HBL50 Schematics Document
Intel Yonah Processor with 945GM/945PM + DDRII + ICH7M
(With nVIDIA G73M/72MV)

2005-11-08
REV: 0.3

3

3

4

4

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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B

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Title

Cover Page
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
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59


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Compal Confidential
page 47

Clock Generator
ICS9LPRS325

Thermal Sensor
F75383M

Yonah

Fan Control

Model Name : HBL50
File Name : LA-2921

E

page 4

uPGA-478 Package

page 14

page 4,5
1

DVI-D Conn.

LCD Conn.

CRT & TV-out

page 23

page 25

H_A#(3..31)

Memory BUS(DDRII)

LVDS
SDVO

CH7307C
DVI

H_D#(0..63)

page 24

DVI
page 25

1

PSB
533/667MHz

Intel 945PM/GM

Dual Channel

uFCBGA-1466

1.8V DDRII 400/533

LVDS
PCI-Express

200pin DDRII-SO-DIMM X2
BANK 0, 1, 2, 3

page 6,7,8,9,10,11

nVidia G73M/(72M)/72MV

with 64/128/256MB VRAM

DMI

New Card
Socket page

page 15,16,17,18,19,20,21,22

LAN(GbE)
BCM5789

37

MINI CARD x2

page 34

PCI BUS

3.3V 33 MHz
IDSEL:AD16
(PIRQE#,
GNT#2,
REQ#2)

IDSEL:AD18
(PIRQG/H#,
GNT#3,
REQ#3)

IEEE 1394
VT6311S
page 38

IDSEL:AD17
(PIRQF#,
GNT#3,
REQ#3)

Intel ICH7-M

IDSEL:AD20
(PIRQA#,
GNT#2,
REQ#2)

Mini PCI
socket

LAN (10/100)

(WLAN)
(TV-Tuner)

page 34

3.3V ATA-100

page 26,27,28,29

USB port 0, 2

USB port5

USB port 1

2

HD Audio

IDE

S-ATA

CDROM
Conn.
page 31

ENE CB714
page 32

Bluetooth
Conn page 42

page 37

USB port 3, 7

3.3V 24.576MHz/48Mhz

BGA-652

CardBus

BCM4401E

3.3V 48MHz

USB conn x4

page 36

PCI Express
2

page 12,13

port 0

port 0

MDC 1.5
Conn
page 42

HDA Codec
ALC883
page 44

page 36

RJ45

1394 Conn.
page 38

Slot 0

page 35

page 33

6 in 1
socket

S-ATA HDD
Conn.page 30

page 33

HDD
Conn.
page

SATA-to-IDE
SPIF3811-HV096
page 30

30

Audio AMP
LPC BUS

Subwoofer

page 45

page 46

3

3

RTC CKT.

ENE KB910Q

page 43

page 40

Power On/Off CKT.
page 43

Super I/O

TPM1.2

SMsC LPC47N207

SLB9635 TT 1.2

page 39

Phone Jack x3
page 45

page 39

Switch/B Conn.
USB port4, 6

page 42

Int.KBD

Touch Pad

page 43

FIR

page 41

TFDU6102-TR3

DC/DC Interface CKT.
page 48

Power Circuit DC/DC
page 49,50,51,52
53,54,55,56

CD-PLAY/B Conn.
page 42

page 39

BIOS

EC I/O Buffer

page 41

page 41

MEDIA/B Conn.
page 42

CIR
page 42

4

4

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Block Diagrams
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
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of

59


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SIGNAL

STATE

Voltage Rails

1

E

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

+VALW

+V

+VS

Clock

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

ON

Power Plane

Description

S1

S3

S5

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

VIN

Adapter power supply (19V)

N/A

N/A

N/A

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

+0.9VS

0.9V switched power rail for DDR terminator

ON

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

+1.05VS

1.05V switched power rail

ON

OFF

OFF

+1.5VS

1.5V switched power rail

ON

OFF

OFF

+1.8V

1.8V power rail for DDR

ON

ON

OFF

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+2.5VS

2.5V switched power rail

ON

OFF

OFF

Vcc
Ra/Rc/Re

+3VALW

3.3V always on power rail

ON

ON

ON*

Board ID

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

0
1
2
3
4
5
6
7

Full ON

1

Board ID / SKU ID Table for AD channel

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V

3.300 V

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

2

2

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

BOARD ID Table
Board ID
0
1
2
3
4
5
6
7

External PCI Devices

Device

IDSEL#

CardBus(SD)

Interrupts

AD20

2

PIRQA/PIRQB

13 94

AD16

0

PIRQE

LAN(10/100)

AD17

3

PIRQF

Mini-PCI(WLAN/TV-Tuner) AD18

1

PIRQG/PORQH

EC SM Bus1 address
3

REQ#/GNT#

Device

Address

Smart Battery

0001 011X b

EEPROM(24C16/02)

1010 000X b

GMT G781-1

1001 101X b

EC SM Bus2 address
Device

SKU ID
0
1
2
3
4
5
6
7

1001 100X b

ICH7M SM Bus address
Device

Address

Clock Generator
(ICS9LPRS325AKLFT_MLF72)

1101 001Xb

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 010Xb

PCB Revision
0.1

BTO Item
BOM Structure
VGA
PM@ + VGA@
GM@
UMA
UMA's DVI
7307@
LAN(10/100)
4401@
5789@
LAN(GIGA)
MINI CARD1
MINI1@
MINI CARD2
MINI2@
SATA-to-IDE
3811@
PATA
PATA@
GRAPEVINE
GRA@
G72MV Only
G72@
G73 Only
G73@
VRAM

X76@
VRAM 64M
64@
VRAM 128M
64@+128@
VRAM 256M
64@+128@+256@
MEDIA/B
MEDIA@
CIR
CIR@
FIR
FIR@
GENEVA
GEN@
LCM
LCM@
Sub-woofer
SUB@
5789&5787
8789@
4401&5789
0189@
VP1020
VP1020@
INTERNAL MIC
INTMIC@
1394
1394@
SATA HDD

SATA@

SKU ID Table

Address

Fintek F75383M

BTO Option Table

SKU
PM
GM

4

2005/06/20

Issued Date

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification

3

D

Title

Notes List
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
E

3

of

59


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2

H_D#[0..63]

JP18A
H_A#[3..31]

6 H_A#[3..31]

D

H_REQ#[0..4]

6 H_REQ#[0..4]

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30

H_A#31

J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2

Y1

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#

A31#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

K3
H2
K2
J3
L5

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

L2
V4

ADSTB0#
ADSTB1#

6 H_ADSTB#0
6 H_ADSTB#1

C

14 CLK_CPU_BCLK
14 CLK_CPU_BCLK#

A22
A21

6 H_ADS#
6 H_BNR#
6 H_BPRI#
6 H_BR0#
6 H_DEFER#
6 H_DRDY#
6 H_HIT#
6 H_HITM#

H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1

6 H_LOCK#
6 H_RESET#

H_RS#[0..2]

6 H_RS#[0..2]

H_IERR#
H_RESET#
H_RS#0
H_RS#1
H_RS#2

6 H_TRDY#

T5
T3
T1
T4

B

PAD
PAD
PAD
PAD

28 ITP_DBRESET#
6 H_DBSY#
27 H_DPSLP#
27,56 H_DPRSTP#
6 H_DPWR#
PAD

T2

27 H_PWRGOOD
6 H_CPUSLP#

6,27 H_THERMTRIP#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

F3
F4
G3
G2

AD4
AD3
AD1
AC4

ITP_DBRRESET# C20
E1
B5
E5
D24
ITP_BPM#4
AC2
ITP_BPM#5

AC1
H_PROCHOT# D21

YONAH

ADDR GROUP

BCLK0
BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#

DATA GROUP

HOST CLK

CONTROL

RS0#
RS1#

RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

MISC

H_PW RGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

D6
D7

AC5
AA6
AB3
C26
D25
AB5
AB6

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMDA
THERMDC

A24
A25
C7

THERMDA DIODE
THERMDC
THERMTRIP#

THERMAL

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#

D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#

D59#
D60#
D61#
D62#
D63#

E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23

P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25

AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18

H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48

H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

1

H_D#[0..63] 6

+3VS
C624
0.1U_0402_16V4Z
1
2

U37

1
C625

2200P_0402_50V7K

2

D

1

VDD

SCLK

8

EC_SMB_CK2 40

THERMDA

2

D+

SDATA

7

EC_SMB_DA2 40

THERMDC

3

D-

ALERT#

6

GND

5

4

THERM#

ADM1032ARMZ-2REEL_MSOP8
F75383M_MSOP8

+1.05VS

C

DINV0#
DINV1#
DINV2#
DINV3#

J26
M26

V23
AC20

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

H23
M24
W24
AD23
G22
N25
Y25
AE24

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1

A6
A5
C4
B3
C6
B4

H_A20M# 27
H_FERR# 27
H_IGNNE# 27
H_INIT# 27
H_INTR 27
H_NMI 27

STPCLK#
SMI#

D5

A3

H_STPCLK# 27
H_SMI# 27

LEGACY CPU

6
6
6
6

ITP_TDI

R15

2

1

56_0402_5%

ITP_TDO

R17

2

1

56_0402_5%

ITP_TMS

R16

2

1

56_0402_5%

H_PROCHOT#

R500

2

1

75_0402_5%

ITP_BPM#5

R18

2

1

56_0402_5%

H_IERR#

R501

2

1

56_0402_5%

ITP_TRST#

R19

2

1

56_0402_5%

ITP_TCK

R20

2

1

56_0402_5%

TEST1

R513

2

1 @ 1K_0402_5%

TEST2

R512

2

1

B

51_0402_5%

6
6
6
6
6
6
6
6

FOX_PZ47903-2741-42_YONAH
A

A

Layout Note:
THERMDA & THERMDC Trace / Space = 10 / 10 mil
2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Yonah (1/2)
Size Document Number
Custom

Rev
0.3

HBL50 LA-2921P

Date:

Sheet

Friday, November 11, 2005
1

4

of

59


5

4

3

2

1

Layout Note:
Route VCCSENSE and VSSSENSE traces at 27.4Ohms
with 50 mil spacing.
Place PU and PD wihin 1 inch of CPU.

D

100_0402_1%
100_0402_1%

2
2
56 VSSSENSE

VCCSENSE
VSSSENSE

20mils

10U_0805_10V4Z

1

1

2

2

VCCA

K6
J6
M6
N6
T6
R6
K21
J21
M21
N21
T21
R21
V21
W21
V6
G21

VCCP
VCCP
VCCP

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

56 PSI#

AE6

PSI#

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

AD6
AF5

AE5
AF4
AE3
AF2
AE2

VID0
VID1
VID2
VID3
VID4
VID5
VID6

+1.05VS

C626

0.01U_0402_16V7K

Layout Note:
Place C14 near Pin B26

56
56
56
56
56
56
56

1

+1.05VS

R511
1K_0402_1%
2

C

1
R510

VCCSENSE
VSSSENSE

B26

+1.5VS
C628

AF7
AE7

GTL_REF0

2
2K_0402_1%
14 CPU_BSEL0

14 CPU_BSEL1
14 CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

+CPU_CORE

BSEL2

BSEL1

BSEL0

BCLK

0

0

1

133

0

1

1

166

B

R515 1

2

27.4_0402_1%

COMP0

R514 1

2

54.9_0402_1%

COMP1

R13

1

2

27.4_0402_1%

COMP2

R14

1

2

54.9_0402_1%

COMP3

AD26

GTLREF

B22
B23
C21

BSEL0
BSEL1
BSEL2

R26
U26
U1
V1

COMP0

COMP1
COMP2
COMP3

E7
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17
D2
F6
D3
C1
AF1
D22
C23
C24
AA1
AA4
AB2

AA3
M4
N5
T2
V3
B2
C3
T22
B25

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

+CPU_CORE

+CPU_CORE

JP18B

56 VCCSENSE
R499 1
R498 1

YONAH

POWER, GROUNG, RESERVED SIGNALS AND NC

+CPU_CORE

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

RSVD
RSVD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB26
AA25

AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11

AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6

P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

JP18C

3 x 330uF(9mOhm/3)
1

1

1

+ C614
+ C609
+ C621
@
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
2
2
2

South Side Secondary
+CPU_CORE

3 x 330uF(9mOhm/3)
1

1

1

+ C620

+ C608
+ C619
@
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9
2
2
2

North Side Secondary
+CPU_CORE

1

C31

22U_0805_6.3V6M
1
C33

2
22U_0805_6.3V6M

1

C35

22U_0805_6.3V6M
1
C32

1

C30

22U_0805_6.3V6M
1
C28

2

2
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
(Place these capacitors on South side,Secondary Layer)

2

1

C26

22U_0805_6.3V6M
1
C24

2
22U_0805_6.3V6M

2

+CPU_CORE

1

22U_0805_6.3V6M
1
C618

1

C623

2
22U_0805_6.3V6M

22U_0805_6.3V6M
1
C613

1

C616

C22

22U_0805_6.3V6M
1
C20

2
2

2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
(Place these capacitors on South side,Secondary Layer)

2

+CPU_CORE

1

22U_0805_6.3V6M
1
C607

1

C611

2
22U_0805_6.3V6M

C29

22U_0805_6.3V6M
1
C27

1

C25

22U_0805_6.3V6M
1
C23

2
2
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
(Place these capacitors on North side,Secondary Layer)

2

+CPU_CORE

1

C21

22U_0805_6.3V6M
1
C19

2
22U_0805_6.3V6M

2

1

22U_0805_6.3V6M
1
C617

1

C622

22U_0805_6.3V6M
1
C612

1

C615

22U_0805_6.3V6M
1
C606

C610

2
2
2
2

2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
(Place these capacitors on North side,Secondary Layer)

+CPU-CORE
Decoupling
SPCAP,Polymer

C,uF

ESR, mohm

6X330uF

9m ohm/6

1.8nH/6

MLCC 0805 X5R

32X22uF

3m ohm/32

0.6nH/32

2

ESL,nH

+1.05VS
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

AE18
AE17
AB15
AA15
AD15
AC15
AF15
AE15
AB14
AA13
AD14
AC13
AF14
AE13
AB12
AA12
AD12
AC12
AF12

AE12
AB10
AB9
AA10
AA9
AD10
AD9
AC10
AC9
AF10
AF9
AE10
AE9
AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18

F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10
B9
A10
A9
D10
D9
C10
C9
F10

F9
E10
E9
B7
A7
F7

1
FOX_PZ47903-2741-42_YONAH

C13
220U_D2_2VMR15

TRACE CLOSELY CPU < 0.5'

+
2

1

1

C34

2

C36

2

1

C38

2

0.1U_0402_16V4Z

COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms)
COMP1, COMP3 layout : Space 25mils (55Ohms)

1

C37

2

1

C16

2

0.1U_0402_16V4Z

1

2

C18

1

1

C17
@

2

0.1U_0402_16V4Z

C15
@

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

YONAH

POWER, GROUND

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19

B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26

R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

D

C

B

FOX_PZ47903-2741-42_YONAH

2
0.1U_0402_16V4Z

A

A

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Yonah (2/2)
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
1

5

of

59


5

4

3

2

1

945GM(A-3)(QK56)[QS]: SA0000059D0(ABO!)
945PM(A-3)(QK58)[QS]: SA00000KD70(ABO!)

R532
54.9_0402_1%
1
2

HVREF0
HVREF1
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING

R529
24.9_0402_1%
2
1

R531
24.9_0402_1%
2
1

B

HADSTB#0
HADSTB#1

B9
C13

H_ADSTB#0
H_ADSTB#1

HCLKN
HCLKP

AG1
AG2

CLK_MCH_BCLK#
CLK_MCH_BCLK

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3

HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

K4
T7
Y5
AC4
K3
T6
AA5
AC5

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

J7
W8
U3
AB10

H_DINV#0
H_DINV#1

H_DINV#2
H_DINV#3

HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6

A7
E3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRD Y#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

HRS0#
HRS1#
HRS2#

B4
E6
D6

H_RS#0
H_RS#1
H_RS#2

HDINV#0
HDINV#1
HDINV#2
HDINV#3

DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3

28
28
28
28

DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3

28
28
28
28

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

28
28
28
28

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

H_REQ#[0..4] 4

H_ADSTB#0 4
H_ADSTB#1 4

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

R47

R46
4
4
4
4

H_RESET# 4
H_ADS# 4
H_TRDY# 4
H_DPWR# 4
H_DRDY# 4
H_DEFER# 4
H_HITM# 4
H_HIT# 4
H_LOCK# 4
H_BR0# 4
H_BNR# 4
H_BPRI# 4
H_DBSY# 4
H_CPUSLP# 4

1
1

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMI_MTX_IRX_N0

DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

AE37
AF41
AG37
AH41

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

AC37
AE41
AF37
AG41

DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
SM_CK1

SM_CK2
SM_CK3

12
12
13
13

DDRA_CLK0#
DDRA_CLK1#
DDRB_CLK0#
DDRB_CLK1#

AW35
AT1
AY7
AY40

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

12
12
13
13

DDRA_CKE0
DDRA_CKE1

DDRB_CKE0
DDRB_CKE1

AU20
AT20
BA29
AY29

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

DDRA_SCS#0
DDRA_SCS#1
DDRB_SCS#0
DDRB_SCS#1

AW13
AW12
AY21
AW21

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

PAD
PAD

M_OCDOCMP0
M_OCDOCMP1

DDRA_ODT0
DDRA_ODT1
DDRB_ODT0
DDRB_ODT1
2 80.6_0402_1%
2 80.6_0402_1%

SMRCOMPN
SMRCOMPP

SM_OCDCOMP0
SM_OCDCOMP1

BA13
BA12
AY20
AU21

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

AK1
AK41

SMVREF

PM_BMBUSY#
G28
PM_EXTTS#0
F25
PM_EXTTS#1
H26
H_THERMTRIP#
G6
4,27 H_THERMTRIP#
GMCH_PWROK AH33
PLTRST_R#
AH34
1
2
26,28,31,34,39,40 PLT_RST#
R128
100_0402_1%
K28
26 MCH_ICH_SYNC#
28 PM_BMBUSY#
12,13 PM_EXTTS#0

AG33
AF33

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

D_REF_CLKN
D_REF_CLKP

A27
A26

CLK_DREF_96M#
CLK_DREF_96M

D_REF_SSCLKN
D_REF_SSCLKP

C40
D41

CLK_DREF_SSC#
CLK_DREF_SSC

H32

MCH_CLKREQ#

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7

CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

CLK_REQ#

AL20
AF10

AV9
AT9

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG3
PAD
CFG4
PAD
CFG5

CFG6
PAD
CFG7
CFG8
PAD
CFG9
CFG10
PAD
CFG11
CFG12
CFG13
CFG14
PAD
CFG15
PAD
CFG16
CFG17
PAD
CFG18
CFG19
CFG20

G_CLKP
G_CLKN

AY35
AR1
AW7
AW40

12
12
13
13

+1.8V

AC35
AE39
AF35
AG39

DDRA_CLK0
DDRA_CLK1
DDRB_CLK0
DDRB_CLK1

T17
T6

4
4
4
4
4
4
4
4

DMI_ITX_MRX_P0

DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3

12
12
13
13

12
12
13
13

CLK_MCH_BCLK# 14
CLK_MCH_BCLK 14

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

K16
K18
J18
F18
E15
F15
E18
D19

D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26

CFG

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

28
28
28
28

AE35
AF39
AG35

AH39

CLK

D8
G8
B8
F8
A8

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

Description at page10

U40B
DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3

NC0
NC1
NC2
NC3
NC4
NC5

NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2

B41
C41
D1

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27

A35

NC

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28

H_A#29
H_A#30
H_A#31

SM_RCOMPN
SM_RCOMPP
SM_VREF0
SM_VREF1
PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#

PM

J13
H_VREF
K13
H_XRCOMP E1
H_XSCOMP E2
H_YRCOMP Y1
H_YSCOMP U1
H_SWNG0
E4
H_SWNG1 W1

H9
C9

E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

HA3#
HA4#

HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

DDR MUXING

+1.05VS

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#

HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#

HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

DMI

C

F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3

U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1

AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8

HOST

D

R530
54.9_0402_1%
1
2

H_A#[3..31] 4

U40A
H_D#0
H_D#1

H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61

H_D#62
H_D#63

ICH_SYNC#

CALISTOGA_FCBGA1466~D
PM@

RESERVED

4 H_D#[0..63]

MCH_CLKSEL0 14
MCH_CLKSEL1 14
MCH_CLKSEL2 14
T15
T8
CFG5 10
T14
CFG7 10
T11
CFG9 10
T12
CFG11 10
CFG12 10
CFG13 10
T7
T13
CFG16 10
T9

CFG18 10
CFG19 10
CFG20 10

D

CLK_MCH_3GPLL 14
CLK_MCH_3GPLL# 14
CLK_DREF_96M# 14
CLK_DREF_96M 14
CLK_DREF_SSC# 14
CLK_DREF_SSC 14
MCH_CLKREQ# 14

C

B

Layout Note:
SMVREF trace
width and spacing
is 20/20.

H_RS#[0..2] 4

GMCH_PWROK

+1.8V

R127

1
R130
1

2

CALISTOGA_FCBGA1466~D
PM@

@ 0_0402_5%
VGATE
2

VGATE 14,28,56

0_0402_5%
SYS_PWROK
2

SYS_PWROK 28,43

+1.05VS

1

+1.05VS

+1.05VS
1
R527

2

221_0603_1%

R528
2

221_0603_1%

100_0402_1%

H_SWNG0

2

+3VS
R578
100_0402_1%

R111
10K_0402_5%
1
2

PM_EXTTS#0

28,56 PM_DPRSLPVR

1
R121

PM_EXTTS#1
2
0_0402_5%

R100
@ 10K_0402_5%
1
2
A

2005/09/20

H_SWNG1

1

2

0.1U_0402_16V4Z
C641

2
R526
1

2

100_0402_1%

1

0.1U_0402_16V4Z
C48

2
R44
1

2

100_0402_1%

1

0.1U_0402_16V4Z
C66

H_VREF

200_0603_1%

1
1
R53
2

A

R60

2

1

2

0.1U_0402_16V4Z
C46

SMVREF

1

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 10/20.

1

R577
100_0402_1%

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Calistoga (1/6)
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
1

6

of

59


5

4

3

2

1

DDRB_SDQ[0..63]

13 DDRB_SDQ[0..63]

12 DDRA_SMA[0..13]

D

DDRA_SDQ[0..63]

D

U40D
SA_BS0
SA_BS1
SA_BS2

12 DDRA_SDM[0..7]

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

C

12
12
12
12
12
12
12
12

DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7

DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7

AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

12
12
12

12
12
12
12
12

DDRA_SDQS0#
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS3#
DDRA_SDQS4#
DDRA_SDQS5#
DDRA_SDQS6#
DDRA_SDQS7#

DDRA_SDQS0#
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS3#
DDRA_SDQS4#
DDRA_SDQS5#
DDRA_SDQS6#
DDRA_SDQS7#

AK32
AU33
AN27
AM21
AM12
AL8

AN3
AH5

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13

AY16
AU14
AW16

BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

AY13
AW14
AY14

AK23
AK24

SA_CAS#
SA_RAS#
SA_WE#
SA_RCVENIN#
SA_RCVENOUT#

U40E
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19

SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49

SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

DDR SYS MEMORY A

AU12
AV14
BA20

12 DDRA_SBS0#
12 DDRA_SBS1#
12 DDRA_SBS2#

B

12 DDRA_SCAS#
12 DDRA_SRAS#
12 DDRA_SWE#

T18
T19

PAD
PAD

SA_RCVENIN#
SA_RCVENOUT#

DDRB_SMA[0..13]

13 DDRB_SMA[0..13]
DDRA_SMA[0..13]

check layout

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36

AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7

AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8

DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38

DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

AT24
AV23
AY28

SB_BS0
SB_BS1
SB_BS2

DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7

AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7

AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

DDRB_SDQS0#
DDRB_SDQS1#

DDRB_SDQS2#
DDRB_SDQS3#
DDRB_SDQS4#
DDRB_SDQS5#
DDRB_SDQS6#
DDRB_SDQS7#

AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4

DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13

AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4

SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

AR24
AU23
AR27
AK16
AK18

SB_CAS#
SB_RAS#
SB_WE#
SB_RCVENIN#
SB_RCVENOUT#

13 DDRB_SBS0#
13 DDRB_SBS1#
13 DDRB_SBS2#
13 DDRB_SDM[0..7]

13
13
13

13
13
13
13
13

DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7

13
13
13
13
13
13
13
13

DDRB_SDQS0#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQS3#
DDRB_SDQS4#
DDRB_SDQS5#

DDRB_SDQS6#
DDRB_SDQS7#

13 DDRB_SCAS#
13 DDRB_SRAS#
13 DDRB_SWE#
T10
T16

PAD
PAD

SB_RCVENIN#
SB_RCVENOUT#

DDR SYS MEMORY B

12 DDRA_SDQ[0..63]

check layout

CALISTOGA_FCBGA1466~D
PM@

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5

SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35

SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AK39

AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29

AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4

AK5
AJ5
AJ3

DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25

DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55

DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63

C

B

CALISTOGA_FCBGA1466~D
PM@

A

A

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Calistoga (2/6)
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
1

7

of

59


5

4

3

2

1

D

D

U40C

GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+

23 GMCH_TXOUT0+
23 GMCH_TXOUT1+
23 GMCH_TXOUT2+
23 GMCH_TXOUT023 GMCH_TXOUT123 GMCH_TXOUT2-

23 GMCH_TZOUT023 GMCH_TZOUT123 GMCH_TZOUT223
23
23
23
C

GMCH_TXCLK+
GMCH_TXCLKGMCH_TZCLK+
GMCH_TZCLK-

R108 GM@ 0_0402_5%
1
2 LBKLT_EN

15,40 ENBKL

23 GMCH_LCD_CLK
23 GMCH_LCD_DATA
23 GMCH_ENVDD

C37
B35
A37

LA_DATA#0
LA_DATA#1
LA_DATA#2

GMCH_TZOUT0+
GMCH_TZOUT1+
GMCH_TZOUT2+

F30
D29
F28

LB_DATA0
LB_DATA1
LB_DATA2

GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-

G30
D30
F29

LB_DATA#0
LB_DATA#1
LB_DATA#2

GMCH_TXCLK+
GMCH_TXCLKGMCH_TZCLK+
GMCH_TZCLK-

A32
A33
E26
E27

LA_CLK
LA_CLK#
LB_CLK
LB_CLK#

D32
J30
H30
H29
G26
G25
F32
B38
C35
C33
C32

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG

LVBG
LVREFH
LVREFL

A16
C18
A19

TVDAC_A
TVDAC_B
TVDAC_C

J20

TV_IREF

GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA
1
R82

2 TV_IREF
4.99K_0402_1%

B16
B18
B19
J29
K30

B

24 GMCH_CRT_VSYNC
24 GMCH_CRT_HSYNC
24 GMCH_CRT_B
24 GMCH_CRT_G
24 GMCH_CRT_R

GMCH_CRT_CLK
GMCH_CRT_DATA

2
R567
2
R565
2
R564

1
1
1

150_0402_1%
150_0402_1%
150_0402_1%
1
R91

2 CRT_IREF

255_0402_1%

TV_IRTNA
TV_IRTNB
TV_IRTNC
TV_DCONSEL1
TV_DCONSEL0

C26
C25

DDCCLK
DDCDATA

H23
G23
E23
D23
C22
B22
A21
B21

VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED

RED#

J22

CRT

24 GMCH_CRT_CLK
24 GMCH_CRT_DATA

TV

24 GMCH_TV_COMPS
24 GMCH_TV_LUMA
24 GMCH_TV_CRMA

LA_DATA0
LA_DATA1
LA_DATA2

GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-

LBKLT_EN
LCTLA_CLK
LCTLB_DATA
GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_ENVDD
LIBG

CRT_IREF

10mils
+3VS

A

R122 1

2 10K_0402_5%

GMCH_LCD_CLK

R104 1

2 10K_0402_5%

GMCH_LCD_DATA

R125 1

2 10K_0402_5%

LCTLB_DATA

R117 1

2 10K_0402_5%

LCTLA_CLK

R107 1

2 4.7K_0402_5%

GMCH_CRT_CLK

R94

1

2 4.7K_0402_5%

GMCH_CRT_DATA

R109 1

2 100K_0402_5%

LBKLT_EN

R576 1

2 1.5K_0402_1%

LIBG

R541 1

2 150_0402_1%

GMCH_TV_COMPS

R544 1

2 150_0402_1%

GMCH_TV_LUMA

R563 1

2 150_0402_1%

GMCH_TV_CRMA

EXP_COMPI
EXP_COMPO

LVDS

23 GMCH_TZOUT0+
23 GMCH_TZOUT1+
23 GMCH_TZOUT2+

B37
B34
A36

SDVOCTRL_DATA
SDVOCTRL_CLK

PCI-EXPRESS GRAPHICS

H27
H28

25 SDVO_SDAT
25 SDVO_SCLK

D40
D38

PEG_COMP

10mils

1
R138

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11

EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N7

PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_N15

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

D34
F38
G34
H38

J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15

EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36

AA40
AB36
AC40

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15

EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4

PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15

2

24.9_0402_1%

+1.5VS_PCIE

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]

PCIE_MTX_C_GRX_P[0..15] 15
PCIE_GTX_C_MRX_N[0..15] 15
PCIE_GTX_C_MRX_P[0..15] 15

C

C715 1

C710 1
C708 1
C706 1
C704 1
C702 1
C700 1
C743 1

C698
2 PM@ 0.1U_0402_16V4Z
C713
2 PM@ 0.1U_0402_16V4Z
C733
2 PM@ 0.1U_0402_16V4Z
C732
PM@
0.1U_0402_16V4Z
2
C729
2 PM@ 0.1U_0402_16V4Z
C727
2 PM@ 0.1U_0402_16V4Z
C725
2 PM@ 0.1U_0402_16V4Z
C723
PM@
0.1U_0402_16V4Z
2

1

C697
0.1U_0402_16V4Z
C714
0.1U_0402_16V4Z
C734
0.1U_0402_16V4Z
C731
0.1U_0402_16V4Z
C730
0.1U_0402_16V4Z
C728
0.1U_0402_16V4Z
C726
0.1U_0402_16V4Z
C724
0.1U_0402_16V4Z

1

C716 1

2 PM@

C711 1

2 PM@

C709 1

2 PM@

C707 1

2 PM@

C705 1

2 PM@

C703 1

2 PM@

C701 1

2 PM@

C744 1

2 PM@

2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7

2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N9
2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PM@
0.1U_0402_16V4Z
2
PCIE_MTX_C_GRX_N15

1
1
1
1
1
1
1

2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9

2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P12
PM@
0.1U_0402_16V4Z
2
PCIE_MTX_C_GRX_P13
2 PM@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15

1
1
1
1
1
1
1

B

CALISTOGA_FCBGA1466~D
PM@

PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1 C695 1

C696 1
2 7307@ 0.1U_0402_16V4Z

2 7307@ 0.1U_0402_16V4Z

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_P0

C209 1

C216 1
2 7307@ 0.1U_0402_16V4Z

2 7307@ 0.1U_0402_16V4Z

C239 1

C240 1
2 7307@ 0.1U_0402_16V4Z

2 7307@ 0.1U_0402_16V4Z

C241 1

C242 1
2 7307@ 0.1U_0402_16V4Z

2 7307@ 0.1U_0402_16V4Z

C234 1

C235 1
2 7307@ 0.1U_0402_16V4Z

2 7307@ 0.1U_0402_16V4Z

PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P3

2005/06/20

Issued Date

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

SDVO_INT# 25
SDVO_INT 25
SDVOB_R# 25
SDVOB_R 25
SDVOB_G# 25

SDVOB_G 25
SDVOB_B# 25
SDVOB_B 25
A

SDVOB_CLK# 25
SDVOB_CLK 25

Compal Electronics, Inc.

Compal Secret Data

Security Classification

5

PCIE_MTX_C_GRX_N[0..15] 15

2

Title

Calistoga (3/6)
Size
B
Date:

Document Number

Rev

0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
1

8

of

59


5

4

+1.05VS

D7
@ RB751V_SOD323
2
1

R101
@ 10_0402_5%
1
2

+2.5VS

+1.5VS

D6
@ RB751V_SOD323
2
1

R93
@ 10_0402_5%
1
2

+3VS

3

2

1

+2.5VS

2

+1.5VS
A

AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

E19
F19
C20
D20
E20
F20

C196
0.1U_0402_16V4Z

C683
0.1U_0402_16V4Z

+2.5VS

2005/09/21

C194
0.1U_0402_16V4Z

C722
10U_0805_10V4Z

C712
10U_0805_10V4Z

+

2

C690
2

330U_D2E_2.5VM

close pin G41

1

+ C887
2

2

220U_D2_4VM

CRTDAC: Route caps within
250mil of Alviso. Route FB
within 3" of Calistoga

+3VS_TVDACC

(120mA)
+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC

1

1

2

2

1

2

+3VS_TVDACA

1

2

+3VS
L5
MBK1608301YZF_0603
2
1
2005/09/19
1

2

1
+ C49
2

220U_D2_4VM

C

+2.5VS

+3VS_TVBG

+3VS
L7
MBK1608301YZF_0603
2
1

C85
0.1U_0402_16V4Z

1

+3VS_TVDACB

1

2

+3VS
L4
MBK1608301YZF_0603
2
1

1

2

AH1 (150mA) +1.5VS
AH2

close pin A38
(20mA)

2

1

2
2

1

2

+1.5VS_3GPLL

1

2

+1.5VS

1

2

R112
0_0603_5%
2
1

1

@

2

+1.5VS_MPLL

R517
0_0603_5%
2
1

45mA Max.
1

2

+1.5VS

+1.5VS_TVDAC

1

2

1

R568
0_0603_5%
2
1

1

2

2

@

+1.5VS_HPLL
+1.5VS

1

2

2

B

1

2

R516
0_0603_5%
2
1

45mA Max.
1

+1.5VS

C672
0.1U_0402_16V4Z

1

1

C94
0.022U_0402_16V7K

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28

AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+3VS

(40mA)

PCI-E/MEM/PSB PLL decoupling
C119
0.1U_0402_16V4Z

A23
B23
B25

+3VS
R90
0_0603_5%
2
1

+1.5VS_TVDAC

C140
0.1U_0402_16V4Z

+3VS_TVBG

D21 (24mA)
H19

C139
10U_0805_10V4Z

A28
B28
C28

C141
0.1U_0402_16V4Z

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8

VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

2

C93
0.022U_0402_16V7K

AF2 (45mA)

H20
G20

1

C84
0.022U_0402_16V7K

+1.5VS_MPLL

VCCA_MPLL
VCCA_TVBG
VSSA_TVBG

330U_D2E_2.5VM

C92
0.1U_0402_16V4Z

+2.5VS

2

2

C105
0.022U_0402_16V7K

A38 (10mA)
B39

2

1

L8
MBK1608301YZF_0603
2
1

1

2

C687

+2.5VS
2

C106
0.1U_0402_16V4Z

VCCA_LVDS
VSSA_LVDS

VCCHV0
VCCHV1
VCCHV2

VCCAUX32

VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

1
+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

VCCD_TVDAC
VCCDQ_TVDAC

2

+2.5VS_CRTDAC

B26 (50mA)
C39 (50mA)
AF1 (45mA)

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

1

E21 (70mA)
F21
G21

2

1

+

+1.5VS

1

C631
10U_0805_10V4Z

1

+1.5VS_3GPLL
+2.5VS
(2mA)

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL

VCCD_HMPLL0
VCCD_HMPLL1

2

1

1

L45
MBK1608301YZF_0603
2
1

+1.5VS

1

C638
0.1U_0402_16V4Z

MCH_D2
C633
0.22U_0603_16V7K

2

2

C739
220U_D2_2VMR15

+

C636
10U_0805_10V4Z

1

1

C632
0.47U_0603_16V4Z
MCH_AB1

C630
0.22U_0603_16V7K

B

P O W E R

1

C637
0.1U_0402_16V4Z

C643
0.47U_0603_16V4Z

MCH_A6

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

(1500mA)

+1.5VS

C180
0.1U_0402_16V4Z

2

AC33
G41
H41

R580
0_0805_5%
2
1

C109
0.1U_0402_16V4Z

1

VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG

+1.5VS_PCIE

W=60 mils

C195
0.01U_0402_16V7K

2

AB41
AJ41
L41
N41
R41
V41
Y41

C108
0.022U_0402_16V7K

1

C67
2.2U_0805_10V6K

C627
4.7U_0805_10V4Z

C

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

+2.5VS

+1.5VS_DPLLB

L46
MBK1608301YZF_0603
2
1

1
2
C117
0.1U_0402_16V4Z

(60mA)
B30
C30
A30

C118
0.022U_0402_16V7K

2

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

H22

C127
10U_0805_10V4Z

220U_D2_2VMR15

+

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13

VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43

VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
VTT66
VTT67
VTT68
VTT69
VTT70
VTT71
VTT72
VTT73

VTT74
VTT75
VTT76

C111
0.1U_0402_16V4Z

1
C629

VCC_SYNC
AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13

R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8

M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1

C68

0.1U_0402_16V4Z

+1.05VS

(800mA)

D

+1.5VS_DPLLA

U40H

C107
0.1U_0402_16V4Z

D

+1.5VS

1

2

A

CALISTOGA_FCBGA1466~D
PM@

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Calistoga (4/6)
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
1

9

of

59


5

4

3

2

1

Strap Pin Table

CFG[3:17] have internal pull up

1
C41
220U_D2_2VMR15

+
2

1
+
C40
@
220U_D2_2VMR15
2

B

+1.05VS

M19
L19
N18
M18
L18
P17
N17
M17
N16
M16

L16

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17
+1.8V

VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110

VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107

AR6
AP6
AN6
AL6
AK6
AJ6
AV1 MCH_AV1
AJ1 MCH_AJ1

CALISTOGA_FCBGA1466~D
PM@

1

2

1

2

Place near pin AV1 & AJ1

CFG[19:18] have internal pull down
MCH_AT41
MCH_AM41

011
001

1

2

C717
0.47U_0603_16V4Z

CFG[2:0]

1

2

CFG5
CFG7

0 = Reserved
1 = Mobile Yonah CPU*(Default)

CFG9

0 = Lane Reversal Enable
1 = Normal Operation*(Default)

CFG11

0 = Reserved

Place near pin AT41 & AM41

2

1

2

C129
0.1U_0402_16V4Z

1

C86
0.1U_0402_16V4Z

2

C121
0.1U_0402_16V4Z

2

1

1 = Calistoga
00
01
10
11

CFG[13:12]

1

= 667MT/s FSB
= 533MT/s FSB

0 = DMI x 2
1 = DMI x 4 *(Default)

PSB 4X CLK Enable

C75
0.1U_0402_16V4Z

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29

AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22

AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12

AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

C718
0.47U_0603_16V4Z

C640
0.22U_0603_16V7K

C

P O W E R

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3

VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8
VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33

VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63

VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93

VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

=
=
=
=

D

*

Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation *(Default)

CFG16

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled *(Default)

CFG18

0 = 1.05V
1 = 1.5V

CFG19

0 = Normal Operation * (Default)
1 = DMI Lane Reversal Enable

*(Default)

0 = No SDVO Device Present *
(Default)

SDVO_CTRLDATA

1 = SDVO Device Present

CFG20
(PCIE/SDVO select)

0 = Only PCIE or SDVO is
operational. *(Default)
1 = PCIE/SDVO are operating
simu.

C

1

2

6 CFG5

6 CFG7
6 CFG9

Place near pin BA23

1

2

C719
10U_0805_10V4Z

2

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15

VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45

VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75

VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

C679
0.47U_0603_16V4Z

2

1

AA33
W33
P33
N33
L33
J33
AA32
Y32
W32
V32
P32
N32
M32
L32
J32
AA31
W31
V31
T31
R31
P31
N31
M31
AA30
Y30
W30
V30
U30

T30
R30
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
P28
N28
M28
L28
P27
N27
M27
L27

P26
N26
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
M22
L22
AC21
AA21
W21
N21
M21
L21

AC20
AB20
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19

C720
10U_0805_10V4Z

1

2

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23

AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16

W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

+1.8V

U40G

2005/09/20

6 CFG12

1
1

2

6 CFG13

+ C735
2

6 CFG11

6 CFG16

330U_D2E_2.5VM_R9

R58

1

2 @

2.2K_0402_5%

R81

1

2 @

2.2K_0402_5%

R67

1

2 @

2.2K_0402_5%

R57

1

2 @

2.2K_0402_5%

R59

1

2 @

2.2K_0402_5%

R69

1

2 @

2.2K_0402_5%

R68

1

2 @

2.2K_0402_5%

R92

1

2 @ 1K_0402_5%

R95

1

2 @ 1K_0402_5%

R118

1

2 @ 1K_0402_5%

+3VS
C650
0.47U_0603_16V4Z

2

2

1

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22

VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52

VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

C634
0.47U_0603_16V4Z

1

1

C43
1U_0603_10V4Z

2

C42
0.22U_0603_16V7K

1

C44
10U_0805_10V4Z

C45
10U_0805_10V4Z

C639

0.22U_0603_16V7K

D

VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25

VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55

VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72

P O W E R

(3500mA)

AD27
AC27
AB27
AA27
Y27
W27
V27
U27

T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24

T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18

Y18
W18
V18
U18
T18

+1.05VS

+1.5VS

U40F

C635
0.47U_0603_16V4Z

+1.05VS

6 CFG18
6 CFG19

1

6 CFG20

B

2

Place near pin BA15

CALISTOGA_FCBGA1466~D
PM@

A

A

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Calistoga (5/6)
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
1

10

of

59


5

4

3

2

U40I
AC41
AA41
W41
T41
P41
M41
J41
F41
AV40
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39

AJ39
AC39
AB39
AA39
Y39
W39
V39
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
AB37
AA37
Y37

W37
V37
T37
R37
P37
N37
M37
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35

W35
V35
T35
R35
P35
N35
M35
L35
J35
H35
G35
F35
D35
AN34
AK34
AG34
AF34

D

C

B

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5

VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35

VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95

VSS96
VSS97
VSS98
VSS99

1

U40J

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118

VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148

VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178

VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33

Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29

T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26

D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21

AV21
AR21

AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18

AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13

AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
J11
D11
B11
AV10
AP10
AL10
AJ10

VSS200
VSS201
VSS202
VSS203
VSS204
VSS205

VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235

VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS265
VSS264
VSS263

VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291

VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322

VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352

VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7

AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4

J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

D

C

B

CALISTOGA_FCBGA1466~D
PM@

CALISTOGA_FCBGA1466~D
PM@

A

A

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Calistoga (6/6)
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
1

11

of

59


5

4

+1.8V

DDRA_SDQS0#
DDRA_SDQS0
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ8
DDRA_SDQ14

D

7 DDRA_SDQS1#
7 DDRA_SDQS1

DDRA_SDQS1#
DDRA_SDQS1
DDRA_SDQ9
DDRA_SDQ15

DDRA_SDQ16
DDRA_SDQ17
7 DDRA_SDQS2#
7 DDRA_SDQS2

DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ29
DDRA_SDQ24
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27

6 DDRA_CKE0
C

7 DDRA_SBS2#

DDRA_CKE0
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

7 DDRA_SBS0#
7 DDRA_SWE#
7 DDRA_SCAS#
6 DDRA_SCS#1
6 DDRA_ODT1

DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#
DDRA_SCS#1
DDRA_ODT1
DDRA_SDQ37
DDRA_SDQ36

7 DDRA_SDQS4#
7 DDRA_SDQS4

DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ35
DDRA_SDQ32
DDRA_SDQ40
DDRA_SDQ44
DDRA_SDM5

B

DDRA_SDQ41
DDRA_SDQ46

DDRA_SDQ49
DDRA_SDQ48

7 DDRA_SDQS6#
7 DDRA_SDQS6

DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ54
DDRA_SDQ50
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDM7
DDRA_SDQ59
DDRA_SDQ58

13,14 D_CK_SDATA
13,14 D_CK_SCLK

D_CK_SDATA
D_CK_SCLK
+3VS

41
43
45
47
49
51
53

55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113

115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173

175
177
179
181
183
185
187
189
191
193
195
197
199

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1

VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9

A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42

DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

***
VSS
DQ4
DQ5
VSS

DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#

DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS

DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7

VSS
DQ62
DQ63
VSS
SAO
SA1

+1.8V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104

106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164

166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDRA_SDQ6
DDRA_SDQ0

1

1
3
5
7
9
11

13
15
17
19
21
23
25
27
29
31
33
35
37
39

R153
DDRA_SDM0
1K_0402_1%
DDRA_SDQ5
DDRA_SDQ7

20mils

2

7 DDRA_SDQS0#
7 DDRA_SDQS0

1

+DIMM_VREF
1

DDRA_SDQ4
DDRA_SDQ1

2

DDRA_SDQ13
DDRA_SDQ12

1

DDRA_SDM1

2

1

C281
0.1U_0402_16V4Z

2

C294

R156

2.2U_0805_10V6K

1K_0402_1%

D

2

JP22
+DIMM_VREF

3

+1.8V

DDRA_CLK0 6
DDRA_CLK0# 6
DDRA_SDQ11
DDRA_SDQ10

7 DDRA_SMA[0..13]
DDRA_SDQ20
DDRA_SDQ21
R119 1
DDRA_SDM2

7 DDRA_SDQ[0..63]
0_0402_5%
2

7 DDRA_SDM[0..7]

DDRA_SMA[0..13]
DDRA_SDQ[0..63]
DDRA_SDM[0..7]

PM_EXTTS#0 6,13

+1.8V

DDRA_SDQ23
DDRA_SDQ22
1

DDRA_SDQ28
DDRA_SDQ25
DDRA_SDQS3#
DDRA_SDQS3

2

1

C53
2.2U_0805_10V6K

2

1

C123
2.2U_0805_10V6K

2

1

C125
2.2U_0805_10V6K

2

C54
2.2U_0805_10V6K

+1.8V

DDRA_SBS2#
1
DDRA_CKE0
2
RP41

DDRA_SMA4
DDRA_SMA2
DDRA_SMA0

DDRA_ODT0
DDRA_SMA13

2

+0.9VS

DDRA_CKE1 6

DDRA_SMA11
DDRA_SMA7
DDRA_SMA6

DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS#0

1

DDRA_SDQS3# 7
DDRA_SDQS3 7

DDRA_SDQ31
DDRA_SDQ30
DDRA_CKE1

C71
2.2U_0805_10V6K

DDRA_SBS1# 7
DDRA_SRAS# 7
DDRA_SCS#0 6
DDRA_ODT0 6

DDRA_SDQ39

DDRA_SDQ38

4
3
56_0404_4P2R_5%

1

C115

DDRA_SMA9
1
DDRA_SMA12
2
RP39

4
3
56_0404_4P2R_5%

DDRA_SMA5
DDRA_SMA8

1
2
RP37

4
3
56_0404_4P2R_5%

DDRA_SMA1
DDRA_SMA3

1
2
RP35

4
3
56_0404_4P2R_5%

+0.9VS

DDRA_SBS0#
1
DDRA_SMA10
2
RP33

4
3
56_0404_4P2R_5%

1

DDRA_SCAS#
1
DDRA_SWE#
2

RP31

4
3
56_0404_4P2R_5%

2

DDRA_ODT1
1
DDRA_SCS#1
2
RP29

4
3
56_0404_4P2R_5%

DDRA_CKE1
1
DDRA_SMA11
2
RP12

4
3
56_0404_4P2R_5%

2

0.1U_0402_16V4Z

C645
0.1U_0402_16V4Z

1

2

1

2

1

C113
0.1U_0402_16V4Z

2

1

C648
0.1U_0402_16V4Z

2

1

C62

0.1U_0402_16V4Z

2

1

C653
0.1U_0402_16V4Z

2

C

C63
0.1U_0402_16V4Z

1

C660
0.1U_0402_16V4Z

2

C667
0.1U_0402_16V4Z

DDRA_SDM4
DDRA_SDQ34
DDRA_SDQ33

+0.9VS

DDRA_SDQ45
DDRA_SDQ43
DDRA_SDQS5#
DDRA_SDQS5

DDRA_SDQS5# 7
DDRA_SDQS5 7

DDRA_SDQ47
DDRA_SDQ42
DDRA_SDQ52
DDRA_SDQ53
DDRA_CLK1 6
DDRA_CLK1# 6
DDRA_SDM6
DDRA_SDQ51
DDRA_SDQ55
DDRA_SDQ57
DDRA_SDQ56
DDRA_SDQS7#
DDRA_SDQS7

DDRA_SDQS7# 7
DDRA_SDQS7 7

1

2

C671
0.1U_0402_16V4Z

DDRA_SMA7
DDRA_SMA6

1
2
RP10

4
3
56_0404_4P2R_5%

DDRA_SMA4
DDRA_SMA2

1
2
RP8

4
3
56_0404_4P2R_5%

+0.9VS

DDRA_SMA0
1

DDRA_SBS1#
2
RP6

4
3
56_0404_4P2R_5%

1

DDRA_SRAS#
1
DDRA_SCS#0
2
RP4

4
3
56_0404_4P2R_5%

DDRA_ODT0
1
DDRA_SMA13
2
RP2

4
3
56_0404_4P2R_5%

2

C80
0.1U_0402_16V4Z

1

2

1

2

1

C678
0.1U_0402_16V4Z

2

1

C88
0.1U_0402_16V4Z

2

1

C104

0.1U_0402_16V4Z

2

1

C69
0.1U_0402_16V4Z

2

C76
B

0.1U_0402_16V4Z

C95
0.1U_0402_16V4Z

DDRA_SDQ62
DDRA_SDQ63
R23 1
R21 1

2 10K_0402_5%
2 10K_0402_5%

P-TWO_A5692A-A0G16-N

Change PCB Footprint

DIMM0 STD H:9.2mm (BOT)

A

A

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

DDRII-SODIMM0
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
1

12

of

59


A

B

+1.8V
JP21
+DIMM_VREF
DDRB_SDQ0
DDRB_SDQ1
7 DDRB_SDQS0#
7 DDRB_SDQS0

DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9

1

7 DDRB_SDQS1#
7 DDRB_SDQS1

DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11

DDRB_SDQ17
DDRB_SDQ20
7 DDRB_SDQS2#

7 DDRB_SDQS2

DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ28
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ30
DDRB_SDQ31

6 DDRB_CKE0
2

7 DDRB_SBS2#

DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

7 DDRB_SBS0#
7 DDRB_SWE#
7 DDRB_SCAS#
6 DDRB_SCS#1

6 DDRB_ODT1

DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS#1
DDRB_ODT1
DDRB_SDQ32
DDRB_SDQ33

7 DDRB_SDQS4#
7 DDRB_SDQS4

DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5

3

DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49

7 DDRB_SDQS6#

7 DDRB_SDQS6

DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ51
DDRB_SDQ50
DDRB_SDQ56
DDRB_SDQ61
DDRB_SDM7
DDRB_SDQ59
DDRB_SDQ58

12,14 D_CK_SDATA
12,14 D_CK_SCLK

D_CK_SDATA
D_CK_SCLK
+3VS

C

D

E

+1.8V

1
3
5

7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65

67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125

127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185

187
189
191
193
195
197
199

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16

DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD

A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST

VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

***
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12

DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1

VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44

DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

+DIMM_VREF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54

56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114

116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174

176
178
180
182
184
186
188
190
192
194
196
198
200

+1.8V

DDRB_SDQ5
DDRB_SDQ4
1

DDRB_SDM0
C263
DDRB_SDQ6
DDRB_SDQ7

1

C276

1

1

C39 +

2.2U_0805_10V6K
2
2
0.1U_0402_16V4Z

C290 +

C78

1

1

C89

1

C79

C90

1

@ 150U_D2_6.3VM
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2
2
2
2
2
2
330U_D2E_2.5VM_R9
0.1U_0402_16V4Z
0.1U_0402_16V4Z

DDRB_SDQ12
DDRB_SDQ13
1

DDRB_SDM1
DDRB_CLK1 6
DDRB_CLK1# 6
DDRB_SDQ14
DDRB_SDQ15

DDRB_SDQ21
DDRB_SDQ16
R120 1
DDRB_SDM2

7 DDRB_SMA[0..13]
0_0402_5%
2

7 DDRB_SDQ[0..63]
PM_EXTTS#0 6,12
7 DDRB_SDM[0..7]

DDRB_SMA[0..13]
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
+1.8V

DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ26
DDRB_SDQ24

1

C50
DDRB_SDQS3#
DDRB_SDQS3

DDRB_SDQS3# 7
DDRB_SDQS3 7

C55

1

C124

1

C126

1

1

C70

2.2U_0805_10V6K
2.2U_0805_10V6K
2.2U_0805_10V6K
2
2
2
2
2
2.2U_0805_10V6K
2.2U_0805_10V6K

DDRB_SDQ29
DDRB_SDQ27
DDRB_CKE1

DDRB_CKE1 6

+0.9VS

+1.8V
2

DDRB_SBS2#
DDRB_CKE0

DDRB_SMA11
DDRB_SMA7
DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS#0
DDRB_ODT0
DDRB_SMA13

DDRB_SBS1# 7
DDRB_SRAS# 7
DDRB_SCS#0 6
DDRB_ODT0 6

1
2
RP13

4
3
56_0404_4P2R_5%

DDRB_SMA9

DDRB_SMA12

1
2
RP11

4
3
56_0404_4P2R_5%

DDRB_SMA5
DDRB_SMA8

1
2
RP9

4
3
56_0404_4P2R_5%

DDRB_SMA1
DDRB_SMA3

1
2
RP7

4
3

56_0404_4P2R_5%

DDRB_SBS0#
DDRB_SMA10

1
2
RP5

4
3
56_0404_4P2R_5%

DDRB_SCAS#
DDRB_SWE#

1
2
RP3

4
3
56_0404_4P2R_5%

DDRB_ODT1
DDRB_SCS#1

1
2
RP1

4
3
56_0404_4P2R_5%

DDRB_CKE1
DDRB_SMA11

1
2
RP40

4
3
56_0404_4P2R_5%

DDRB_SMA7
DDRB_SMA6

1
2
RP38

4
3
56_0404_4P2R_5%

DDRB_SMA4
DDRB_SMA2

1
2
RP36

4
3
56_0404_4P2R_5%

DDRB_SMA0
DDRB_SBS1#

1
2
RP34

4
3
56_0404_4P2R_5%

DDRB_SRAS#
DDRB_SCS#0

1
2
RP32

4
3
56_0404_4P2R_5%

DDRB_ODT0
DDRB_SMA13

1
2
RP30

4
3
56_0404_4P2R_5%

DDRB_SDQ36
DDRB_SDQ37
DDRB_SDM4
DDRB_SDQ39
DDRB_SDQ38
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5

DDRB_SDQS5# 7
DDRB_SDQS5 7

DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_CLK0 6
DDRB_CLK0# 6

DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ57
DDRB_SDQS7#
DDRB_SDQS7

DDRB_SDQS7# 7
DDRB_SDQS7 7

1

C64

C61

1

C114

1

C116

1

0.1U_0402_16V4Z
0.1U_0402_16V4Z
2

2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z

+0.9VS

1

C669

C677

1

C647

1

C652

1

C659

1

0.1U_0402_16V4Z
0.1U_0402_16V4Z

2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

+0.9VS

1

C662

C87

1

C91

1

C97

1

C110

1

3

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z

+0.9VS

1

C65

C73

1

C77

1

0.1U_0402_16V4Z
0.1U_0402_16V4Z

2
2
2
0.1U_0402_16V4Z

DDRB_SDQ62
DDRB_SDQ63
1
R24 1
R22

2
2 10K_0402_5%
10K_0402_5%

+3VS

P-TWO_A5652C-A0G16

DIMM1 STD H:5.2mm (BOT)

4

4

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

DDRII-SODIMM1
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
E

13

of

59


A

B

FSLC

FSLB

FSLA

CLKSEL2

CLKSEL1

CLKSEL0

0

0

0

1

C

CPU SRC PCI
MHz MHz MHz

1

1

133

100

33.3

2

1

166

100

33.3

D

+CLK_VDD48

+CLK_VDDREF
1

C432
10U_0805_10V4Z

2

1

C444
0.047U_0402_16V7K

2

0
**SEL_PCI5/REF1

CLKREQ3#

33.3MHz PCICLK5

**SEL_PCI6/PCICLK1

CLKREQ5#

33.3MHz PCICLK6

**SEL_24M/PCICLK2

TESTMODE

24MHz Output

**SEL_48M/PCICLK3

CLKREQ7#

48MHz_1 Output

ITP_EN/PCICLK_F0

SRC pair

+CLK_VDD2

C466
33P_0402_50V8J
1
2

1
R376
1
R316

1

**SEL_24M/PCICLK2=0=TESTMODE
**SEL_PCI6/PCICLK1=0=CLKREQ5#

+3VS

CLK_REF
2
10K_0402_5%

1
R619

CLK_PCI0
2
10K_0402_5%

CLK_ICH_48M
CLK_SD_48M

28 CLK_ICH_48M
32 CLK_SD_48M

ITP_EN/PCICLK_F0=0=SRC pair

2 CLK_PCI4
10K_0402_5%

1
R711

39 CLK_PCI_SIO
36 CLK_PCI_MINI
34 CLK_PCI_LAN

2005/08/31

R288 1
R307 1

CLK_14M_SIO

39 CLK_14M_SIO

2

32 CLK_PCI_PCM
40 CLK_PCI_LPC
39 CLK_PCI_TPM
28 CLK_ICH_14M
6 CLK_DREF_96M
6 CLK_DREF_96M#
26 CLK_PCI_ICH

2 12_0402_5%
2 12_0402_5%

30
36

VDDPCI
VDDPCI

12

VDDCPU

R349 2

1 33_0402_5%

REF0/FSLC/TEST_SEL

3
S

10

CLK_CPU1# R372 1

2 0_0402_5%

CLK_MCH_BCLK
CLK_MCH_BCLK#

CPUCLKT0LP

14

CLK_CPU0

R375 1

2 0_0402_5%

CLK_CPU_BCLK

CPUCLKC0LP

13

CLK_CPU0# R374 1

2 0_0402_5%

CLK_CPU_BCLK#

R371 1 EXP@

2 0_0402_5%

CLK_PCIE_CARD

2 0_0402_5%

CLK_PCIE_CARD#

SRCCLKT9LP

3

SRCCLKC9LP

2

CLK_SRC9# R370 1 EXP@

72
70

CLK_SRC8

CLK_PCI_PCM

R338 1

2 33_0402_5%

CLK_PCI2

32

SEL_24M/PCICLK2

SRCCLKC8LP

69

CLK_SRC8# R365 1 MINI2@ 2 0_0402_5%

CLK_PCI_LPC
CLK_PCI_TPM

R345 1
R344 1 @

2 33_0402_5%
2 12_0402_5%

CLK_PCI1

27

SEL_PCI6/PCICLK1

CLKREQ8#

71

SRCCLKT7LP

66

SRCCLKC7LP

67

R659 1

2 10K_0402_5%

2 33_0402_5%
2 0_0402_5%

CLK_DOT

43

DOTT_96MHz/27MHz_Nonspread
CLKREQ7#/48Mhz_1

38

CLK_DREF_96M#

R305 1

2 0_0402_5%

CLK_DOT#

44

DOTC_96MHz/27MHz_spread

SRCCLKT6LP

63

CLK_SRC6

R355 1

2 0_0402_5%

CLK_PCIE_SATA

R308 1

2 33_0402_5%

CLK_PCI0

64

CLK_SRC6# R361 1

2 0_0402_5%

37

SRCCLKC6LP

CLK_PCIE_SATA#

CLK_PCI_ICH

CLKREQ6#

62

SRCCLKT5LP

60

CLK_SRC5

SRCCLKC5LP

61

CLK_SRC5# R351 1

CLKREQ5#/PCICLK6

29

R637 1

SEL_PCI5/REF1

ITP_EN/PCICLK_F0
VTT_PWRGD#/PD
GND

2005/10/18

VGATE 6,28,56

1

3

D

S
Q38
2N7002_SOT23

D_CK_SCLK

Q14
2N7002_SOT23

+1.05VS

2 10K_0402_5%
CLK_PCIE_ICH
2 0_0402_5%
2 0_0402_5%

CLK_PCIE_CARD 37

58

CLK_SRC4

59

CLK_SRC4# R340 1 8789@ 2 0_0402_5%

CLKREQ4#

57

R336 1 8789@ 2 0_0402_5%

R640 1

SMBDAT
SRCCLKT3LP

55

CLK_SRC3

4

GNDSRC

SRCCLKC3LP

56

CLK_SRC3# R329 1 VGA@ 2 0_0402_5%

15

GNDCPU

CLKREQ3#/PCICLK5

28

CLK_PCI5

21

GNDREF

SRCCLKT2LP

52

CLK_SRC2

CLK_SRC2# R299 1

R323 1 VGA@ 2 0_0402_5%

2 0_0402_5%

GNDPCI

SRCCLKC2LP

53

35

GNDPCI

CLKREQ2#

26

42

GND48

SRCCLKT1LP

50

CLK_SRC1

68

GNDSRC

SRCCLKC1LP

51

CLK_SRC1# R301 1 MINI1@ 2 0_0402_5%

CLKREQ1#

46

73
74
75
76

THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD

CLK_PCIE_ICH# 28

CLK_PCIE_LAN 34
CLK_PCIE_LAN# 34
+3VS

CLK_PCIE_VGA
CLK_PCIE_VGA#

LCD100/96/SRC0_TLP

47

CLK_SRC0

LCD100/96/SRC0_CLP

48

CLK_SRC0# R303 1

CLK_MCH_3GPLL#

CLK_PCIE_MINI1#

2 10K_0402_5%
+3VS
CLK_DREF_SSC
2 0_0402_5%
2 0_0402_5%

CLK_DREF_SSC#

CLK_PCIE_VGA

1
R322
1
R328
CLK_PCIE_MINI2 1
R366
CLK_PCIE_MINI2# 1
R364
CLK_PCIE_ICH

1
R346
CLK_PCIE_ICH#
1
R350
CLK_PCIE_MINI1 1
R283
CLK_PCIE_MINI1# 1
R282
CLK_PCIE_SATA 1
R354
CLK_PCIE_SATA# 1
R360
CLK_DREF_SSC 1
R285
CLK_DREF_SSC# 1
R284
CLK_DREF_96M
1
R287
CLK_DREF_96M# 1
R286
CLK_PCIE_CARD 1
R381
CLK_PCIE_CARD# 1
R380
CLK_MCH_3GPLL 1
R281
CLK_MCH_3GPLL# 1
R280

CLK_PCIE_LAN
1
R335
CLK_PCIE_LAN# 1
R339

2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%

2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%

CLK_PCIE_VGA#

CLK_PCIE_ICH 28

R639 1
2 10K_0402_5%
+3VS
CLK_PCIE_MINI1
R302 1 MINI1@ 2 0_0402_5%

R626 1
R304 1

CLK_PCIE_MINI2# 36

SATA_CLKREQ# 28

CLK_PCIE_LAN#

2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2
@ 49.9_0402_1%
2

CLK_PCIE_SATA# 27

CLK_PCIE_LAN

1
R383
CLK_MCH_BCLK# 1
R382
CLK_CPU_BCLK
1
R385
CLK_CPU_BCLK# 1
R384

CLK_PCIE_MINI2 36

+3VS

R636 1
2 @ 10K_0402_5%
+3VS
R334 2 1394@ 1
33_0402_5% CLK_PCI_1394
R300 1
CLK_MCH_3GPLL
2 0_0402_5%

31

EXP_CLKREQ# 37

+3VS

2 @ 10K_0402_5%

17

CLK_PCIE_CARD# 37

CLK_PCIE_SATA 27

CLK_PCIE_ICH#

2 10K_0402_5%

SRCCLKT4LP

ICS9LPR325AKLFT_MLF72
G72@

+1.05VS

R647 1
R347 1

SRCCLKC4LP

SMBCLK

CLK_CPU_BCLK# 4

MINI2_CLKREQ# 36

R306 1

D_CK_SDATA

2

CLK_MCH_BCLK# 6

+3VS

R353 1

16

C440
10U_0805_10V4Z

CLK_CPU_BCLK 4

CLK_PCIE_MINI2#

CLK_DREF_96M

D_CK_SCLK

2

1

+3VS

1

CLK_MCH_BCLK 6

R658 1
2 10K_0402_5%
+3VS
R367 1 MINI2@ 2 0_0402_5%
CLK_PCIE_MINI2

CLK_ICH_14M

9

C460

0.047U_0402_16V7K
2

1

CLK_MCH_BCLK
CLK_SRC9

CLKREQ9#

2
G

S

2
G
D
2
G
1

11

SRCCLKT8LP

R386
4.7K_0402_5%
1
2
+3VS

D

28,34,36,37 ICH_SMBCLK

CPUCLKT1LP
CPUCLKC1LP

SEL_48M/PCICLK3

CLK_ENABLE#

+3VS

2 0_0402_5%

PCICLK4/FCTSEL1

CLKIREF

1

PM_STP_CPU# 28

R373 1

33

2 0_0402_5%

R315
0_0805_5%
1
2

40mil
C457

CLK_CPU1

34

Q15
2N7002_SOT23

2005/08/31

PM_STP_CPU#

5

23

39

C475
0.047U_0402_16V7K

PM_STP_PCI# 28

CLK_PCI3

12,13 D_CK_SDATA

28,34,36,37 ICH_SMBDATA

24

CPUCLKC2_ITP/SRCCLKC10LP

FSLB/TEST_MODE/24Mhz

22

2

+CLK_VDD1

C476
0.047U_0402_16V7K

CLK_PCI4

12,13 D_CK_SCLK

D_CK_SDATA

2

1
2
R379
2.2_0603_5%

R326 1 FIR@ 2 12_0402_5%
R327 1
2 12_0402_5%
R333 1 4401@ 2 33_0402_5%

+3VS

3

CPU_STOP#

6

3

1

PM_STP_PCI#

CPUCLKT2_ITP/SRCCLKT10LP
USB_48MHz/FSLA

CLK_REF

1
C469
0.047U_0402_16V7K

0.047U_0402_16V7K

25

X2

45

15mil

R387
4.7K_0402_5%
1
2
+3VS

2

2

+CLK_VDD2

+CLK_VCCA
1

C483
10U_0805_10V4Z

PCI_SRC_STOP#

X1

41

2005/10/18
CLK_ENABLE#
2
10K_0402_5%

8

1
C443
0.047U_0402_16V7K

VDD48

CLKSEL1
CLKSEL2

GNDA

2

CLK_PCI_SIO
CLK_PCI_MINI
CLK_PCI_LAN

R657 1

1
R620

19

VDDA

7

VDDREF

CLKSEL0

CLK_ENABLE#

56 CLK_ENABLE#

+3VS

VDDSRC
VDDSRC
VDDSRC

VDDSRC

20

CLK_XTALOUT

1
C477
0.047U_0402_16V7K

20mil

14.31818MHz_20P_1BX14318BE1A

2

1
R712

CLK_XTALIN

2

1

18
2 +CLK_VDDREF
1_0603_5%
15mil
40

2 +CLK_VDD48
2.2_0603_5%
15mil

Y3
C468
33P_0402_50V8J
1
2

**SEL_PCI5=1=PCICLK5

1
C452
10U_0805_10V4Z

U19

CPU_ITP pair
+CLK_VDD1

2

H

Clock Generator

+CLK_VDD1

1

1
49
54
65

G

40mil

0.047U_0402_16V7K

+CLK_VDD1

1

F

R377
0_0805_5%
1
2

+3VS

C474

Table : ICS9LPR325
1

E

CLK_PCIE_VGA 15
CLK_PCIE_VGA# 15
CLK_PCI_1394 38
CLK_MCH_3GPLL 6
CLK_MCH_3GPLL# 6
MCH_CLKREQ# 6
CLK_PCIE_MINI1 36

3

CLK_PCIE_MINI1# 36
MINI1_CLKREQ# 36
CLK_DREF_SSC 6
CLK_DREF_SSC# 6

+1.05VS

1
2
R616
@ 1K_0402_5%

R622
1K_0402_5%
1
2
1
R615

0_0402_5%

2

MCH_CLKSEL0 6
CPU_BSEL0 5

CLKSEL1
1
R617
@ 0_0402_5%

2

R625
1K_0402_5%
1
2
1
R618
0_0402_5%

2

2

R624
@ 1K_0402_5%

G72M:SLG8LP465VTR: SA00000TS00

R643
8.2K_0402_5%
CLKSEL2 1
2

MCH_CLKSEL1 6

1
R646
@ 0_0402_5%

CPU_BSEL1 5

2

1

2

R623
@ 56_0402_5%

1

4

R621
8.2K_0402_5%
CLKSEL0 1
2

1

2

G73M: ICS9LPR325CKLFT_MLF72: SA00000RE20
R638
@ 1K_0402_5%
R645
1K_0402_5%
1
2
1
R642
0_0402_5%

2

CPU_BSEL2 5

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

4

MCH_CLKSEL2 6

2005/06/20

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

E

F

Title

Clock Generator
Size
B

Document Number

Rev
0.3

HBL50 LA-2921P

Date:

Friday, November 11, 2005
G

Sheet

14
H

of

59


5

4

3

2

1

U42A

1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1

2
1
2
1
2

2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z
2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z
2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z
2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z
2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z
2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z
2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z
2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z
2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z
2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z
2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z
2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z

2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z
2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z
2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z
2 VGA@ 0.1U_0402_16V4Z
VGA@ 0.1U_0402_16V4Z
14 CLK_PCIE_VGA
14 CLK_PCIE_VGA#
26 PLTRST_VGA#

PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N2
PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N3
PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N4
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N5
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N7
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8

PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N10
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N15

AJ15
AK15
AH16
AG16
AG17
AH17
AG18
AH18
AK18
AJ18
AJ19
AH19
AG20
AH20
AG21

AH21
AK21
AJ21
AJ22
AH22
AG23
AH23
AK24
AJ24
AJ25
AH25
AH26
AG26
AK27
AJ27
AJ28
AH27

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N

PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

CLK_PCIE_VGA
CLK_PCIE_VGA#

AH14
AJ14

PEX_REFCLK
PEX_REFCLK_N

PLTRST_VGA#

AH15

PEX_RST_N

AM12
AM11

B

+3VS

2 VGA@ 10K_0402_5% A26
2 VGA@ 10K_0402_5% H2

TESTMEMCLK
TESTMODE

R574 1
R573 1

2 VGA@ 10K_0402_5% AJ11
AK12
2 @ 10K_0402_5%
AL12
AK11
2 @ 10K_0402_5%
2 VGA@ 10K_0402_5% AL13

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_N

R572 1
R575 1
C686 1
@
C682 1
@

IFPAB_VPROBE
2
0.01U_0402_16V7K
IFPCD_VPROBE
2
0.01U_0402_16V7K
XTALIN
XTALOUT

AM4
AK3

1

IN

GND

2

27MHZ_16PF_X7S027000BG1H-U
VGA@
1

2005/09/23

2

AC3
AC1
AC2
AB2
AB1
AA1
AB3
AA3
AC5
AB5
AB4
AA5

MIOB_HSYNC
MIOB_VSYNC
MIOB_DE
MIOB_CTL3

AF3

AE3
AD1
AD3

MIOB_CLKIN
MIOB_CLKOUT
MIOB_CLKOUT_N

AE4
AD4
AD5

U1
U2

XTALIN
XTALOUT

T2

XTALOUTBUFF

T1

XTALSSIN

R78

2 2K_0402_5%
VGA@

1

PEX_PLL_TERM
SUB_VENDOR

R96

PEX_CFG1 18
PEX_CFG2 18

2
VGA@ 2K_0402_5%
2
@ 2K_0402_5%

RAM_CFG0
RAM_CFG1
CRYSTAL_0
PCI_DEVID2
PCI_DEVID0
PCI_DEVID1
CRYSTAL_1
MOBILE_MODE
RAM_CFG2
RAM_CFG3

+3VS

RAM_CFG0 18

RAM_CFG1 18
CRYSTAL_0 18
PCI_DEVID2 18
PCI_DEVID0 18
PCI_DEVID1 18
CRYSTAL_1 18
MOBILE_MODE 18
RAM_CFG2 18
RAM_CFG3 18

PCI_DEVID3

R61

R570 1

1 10K_0402_5%
VGA@

2

2 @ 1K_0402_5%

AL5

IFPAB_RSET

VGA_DVI_TXC+
VGA_DVI_TXCVGA_DVI_TXD0+
VGA_DVI_TXD0VGA_DVI_TXD1+

VGA_DVI_TXD1VGA_DVI_TXD2+
VGA_DVI_TXD2-

AM2
AM3
AE2
AE1
AF1
AF2
AG1
AH1
AG3
AH2
AK1
AJ1
AL2
AL1
AJ2
AJ3

IFPC_TXC
IFPC_TXC_N
IFPC_TXD0
IFPC_TXD0_N
IFPC_TXD1
IFPC_TXD1_N
IFPC_TXD2
IFPC_TXD2_N
IFPD_TXC
IFPD_TXC_N

IFPD_TXD4
IFPD_TXD4_N
IFPD_TXD5
IFPD_TXD5_N
IFPD_TXD6
IFPD_TXD6_N

AH3

IFPCD_RSET

PEX_CFG0 18

PEX_CFG1
PEX_CFG2

1
R562
1
R543

LVDSBC+
LVDSBCLVDSB0+
LVDSB0LVDSB1+
LVDSB1LVDSB2+
LVDSB2-

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0

IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

+3VS

PEX_PLL_TERM 18
SUB_VENDOR 18

PEX_CFG0

23 LVDSBC+
23 LVDSBC23 LVDSB0+
23 LVDSB023 LVDSB1+
23 LVDSB123 LVDSB2+
23 LVDSB2-

AK9
AJ9
AH6
AJ6
AH8
AH7
AJ8
AK8
AJ5
AH5
AK4
AL4
AM6
AM5
AM7
AL7
AK6
AK5
AK7
AL8

PCI_DEVID3 18

2 VGA@ 1 10K_0402_5%

25 VGA_DVI_TXC+
25 VGA_DVI_TXC25 VGA_DVI_TXD0+
25 VGA_DVI_TXD025 VGA_DVI_TXD1+
25 VGA_DVI_TXD125 VGA_DVI_TXD2+

25 VGA_DVI_TXD2-

R569 1

2 @ 1K_0402_5%

1

2

C664
VGA@
18P_0402_50V8J

A

R538
1
VGA@

VGA_TV_LUMA
VGA_TV_CRMA
VGA_TV_COMPS

close chip
2 VGA@ 150_0402_1%
2 VGA@ 150_0402_1%
2 VGA@ 150_0402_1%

VGA_CRT_R

VGA_CRT_G
VGA_CRT_B

R126 1
R131 1
R124 1

2 VGA@ 150_0402_1%
2 VGA@ 150_0402_1%
2 VGA@ 150_0402_1%

BUFRST_N
MEMSTRAPSEL0
MEMSTRAPSEL1
MEMSTRAPSEL2
MEMSTRAPSEL3
STEREO
STRAP
SWAPRDY_A
THERMDN
THERMDP

F3
AE26
AD26
AH31
AH32
T3
F1
M6

J1
K1

SERIAL

ROM_SCLK
ROM_SI
ROM_SO
ROMCS_N

D

FAE recommand 6/29

DD+

AA7
W2
AA6
AA4

C

Y2

DACA_HSYNC
DACA_VSYNC
DACA_RED
DACA_BLUE
DACA_GREEN

DACA_IDUMP
DACA_RSET

AF10
AK10
AH11
AH12
AJ12
AG9
AH9

DACA_VREF

AH10

DACC_HSYNC
DACC_VSYNC
DACC_RED
DACC_BLUE
DACC_GREEN
DACC_IDUMP
DACC_RSET

AG7
AG5
AF6
AE5
AG6
AG4
AF5

DACC_VREF

AH4

DACB_RED
DACB_BLUE
DACB_GREEN
DACB_IDUMP
DACB_RSET

R6
T6
T5
V7
R7

DACB_VREF

R5

I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CH_SCL
I2CH_SDA

K2
J3
H4
J4
G2
G1
G3
H3

VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_CRT_R
VGA_CRT_B
VGA_CRT_G

VGA_CRT_HSYNC 24
VGA_CRT_VSYNC 24
VGA_CRT_R 24
VGA_CRT_B 24
VGA_CRT_G 24

DACA_RSET
DACAVREF

R571 1
2 124_0603_1%
VGA@
1
2
C155

0.01U_0402_16V7K
VGA@

+3VS

NVidia suggestion
OSC_OUT
VGA_TV_CRMA
VGA_TV_COMPS
VGA_TV_LUMA

VGA_TV_CRMA 24
VGA_TV_COMPS 24
VGA_TV_LUMA 24

DACB_RSET

R114 1
VGA@
DACBVREF
C130 1
VGA@
VGA_DDC_CLK
VGA_DDC_DATA
VGA_DVI_SCLK
VGA_DVI_SDATA
I2CC_SCL
I2CC_SDA

2 0.1U_0402_16V4Z

4

8

XOUT

NC

3

PD#

6

VSS

VGA@
1
R64

2 OSC_SPREAD
22_0402_5%

+3VS

NV43M_BGA820
G73@
OSC_SPREAD
OSC_OUT

Thermal sensor
R554
200_0402_5% I2C address
VGA@
1001 101x
U38
1 VCC
SMBCLK

2
1 D+
C666
2200P_0402_50V7K 3
D2 @
4
Close to Sensor

+3VS
R556 1
R555 1

XIN MODOUT

ASM3P1819N-SR_SO8
VGA@

VGA_DDC_CLK 24
VGA_DDC_DATA 24
VGA_DVI_SCLK 25

VGA_DVI_SDATA 25
I2CC_SCL 23
I2CC_SDA 23

I2CC_SCL
I2CC_SDA

1

2

2 124_0603_1%

C665
VGA@
0.1U_0402_16V4Z
2
1

R537
@ 10K_0402_5%

B

Spread spectrum
C60 1
2 0.1U_0402_16V4Z
VGA@
U3
7 VDD

REF 5

2 VGA@ 4.7K_0402_5%
2 VGA@ 4.7K_0402_5%

8

EC_SMB_CK1 40,41,45,53

DXP

SMBDATA

7

EC_SMB_DA1 40,41,45,53

DXN

ALERT

6

GND

5

THERM

THER_ALERT#

A

G781-1_SOP8
VGA@

2

2

B32
C20
D1
J6
U3
U4
U5
U6
V1
V3
V4
V5
V6
W1
W3
W4
W5
Y5
Y6
Y30
AC26

AG12
AH13
AM8
AM9
AM10

NV43M_BGA820
G73@
VGA termination,
R97 1
R102 1
R113 1

2
22_0402_5%

R540
@ 10K_0402_5%

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10

NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25

Part 4 of 6

NC

L2

MIOBD0
MIOBD1
MIOBD2
MIOBD3
MIOBD4
MIOBD5
MIOBD6
MIOBD7

MIOBD8
MIOBD9
MIOBD10
MIOBD11

THER_ALERT#

LVDSAC+
LVDSACLVDSA0+
LVDSA0LVDSA1+
LVDSA1LVDSA2+
LVDSA2-

LVDS/TMDS

MIOA_VREF

DVO / GPIO

M5
R4
P4

U42D
23 LVDSAC+
23 LVDSAC23 LVDSA0+
23 LVDSA023 LVDSA1+
23 LVDSA123 LVDSA2+
23 LVDSA2-

2

3

MIOA_CLKIN
MIOA_CLKOUT
MIOA_CLKOUT_N

PAD T20
ENVDD 23
ENBKL 8,40
POWER_SEL 57

1

OUT

1

C663
VGA@
18P_0402_50V8J

GND

R3
R1
P1
P3

IFPAB_VPROBE
IFPCD_VPROBE

Y5
4

MIOA_HSYNC
MIOA_VSYNC
MIOA_DE
MIOA_CTL3

MIOB_VREF

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

R579 1
R99 1

P2
N2
N1
N3
M1
M3
P5
N6
N5
M4
L4

L5

DVI_DET 25

NV_INVTPWM
ENVDD
ENBKL

GENERAL

C183
C191 1
C193
C204 1
C208
C214 1
C217
C225 1
C226
C236 1
C244
C250 1
C251
C256 1
C257
C264 1
C265
C274 1
C275
C278 1

C279
C282 1
C283
C291 1
C292
C295 1
C297
C299 1
C300
C308 1
C310
C316 1

MIOAD0
MIOAD1
MIOAD2
MIOAD3
MIOAD4
MIOAD5
MIOAD6
MIOAD7
MIOAD8
MIOAD9
MIOAD10
MIOAD11

DVI_DET

1

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14

PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

K3
H1
K5
G5
E2
J5
G6
K6
E1
D2
H5
F4
E3

DACs

C

PCIE_GTX_C_MRX_P[0..15]

8 PCIE_GTX_C_MRX_P[0..15]

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4

GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12

I2C

PCIE_GTX_C_MRX_N[0..15]

8 PCIE_GTX_C_MRX_N[0..15]

Part 1 of 6

PCI EXPRESS

8 PCIE_MTX_C_GRX_P[0..15]

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4

PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

TEST

PCIE_MTX_C_GRX_P[0..15]

AK13
AK14

AM14
AM15
AL15
AL16
AK16
AK17
AL17
AL18
AM18
AM19
AK19
AK20
AL20
AL21
AM21
AM22
AK22
AK23
AL23
AL24
AM24
AM25
AK25
AK26
AL26
AL27
AM27
AM28
AL28
AL29

CLK

PCIE_MTX_C_GRX_N[0..15]

8 PCIE_MTX_C_GRX_N[0..15]

D

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10

PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

If Spread spectrum not stuff than stuff resistor

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

G72/G73 Main
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
1

15

of

59


5

4

FBAD[0..63]

3

2

FBCD[0..63]

FBAD[0..63] 19,20

FBAA[0..12]

FBCD[0..63] 21,22

FBCA[0..12]

FBAA[0..12] 19,20

1

FBCA[0..12] 21,22

D

D

FBBA[2..5]

FBDA[2..5]

FBBA[2..5] 20

FBADQS[0..7]

FBCDQS[0..7]

FBADQS[0..7] 19,20

FBADQS#[0..7]

FBCDQM#[0..7]

FBADQM#[0..7] 19,20

FBCDQS#[0..7] 21,22
FBCDQM#[0..7] 21,22

U42C

FBADQS_WP0
FBADQS_WP1

FBADQS_WP2
FBADQS_WP3
FBADQS_WP4
FBADQS_WP5
FBADQS_WP6
FBADQS_WP7

L28
K31
G32
G28
AB28
AL32
AF32
AH30

FBADQS0
FBADQS1
FBADQS2
FBADQS3
FBADQS4
FBADQS5
FBADQS6
FBADQS7

E32

FB_VREF1

FB_VREF1

FBA_BA1 19,20

FBACAS# 19,20

1

+1.8VS

2

R587
1K_0402_1%
VGA@

FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_REFCLK
FBA_REFCLK_N
FBA_DEBUG

P28
R28
Y27
AA27
D32
D31
AC27

15mil
FBACLK0 19
FBACLK0# 19
FBACLK1 20
FBACLK1# 20

C752
VGA@
0.1U_0402_16V4Z

1

R588
1K_0402_1%
VGA@

2

FBA_DEBUG

NV43M_BGA820
G73@

PAD

T23

FBCDQM0
FBCDQM1

FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7

A4
E11
F5
C9
C28
F24
C24
E20

FBCDQM#0
FBCDQM#1
FBCDQM#2
FBCDQM#3
FBCDQM#4
FBCDQM#5
FBCDQM#6
FBCDQM#7

FBCDQS_RN0
FBCDQS_RN1
FBCDQS_RN2
FBCDQS_RN3
FBCDQS_RN4

FBCDQS_RN5
FBCDQS_RN6
FBCDQS_RN7

C6
E9
E6
A8
B29
E25
A25
F21

FBCDQS#0
FBCDQS#1
FBCDQS#2
FBCDQS#3
FBCDQS#4
FBCDQS#5
FBCDQS#6
FBCDQS#7

FBCDQS_WP0
FBCDQS_WP1
FBCDQS_WP2
FBCDQS_WP3
FBCDQS_WP4
FBCDQS_WP5
FBCDQS_WP6
FBCDQS_WP7

C5
E10
E5
B8
A29
D25
B25
F20

FBCDQS0
FBCDQS1
FBCDQS2
FBCDQS3
FBCDQS4
FBCDQS5
FBCDQS6
FBCDQS7

FB_VREF2

A28

FB_VREF2

FBC_CLK0
FBC_CLK0_N
FBC_CLK1
FBC_CLK1_N
FBC_REFCLK

FBC_REFCLK_N
FBC_DEBUG

E13
F13
F18
E17
B1
C1
F12

PAD T22
FBCCS0# 21,22
FBCWE# 21,22
FBC_BA0 21,22
2 FBCODT0
256@ 0_0402_5%

FBC_BA1 21,22

FB_VREF1=0.5 x FBVDD

C

FBCCAS# 21,22

+1.8VS

B

R582
1K_0402_1%
@
15mil

C736
@
0.1U_0402_16V4Z

PAD

1

R581
1K_0402_1%
@

2

T21

NV43M_BGA820
G73@

FB_VREF2=0.5 x FBVDD

1

FBCODT0
1

FBAODT0

R139
10K_0402_5%
VGA@

2

A

A

2

R186
10K_0402_5%
VGA@

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

R136
10K_0402_5%
256@

FBCRAS# 21,22

FBCCLK0 21
FBCCLK0# 21
FBCCLK1 22
FBCCLK1# 22
FBC_DEBUG

FBC_CKE 21,22
FBCODT0 21,22

1

FBADQS#0
FBADQS#1
FBADQS#2
FBADQS#3

FBADQS#4
FBADQS#5
FBADQS#6
FBADQS#7

FBARAS# 19,20

FBCA3
FBCA0
FBCA2
FBCA1
FBDA3
FBDA4
FBDA5
FBCCS1#
FBCCS0#
FBCWE#
FBC_BA0
FBC_CKE
CODT0 R140 1
FBDA2
FBCA12
FBCRAS#
FBCA11
FBCA10
FBC_BA1
FBCA8
FBCA9
FBCA6
FBCA5

FBCA7
FBCA4
FBCCAS#

2

M28
K32
G31
G27
AA28
AL31
AF31
AH29

R185
10K_0402_5%
VGA@

C13
A16
A13
B17
B20
A19
B19
B14
E16
A14
C15

B16
F17
C19
D15
C17
A17
C16
D14
F16
C14
C18
E14
B13
E15
F15
A20

1

FBADQS_RN0
FBADQS_RN1
FBADQS_RN2
FBADQS_RN3
FBADQS_RN4
FBADQS_RN5
FBADQS_RN6
FBADQS_RN7

FBA_CKE 19,20
FBAODT0 19,20

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26

Part 3 of 6

2

FBADQM#0
FBADQM#1
FBADQM#2
FBADQM#3
FBADQM#4
FBADQM#5
FBADQM#6
FBADQM#7

2 FBAODT0
64@ 0_0402_5%

FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14

FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44

FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63

1

M29
M30
G30
F29
AA29
AK30
AC30
AG30

PAD T24
FBACS0# 19,20
FBAWE# 19,20
FBA_BA0 19,20

B7
A7
C7
A2
B2
C4
A5
B5
F9
F10
D12
D9
E12
D11
E8
D8
E7
F7
D6
D5
D3
E4
C3
B4

C10
B10
C8
A10
C11
C12
A11
B11
B28
C27
C26
B26
C30
B31
C29
A31
D28
D27
F26
D24
E23
E26
E24
F23
B23
A23
C25
C23
A22
C22

C21
B22
E22
D22
D21
E21
E18
D19
D18
E19

2

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7

FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37

FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63

1

FBAA3

FBAA0
FBAA2
FBAA1
FBBA3
FBBA4
FBBA5
FBACS1#
FBACS0#
FBAWE#
FBA_BA0
FBA_CKE
AODT0 R183 1
FBBA2
FBAA12
FBARAS#
FBAA11
FBAA10
FBA_BA1
FBAA8
FBAA9
FBAA6
FBAA5
FBAA7
FBAA4
FBACAS#

2

P32
U27

P31
U30
Y31
W32
W31
T32
V27
T28
T31
U32
W29
W30
T27
V28
V30
U31
R27
V29
T30
W28
R29
R30
P29
U28
Y32

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3

FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26

1

Part 2 of 6

2

B

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27

FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57

FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

MEMORY INTERFACE A

C

N27
M27
N28
L29
K27
K28
J29
J28
P30
N31
N30
N32
L31
L30
J30
L32
H30
K30
H31

F30
H32
E31
D30
E30
H28
H29
E29
J27
F27
E27
E28
F28
AD29
AE29
AD28
AC28
AB29
AA30
Y28
AB30
AM30
AF30
AJ31
AJ30
AJ32
AK29
AM31
AL30
AE32

AE30
AE31
AD30
AC31
AC32
AB32
AB31
AG27
AF28
AH28
AG28
AG29
AD27
AF27
AE28

MEMORY INTERFACE B

U42B
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10

FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40

FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

FBCDQS[0..7] 21,22

FBCDQS#[0..7]

FBADQS#[0..7] 19,20

FBADQM#[0..7]

FBDA[2..5] 22

4

3

2

Title

G72/G73 Memory
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
1

16

of

59


5

4

2

+1.2VS

NV_PLLVDD
+VGA_CORE
U42E

VGA@
L11
+2.5VS MBK1608121YZF_0603
VGA@
4700P_0402_25V7K VID_PLLVDD
1
2

1

2

C184

VGA@

1

C174
VGA@

2

1

1

C175
VGA@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C185
VGA@

2

1

VGA@

2

0.1U_0402_16V4Z

1

C218

2

0.1U_0402_16V4Z

40mA
C172
VGA@
2.2U_0603_6.3V6K

C137
VGA@

2

1

C151
VGA@

2

1

4700P_0402_25V7K

2
470P_0402_50V7K

C223
VGA@

L47
+2.5VS MBK1608121YZF_0603
VGA@
4700P_0402_25V7K
1
2

1

2

C211
VGA@

0.1U_0402_16V4Z
1

C224
VGA@

2

1

VGA@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

C181

C190
VGA@

2

1

VGA@

2

0.1U_0402_16V4Z

1

C182

2

0.1U_0402_16V4Z

PLLVDD

30mA
C693
VGA@
2.2U_0603_6.3V6K

1

C150
VGA@

2

1

C149
VGA@

2

1

4700P_0402_25V7K

2

470P_0402_50V7K

+1.2VS

C

L16
MBK1608121YZF_0603
VGA@
1
2
C222
VGA@

2.2U_0603_6.3V6K

1

1

C189
VGA@

4700P_0402_25V7K

C202
VGA@

2

1

2

C219
VGA@

4700P_0402_25V7K

1

C201
VGA@

2

1

2

4700P_0402_25V7K

FBA_PLLAVDD

C259
VGA@

2

1

470P_0402_50V7K
1
1
1
C178
C163
C161

2
4700P_0402_25V7K

+3VS

VGA@ VGA@
10U_0805_10V4Z 2

2

VGA@

K16
K17
N13
N14
N16
N17
N19
N20
P13

P14
P16
P17
P19
R16
R17
NV_PLLVDD T13
T14
T15
T18
T19
U13
U14
U15
U19
V16
V17
W13
W14
W16
W17
W19
Y13
Y14
Y16
Y17
Y19
Y20
U18

470P_0402_50V7K
1
C210
VGA@

2
470P_0402_50V7K

2

4700P_0402_25V7K
0.022U_0402_16V7K 0.022U_0402_16V7K
1
1
1
1
1
1
C143
C132
C157
C165
C145
C138
VGA@

VGA@
VGA@
VGA@
VGA@

VGA@
2
2
2
2
2
2
4700P_0402_25V7K
0.022U_0402_16V7K 0.022U_0402_16V7K

+1.2VS
1

L10
MBK1608121YZF_0603
VGA@
2

C177
VGA@
2.2U_0603_6.3V6K

1

C147
VGA@

C661
FBC_PLLAVDD
1

1

VGA@
1U_0603_10V4Z 2

C156

1

VGA@

0.1U_0402_16V4Z
1
C164
VGA@

2
2
0.1U_0402_16V4Z

VID_PLLVDD
PLLVDD

40mA
30mA

P20
T20
T23

U20
U23
W20

VDD_LP_0
VDD_LP_1
VDD_LP_2
VDD_LP_3
VDD_LP_4
VDD_LP_5

H7
J7
K7
L7
L8
L10
M10
AC11
AC12
AC24
AD24
AE11
AE12

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4

VDD33_5
VDD33_6
VDD33_7
VDD33_8
VDD33_9
VDD33_10
VDD33_11
VDD33_12

T10
T9

FBA_PLLAVDD 30mA
FBC_PLLAVDD 30mA

G25
G10
G23
G8
+1.8VS
R152 1
K26
2
VGA@ 40.2_0402_1%
0.1U_0402_16V4Z
0.01U_0402_16V7K
0.01U_0402_16V7K
H16
H17
1

1
1
1
1
1
1
C98
C144
C148
C230
C252
C187
C200
J9
J10
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
J23
2
2
2
2
2
2
2

J24
4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.01U_0402_16V7K
0.01U_0402_16V7K
K9
K11
K12
K21
L9
K22
MBK1608121YZF_0603
K24
VGA@
L23
DACA_VDD
4700P_0402_25V7K
M23
1
2
T25
U25
1
1
1
C134
C154
C153
AA23
VGA@

VGA@
VGA@
AB23
2.2U_0603_6.3V6K
2
2
2
2

2

+1.8VS

4700P_0402_25V7K

B

+3VS

F6

470P_0402_50V7K
L6
MBK1608121YZF_0603
VGA@
4700P_0402_25V7K
1
2

A

C72
VGA@
2.2U_0603_6.3V6K

1

2

C131
VGA@

1

2

C133
VGA@

+VGA_CORE

2005/10/20

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6

VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36

VDD_37

Part 5 of 6

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5

AD23
AF23
AF24
AF25
AG24
AG25

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10

AC16
AC17
AC21
AC22
AE18
AE21
AE22
AF12
AF18
AF21
AF22

PEX_PLLAVDD
PEX_PLLDVDD

AF15
AE15

MIOA_VDDQ_0
MIOA_VDDQ_1
MIOA_VDDQ_2
MIOA_VDDQ_3
MIOA_VDDQ_4
MIOB_VDDQ_0
MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3
MIOB_VDDQ_4
MIOACAL_PD_VDDQ
MIOBCAL_PD_VDDQ

M7
M8
R8
T8
U9
AA8
AB7
AB8
AC6
AC7
L1
Y1

IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD
IFPD_IOVDD

AF9
AF8
AD6
AE7

IFPAB_PLLVDD
IFPCD_PLLVDD

VID_PLLVDD
PLLVDD
FBA_PLLAVDD

FBC_PLLAVDD
FBA_PLLVDD
FBC_PLLVDD
FBCAL_PD_VDDQ
FBVTT_0
FBVTT_1
FBVTT_2
FBVTT_3
FBVTT_4
FBVTT_5
FBVTT_6
FBVTT_7
FBVTT_8
FBVTT_9
FBVTT_10
FBVTT_11
FBVTT_12
FBVTT_13
FBVTT_14
FBVTT_15
FBVTT_16
FBVTT_17
CLAMP

C249
VGA@

1

2

C243
VGA@

1

2

0.022U_0402_16V7K

C255
VGA@

1

2

AD10
V8
AD7

FBVDD_0
FBVDD_1
FBVDD_2
FBVDD_3
FBVDD_4
FBVDD_5
FBVDD_6
FBVDD_7
FBVDD_8

FBVDD_9
FBVDD_10
FBVDD_11
FBVDD_12
FBVDD_13
FBVDD_14
FBVDD_15
FBVDD_16
FBVDD_17
FBVDD_18
FBVDD_19

A3
A6
A9
A12
A15
A18
A21
A24
A27
A30
C32
F32
J32
M32
R32
V32
AA32
AD32

AG32
AK32

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23

G11
G12

G15
G18
G21
G22
H11
H12
H15
H18
H21
L25
L26
M25
M26
R25
R26
V25
V26
AA25
AA26
AB25
AB26
H22

1

C238
VGA@

2

1

C266
VGA@

2

2

0.022U_0402_16V7K
D

0.022U_0402_16V7K

0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
10U_0805_10V4Z
1
1
1
1
1
1
1
C228
C248
C254
C260
C262

C56
C57
C52
VGA@

VGA@

2

0.01U_0402_16V7K

VGA@

2

0.01U_0402_16V7K

VGA@

2

VGA@

2

0.01U_0402_16V7K

VGA@

2

2

VGA@

1

C136

4700P_0402_25V7K
VGA@
VGA@
2
2
0.1U_0402_16V4Z

1

1

C81
VGA@

2

2

VGA@

C74

VGA@
2 2.2U_0603_6.3V6K

C192

VGA@
2
2 2.2U_0603_6.3V6K
L14
0.1U_0402_16V4Z
VGA@
1
2
MBK1608121YZF_0603
1
1
C179
C83
VGA@
VGA@
2
2 2.2U_0603_6.3V6K
0.1U_0402_16V4Z

470P_0402_50V7K

135mA DACA_VDD
200mA DACB_VDD
200mA DACC_VDD

1

C197
VGA@

1
2
MBK1608121YZF_0603
1

C142

+2.5VS
+3VSDVI
L12
2
VGA@
10K_0402_5%
4700P_0402_25V7K
1
2
1
1
1 MBK1608121YZF_0603
C152
C146
C692
VGA@

2
470P_0402_50V7K

2

+1.2VS

L15
VGA@
1
2
MBK1608121YZF_0603

1
L3
VGA@

2

10U_0805_10V4Z

+1.8VS

0.1U_0402_16V4Z
1
C135

1

VGA@

2

10U_0805_10V4Z

+PEX_PLLAVDD 100mA
+PEX_PLLDVDD 20mA
+3VS

130mA IFPA_IOVDD
130mA
150mA
150mA IFPD_IOVDD
1
VGA@ R103
35mA IFPAB_CD_PLLVDD
AC9
AA10 35mA

DACA_VDD
DACB_VDD
DACC_VDD

1

C229
VGA@

VGA@

C

+5VS

VGA@
2 2.2U_0603_6.3V6K

2

C203
D

0.1U_0402_16V4Z

R536
10K_0402_5%
VGA@

1

10U_0805_10V4Z

R110
10K_0402_5%
VGA@

+3VSDVI

C649
VGA@

2.2U_0603_6.3V6K

1

2

C658

@ 0.1U_0402_16V4Z
2

1

57 VDD_PWRGOOD

1

C646

2
G

0.1U_0402_16V4Z

0.022U_0402_16V7K

1

2

1

0.022U_0402_16V7K

2

C162
VGA@

2

POWER

C82
VGA@
2.2U_0603_6.3V6K

1420mA

1

1

3
S

8mA
1

1

D

L13
+1.2VS MBK1608121YZF_0603
VGA@
1
2

3

+3VS

Q30
AO3402_SOT23
VGA@
L44
1
2
@
MBK1608121YZF_0603

VGA@

2
4700P_0402_25V7K

For NV43 DVI leakage issue
B

+1.8VS
4700P_0402_25V7K
4700P_0402_25V7K
4700P_0402_25V7K
0.022U_0402_16V7K 4.7U_0805_10V4Z
1
1
1
1
1
1
1
1
1
1
C271
C212
C220
C237
C261
C267
C270
C272
C334
C332
VGA@

2

VGA@

2

VGA@

4700P_0402_25V7K

C213

1

2

VGA@

2

VGA@

2

4700P_0402_25V7K

VGA@

2

VGA@

0.022U_0402_16V7K

2

VGA@

2

VGA@

2

0.022U_0402_16V7K

VGA@

2

4.7U_0805_10V4Z

0.022U_0402_16V7K 0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
1
1

C221
C247
C199
C227
C198
C186
C268
C269

VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
2
2
2
2
2
2
2
2
2
0.022U_0402_16V7K 0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

NV43M_BGA820
G73@

+1.8VS

DACB_VDD
1

2

C253
VGA@
330U_D2E_2.5VM

1

2

2005/09/21

1

1

1

2

+ C362
VGA@
330U_D2E_2.5VM
2

+ C529
VGA@
330U_D2E_2.5VM
2

C96
+ VGA@
330U_D2E_2.5VM

+

A

470P_0402_50V7K
Average to place around +VGA_CORE
plane.

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

G72/G73 Power
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Friday, November 11, 2005

Sheet
1

17

of

59


4

3

2

1

G73M
+3VS
U42F

15 CRYSTAL_0

R535 1

2 2K_0402_5%

VGA@

15 SUB_VENDOR

SUB_VENDOR

R561 1

15 MOBILE_MODE

MOBILE_MODE

R73

MIOAD1
MIOAD0

PEX_CFG[2:0]

MIOAD
[9,8,6]

RAM_CFG[3:0]

MIOAD[5:2]

2 2K_0402_5%
VGA@

G73M : SA00000QZ00

PCI_DEVID[3:0]

G72MV : SA00000QY20

01

0

Recommended for G7x

2 2K_0402_5%
@
For all G7x series.

G72M : SA00000QY00

10

D

0
010

16Mx16x4 1.8V (128bit G73M)

0001

Samsung

16Mx16x4 1.8V (128bit G73M)

0011

Hynix

16Mx16x4 1.8V (64bit G73M)

1001

Samsung

16Mx16x4 1.8V (64bit G73M)

1011

Hynix

16Mx16x4 1.8V (64bit G72MV)

0001

Samsung

16Mx16x4 1.8V (64bit G72MV)

0011

Hynix

VIPD[5:3]

MIOA_HSYNC

G73M-xxxx8
G72M-0x01D8

1000

G72MV-0x01D7
TBD/TBD

0111
C

MOBILE_MODE

MIOBD7

For NV44M/G7x

0

RAM_CFG[1:0]
(Manufacture)
(01=Sam, 10=Inf, 11=Hyn)
RAM_CFG[2] (0=16M or 1=32M)
RAM_CFG[3] (Bandwidth 0=Full, 1=Half)

2005/10/15

+3VS

15
15
15
15
15
15
15
15
15
15
15
15

RAM_CFG0
RAM_CFG1
RAM_CFG2
RAM_CFG3
PCI_DEVID0
PCI_DEVID1
PCI_DEVID2
PCI_DEVID3
PEX_CFG0
PEX_CFG1
PEX_CFG2
PEX_PLL_TERM

1
R788
@

2

R76
@

2

R786
VGA@

2

2

R54
G73@

1

1

1

1

R542
G72@

2

R558
G72@

2

R557
G72@

2

R48
X76@

1

1

1
R51
X76@
2

2

R539
X76@

2

R55

X76@

1

1

10K_0402_5%
10K_0402_5%
2K_0402_5%
2K_0402_5%
2K_0402_5%
2K_0402_5%
10K_0402_5%
10K_0402_5%
2K_0402_5%
2K_0402_5%
2K_0402_5%

B

RAM_CFG0
RAM_CFG1
RAM_CFG2
RAM_CFG3
PCI_DEVID0
PCI_DEVID1
PCI_DEVID2
PCI_DEVID3
PEX_CFG0
PEX_CFG1

PEX_CFG2
PEX_PLL_TERM

R553, R55

HALF

R48

16M

R52

Hynix

R539, R55

Infineon

R553, R56

R553
X76@

R52
X76@

R49
X76@

R72
@

R70
@

R63
@

R560
@

R787
VGA@

1

1

1

1

1

1
R71
@

R77

VGA@

R559
VGA@
2K_0402_5%

2

Samsung

2

R51

2

Vendor

32M

2

RAM Type

R49

2

R56
X76@

Bandwidth
FULL

2

NVidia suggestion

1

R148 1 VGA@ 2 30.1_0402_1%
R150 1
2 0_0402_5%
@
1

NV43M_BGA820
G73@

SUB_VENDOR

2

H26
J26

VBIOS on card (pull high)
VBIOS with system BIOS (pull down)

1

FBCAL_PU_GND
FBCAL_TERM_GND

Parallel=00, SERIAL M25P10=01,
Serial SST45VF=10

2

U10
G24
G9

MIOBD
[11:10]

1

L3
Y3

PLLGND

MIOBD[6,2] 27MHz=10, 14.318MHz=01, 13.5MHz=00

PEX_PLL_TERM

Value

Value

ROM_TYPE[1:0]

+3VS

AE16

FBA_PLLGND
FBC_PLLGND

DESCRIPTION

CRYSTAL[1:0]

1

PEX_PLLGND

2 2K_0402_5%
VGA@

PIN

2

MIOACAL_PU_GND
MIOBCAL_PU_GND

1

1

AD9
AB10

R50

2

IFPAB_PLLGND
IFPCD_PLLGND

15 CRYSTAL_1

1

W18
Y4
Y15
Y18
Y29
AA2
AA12
AA21
AA31
AB6
AB27
AC4
AC10
AC23

AC29
AD2
AD16
AD17
AD31
AE6
AE17
AE27
AF4
AF7
AF11
AF26
AF29
AG2
AG8
AG10
AG11
AG13
AG14
AG15
AG19
AG22
AG31
AH24
AJ4
AJ7
AJ10
AJ13
AJ16
AJ17

AJ20
AJ23
AJ26
AJ29
AK2
AL3
AL6
AL9
AL10
AK28
AK31
AL11
AL14
AL19
AL22
AL25
AM13
AM16
AM17
AM20
AM23
AM26
AM29
D16
W27
W15

2

B

GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113

GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143

GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154

1

C

Part 6 of 6

2

D

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7

GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37

GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67

GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83

GND

B3
B6
B9
B12
B15
B18
B21
B24
B27
B30
C2

C31
D4
D7
D10
D13
D17
D20
D23
D26
D29
F2
F8
F11
F14
F19
F22
F25
F31
G4
G7
G26
G29
H27
H6
J2
J16
J17
J31
K10
K23

K29
K4
L6
L27
M2
M12
M21
M31
N4
N15
N18
N29
P6
P15
P18
P27
R2
R13
R14
R15
R18
R19
R20
R31
T4
T16
T17
T24
T29
U8

U16
U17
U24
U29
V2
V13
V14
V15
V18
V19
V20
V31
W6

G72MV

STRAPS

2

5

10K_0402_5%
10K_0402_5% 2K_0402_5%
2K_0402_5%
2K_0402_5%
2K_0402_5%
2K_0402_5%
10K_0402_5%
10K_0402_5% 2K_0402_5%

2K_0402_5%

Package
A

(10*12.5)

Infineon GDDR2(400): SA00000S800 (HYB18T256161AFL-25)

Infineon GDDR2(350): SA00000T700 (HYB18T256161AF-28)

(11*13)

Samsung GDDR2 (400): SA00000FG10 (K4N56163QF-ZC25)

Samsung GDDR2 (350): SA00000TB00 (K4N56163QF-ZC2A)

(8*13)

Hynix GDDR2 (400): SA00000FF10 (HY5PS561621AFP-25)

Hynix GDDR2 (350): SA00000TJ00 (HY5PS561621AFP-28)

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

A

2

Title

G72/G73 GND & STRAP
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
1

18

of

59


5

4

3

2

BA0
BA1

FBAA12
FBAA11
FBAA10

FBAA9
FBAA8
FBAA7
FBAA6
FBAA5
FBAA4
FBAA3
FBAA2
FBAA1
FBAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8

A7
A6
A5
A4
A3
A2
A1
A0

FBACLK0#
FBACLK0

K8
J8

CK
CK

FBA_CKE

K2

FBACS0#

L8

CS

FBAWE#

K3

WE

FBARAS#

K7

RAS

FBACAS#

L7

CAS

FBADQM#0
FBADQM#1

F3
B3

LDM
UDM

C

FBAODT0

K9

ODT

FBADQS0
FBADQS#0

F7
E8

LDQS
LDQS

R593
1K_0402_1%
64@

FBADQS1
FBADQS#1

B7
A8

UDQS
UDQS

J2

VREF

A2

E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

2

+VRAM_VREFA

(SSTL-1.8) VREF = .5*VDDQ

1
2

R597
1K_0402_1%
64@

1

2

C790
0.047U_0402_16V4Z
64@

Close to U7

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7

VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

FBAD14
FBAD11
FBAD13
FBAD8
FBAD9
FBAD12
FBAD10
FBAD15
FBAD6
FBAD1
FBAD7
FBAD0
FBAD3
FBAD5
FBAD2
FBAD4

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

FBA_BA0
FBA_BA1

L2
L3

BA0
BA1

FBAA12
FBAA11
FBAA10
FBAA9
FBAA8
FBAA7
FBAA6
FBAA5
FBAA4
FBAA3
FBAA2
FBAA1
FBAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

FBACLK0#
FBACLK0

K8
J8

CK
CK

FBA_CKE

K2

CKE

+1.8VS

1

2

1

+1.8VS

CKE

U11
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

C812
0.1U_0402_16V4Z
64@

1

2

C814
1U_0402_6.3V4Z
64@

+VRAM_VREFA

FBACS0#

L8

CS

FBAWE#

K3

WE

FBARAS#

K7

RAS

FBACAS#

L7

CAS

FBADQM#2
FBADQM#3

F3
B3

LDM
UDM

FBAODT0

K9

ODT

FBADQS2
FBADQS#2

F7
E8

LDQS

LDQS

FBADQS3
FBADQS#3

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

(SSTL-1.8) VREF = .5*VDDQ

1

2

C340
0.047U_0402_16V4Z
64@

Close to U8

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1

D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7

C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5

VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

FBAD25

FBAD31
FBAD27
FBAD30
FBAD26
FBAD28
FBAD29
FBAD24
FBAD18
FBAD23
FBAD17
FBAD21
FBAD19
FBAD16
FBAD22
FBAD20

D

FBAD[0..63]

16,20 FBAD[0..63]

FBAA[0..12]

16,20 FBAA[0..12]

FBADQS[0..7]

16,20 FBADQS[0..7]

FBADQS#[0..7]

16,20 FBADQS#[0..7]

FBADQM#[0..7]

16,20 FBADQM#[0..7]

FBA_BA0

16,20 FBA_BA0

FBA_BA1

16,20 FBA_BA1

+1.8VS

FBAODT0

16,20 FBAODT0

FBA_CKE

16,20 FBA_CKE

FBARAS#

16,20 FBARAS#

FBACAS#

16,20 FBACAS#

FBAWE#

16,20 FBAWE#
1

2

C364
0.1U_0402_16V4Z
64@

1

2

C368
1U_0402_6.3V4Z
64@

Close to U8
FBACLK0

16 FBACLK0

R596
120_0402_5%

64@

R596 is 120 Ohm (SD028120080) for G72MV
R596 is 475 Ohm (SD034475080) for G73M

FBACLK0#

16 FBACLK0#
X76@ HY5PS561621F-25

C

FBACS0#

16,20 FBACS0#

1

D

L2
L3

2

U46
FBA_BA0
FBA_BA1

1

X76@ HY5PS561621F-25

DDR2 BGA MEMORY

DDR2 BGA MEMORY

B

B

+1.8VS

1

+1.8VS
0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
C785
C787
C799
C802
C810

C815

C811
64@

2
2
1000P_0402_50V7K

64@

64@

2
2
0.01U_0402_16V7K

64@

64@

2
2
1U_0402_6.3V4Z

64@

64@

1

2
2
0.1U_0402_16V4Z

C816
0.01U_0402_16V7K
64@

1

0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
C331
C335
C349
C353
C366
C375

C367
64@

2
2
1000P_0402_50V7K

64@

64@

2
2
0.01U_0402_16V7K

64@

64@

2
2
1U_0402_6.3V4Z

64@

64@

1

2
2
0.1U_0402_16V4Z

C374
0.01U_0402_16V7K
64@

A

A

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

VRAM DDRA
Size Document Number
Custom

Rev
0.3

HBL50 LA-2921P

Date:

Sheet

Friday, November 11, 2005
1

19

of

59


5

4

3

2

1

D

D

L2
L3

BA0
BA1

FBAA12
FBAA11
FBAA10
FBAA9
FBAA8
FBAA7
FBAA6
FBBA5
FBBA4
FBBA3
FBBA2

FBAA1
FBAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

FBACLK1#
FBACLK1

K8
J8

CK
CK

FBA_CKE

K2

CKE

FBACS0#

L8

CS

FBAWE#

K3

WE

FBARAS#

K7

C

L7

CAS

FBADQM#7
FBADQM#5

F3
B3

LDM
UDM

FBAODT0

K9

ODT

FBADQS7
FBADQS#7

F7
E8

LDQS

LDQS

R592
1K_0402_1%
128@

FBADQS5
FBADQS#5

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3

NC#R7
NC#R8

(SSTL-1.8) VREF = .5*VDDQ

1
2

R594
1K_0402_1%
128@

1

2

C784
0.047U_0402_16V4Z
128@

Close to U9

A9
C1
C3
C7
C9
E9
G1
G3

G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

FBAD44
FBAD46
FBAD41
FBAD40
FBAD45
FBAD43
FBAD47
FBAD42
FBAD63

FBAD58
FBAD61
FBAD56
FBAD60
FBAD57
FBAD59
FBAD62

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

FBA_BA0
FBA_BA1

L2
L3

BA0
BA1

FBAA12
FBAA11
FBAA10
FBAA9
FBAA8
FBAA7
FBAA6
FBBA5
FBBA4

FBBA3
FBBA2
FBAA1
FBAA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2

A1
A0

FBACLK1#
FBACLK1

K8
J8

CK
CK

FBA_CKE

K2

CKE

+1.8VS

1

2

2

+VRAM_VREFB

B9
B1

D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

RAS

FBACAS#

1

+1.8VS

U12
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

C757
0.1U_0402_16V4Z
128@

1

2

C758
1U_0402_6.3V4Z
128@

2

L8

CS

FBAWE#

K3

WE

FBARAS#

K7
L7

CAS

FBADQM#6
FBADQM#4

F3
B3

LDM

UDM

K9

ODT

FBADQS6
FBADQS#6

F7
E8

LDQS
LDQS

FBADQS4
FBADQS#4

B7
A8

UDQS
UDQS

J2

VREF

(SSTL-1.8) VREF = .5*VDDQ

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

C329
0.047U_0402_16V4Z
128@

Close to U10

X76@ HY5PS561621F-25

B9
B1
D9
D1
D3
D7
C2
C8

F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

RAS

FBACAS#

FBAODT0

+VRAM_VREFB

1

FBACS0#

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

FBAD32
FBAD36
FBAD33
FBAD38
FBAD39
FBAD35
FBAD37
FBAD34

FBAD50
FBAD55
FBAD49
FBAD54
FBAD52
FBAD53
FBAD51
FBAD48

16,19 FBAD[0..63]
16,19 FBAA[0..12]
16 FBBA[2..5]
16,19 FBADQS[0..7]
16,19 FBADQS#[0..7]
16,19 FBADQM#[0..7]
16,19 FBA_BA0
16,19 FBA_BA1
+1.8VS

16,19 FBAODT0

FBA_BA0
FBA_BA1
FBAODT0

C

FBACS0#

16,19 FBACS0#

2

FBADQM#[0..7]

FBAWE#

16,19 FBAWE#

2

FBADQS[0..7]
FBADQS#[0..7]

FBACAS#

16,19 FBACAS#

1

FBBA[2..5]

FBARAS#

16,19 FBARAS#

C321
0.1U_0402_16V4Z
128@

FBAA[0..12]

FBA_CKE

16,19 FBA_CKE

1

FBAD[0..63]

C325
1U_0402_6.3V4Z
128@

FBACLK1

16 FBACLK1

1

U45
FBA_BA0
FBA_BA1

R200
120_0402_5%
128@

X76@ HY5PS561621F-25

B

2

B

FBACLK1#

16 FBACLK1#

DDR2 BGA MEMORY

Close to U10

DDR2 BGA MEMORY

R200 is 120 Ohm (SD028120080) for G72MV
R200 is 481 Ohm (SD00000CA80) for G73M
+1.8VS

1

+1.8VS
0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1

1
1
C813
C809
C807
C806
C789
C791

C805

128@

2
2
1000P_0402_50V7K

128@

128@

2
2
0.01U_0402_16V7K

128@

128@

2

2
1U_0402_6.3V4Z

128@

128@

1

2
2
0.1U_0402_16V4Z

1

C808
0.01U_0402_16V7K
128@

0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
C337
C342

C370
C372
C371
C369

C373

128@

2
2
1000P_0402_50V7K

128@

128@

2
2
0.01U_0402_16V7K

128@

128@

2
2
1U_0402_6.3V4Z

128@

1

128@

2
2
0.1U_0402_16V4Z

C365
0.01U_0402_16V7K
128@

A

A

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

VRAM DDRB
Size Document Number
Custom

Rev
0.3

HBL50 LA-2921P

Date:

Sheet

Friday, November 11, 2005
1

20

of

59


5

4

3

2

BA0
BA1

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBCA5
FBCA4
FBCA3
FBCA2

FBCA1
FBCA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

FBCCLK0#
FBCCLK0

K8
J8

CK
CK

FBC_CKE

K2

C

CKE

FBCCS0#

L8

CS

FBCWE#

K3

WE

FBCRAS#

K7

RAS

FBCCAS#

L7

CAS

FBCDQM#1
FBCDQM#3

F3
B3

LDM
UDM

FBCODT0

K9

ODT

FBCDQS1
FBCDQS#1

F7
E8

LDQS
LDQS

FBCDQS3
FBCDQS#3

B7
A8

UDQS
UDQS

J2

VREF

(SSTL-1.8) VREF = .5*VDDQ

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2

NC#L1
NC#R3
NC#R7
NC#R8

R86
1K_0402_1%
256@

1

2

+VRAM_VREFC

1

2

C101
0.047U_0402_16V4Z
256@

2

R85
1K_0402_1%
256@

Close to U11

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9

C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

FBCD26
FBCD31

FBCD24
FBCD28
FBCD29
FBCD27
FBCD30
FBCD25
FBCD15
FBCD12
FBCD8
FBCD10
FBCD9
FBCD11
FBCD13
FBCD14

+1.8VS

1

2

1

+1.8VS

U4
DQ15
DQ14
DQ13
DQ12

DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5

C691

0.1U_0402_16V4Z
256@

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

1

2

2

BA0
BA1

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6

FBCA5
FBCA4
FBCA3
FBCA2
FBCA1
FBCA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4

A3
A2
A1
A0

FBCCLK0#
FBCCLK0

K8
J8

CK
CK

FBC_CKE

K2

CKE

FBCCS0#

L8

CS

FBCWE#

K3

WE

FBCRAS#

K7

RAS

FBCCAS#

L7

CAS

FBCDQM#0
FBCDQM#2

F3
B3

LDM
UDM

K9

ODT

FBCDQS0
FBCDQS#0

F7
E8

LDQS
LDQS

FBCDQS2
FBCDQS#2

B7
A8

UDQS
UDQS

J2

VREF

(SSTL-1.8) VREF = .5*VDDQ

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2

NC#L1
NC#R3
NC#R7
NC#R8

+VRAM_VREFC

A3
E3
J3
N1
P9

L2
L3

FBCODT0

C694
1U_0402_6.3V4Z
256@

1

FBC_BA0
FBC_BA1

C670
0.047U_0402_16V4Z
256@

Close to U12

FBCD19
FBCD21
FBCD16
FBCD22
FBCD20
FBCD17
FBCD23
FBCD18
FBCD0
FBCD5
FBCD2
FBCD3
FBCD7
FBCD6
FBCD4
FBCD1

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6

DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6

VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

16,22 FBCRAS#

VDDL
VSSDL

J1
J7

16,22 FBCCS0#

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

D

16,22 FBCD[0..63]
16,22 FBCA[0..12]
16,22 FBCDQS[0..7]
16,22 FBCDQS#[0..7]
16,22 FBCDQM#[0..7]
16,22 FBC_BA0
16,22 FBC_BA1

+1.8VS

16,22 FBCODT0
16,22 FBC_CKE

16,22 FBCCAS#
16,22 FBCWE#
1

2

1

C102
0.1U_0402_16V4Z
256@

2

FBCA[0..12]
FBCDQS[0..7]
FBCDQS#[0..7]
FBCDQM#[0..7]

FBC_BA0
FBC_BA1
FBCODT0
FBC_CKE
FBCRAS#
FBCCAS#
FBCWE#
C

FBCCS0#

C103
1U_0402_6.3V4Z
256@

Close to U12
FBCCLK0

16 FBCCLK0

R566
120_0402_5%
256@

FBCCLK0#

16 FBCCLK0#
X76@ HY5PS561621F-25

FBCD[0..63]

1

L2
L3

2

U41
FBC_BA0
FBC_BA1
D

1

X76@ HY5PS561621F-25

R566 is 120 Ohm (SD028120080) for G72MV
R566 is 481 Ohm (SD00000CA80) for G73M

DDR2 BGA MEMORY

B

DDR2 BGA MEMORY

+1.8VS

B

+1.8VS

0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
1
C674
C673

C685
C680
C742
C688
C676

1

256@
256@
256@
256@
256@
256@
256@
2
2
2
2
2
2
2
2
1000P_0402_50V7K
0.01U_0402_16V7K
1U_0402_6.3V4Z
0.1U_0402_16V4Z

C675
0.01U_0402_16V7K

256@

1

0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
C171
C112
C280
C122
C128
C99

1
C100
0.01U_0402_16V7K
256@
256@
256@
256@
256@
256@
256@

256@
2
2
2
2
2
2
2
2
1000P_0402_50V7K
0.01U_0402_16V7K
1U_0402_6.3V4Z
0.1U_0402_16V4Z
C160

A

A

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

VRAM DDRC
Size Document Number
Custom

Rev
0.3

HBL50 LA-2921P

Date:

Sheet

Friday, November 11, 2005
1

21

of

59


5

4

3

2

U43
FBC_BA0
FBC_BA1

L2
L3

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8

FBCA7
FBCA6
FBDA5
FBDA4
FBDA3
FBDA2
FBCA1
FBCA0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

FBCCLK1#
FBCCLK1

K8
J8

CK

CK

FBC_CKE

K2

CKE

D

1

U5
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1

C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

BA0
BA1
A12

A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

FBCD33
FBCD39
FBCD35
FBCD37
FBCD38
FBCD32
FBCD36
FBCD34
FBCD52
FBCD48
FBCD54
FBCD50
FBCD49
FBCD53
FBCD51
FBCD55

FBC_BA0
FBC_BA1

L2
L3

BA0
BA1

FBCA12
FBCA11
FBCA10
FBCA9
FBCA8
FBCA7
FBCA6
FBDA5
FBDA4
FBDA3
FBDA2
FBCA1
FBCA0

R2
P7
M2
P3
P8
P2
N7

N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

FBCCLK1#
FBCCLK1

K8
J8

CK
CK

FBC_CKE

K2

CKE

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2

C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7

G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

FBCD57
FBCD63
FBCD59
FBCD62
FBCD60
FBCD58

FBCD61
FBCD56
FBCD41
FBCD44
FBCD40
FBCD47
FBCD43
FBCD42
FBCD46
FBCD45

FBCD[0..63]

16,21 FBCD[0..63]

D

FBCA[0..12]

16,21 FBCA[0..12]

FBDA[2..5]

16 FBDA[2..5]

FBCDQS[0..7]

16,21 FBCDQS[0..7]

FBCDQS#[0..7]

16,21 FBCDQS#[0..7]

FBCDQM#[0..7]

16,21 FBCDQM#[0..7]

CS

FBCWE#

K3

WE

FBCRAS#

K7

RAS

FBCCAS#

L7

CAS

FBCDQM#6
FBCDQM#4

F3
B3

LDM
UDM

FBCODT0

K9

ODT

FBCDQS6
FBCDQS#6

F7
E8

LDQS
LDQS

FBCDQS4
FBCDQS#4

B7
A8

UDQS
UDQS

J2

VREF

(SSTL-1.8) VREF = .5*VDDQ

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

2

1

+1.8VS

R585
1K_0402_1%
256@

1

2

+VRAM_VREFD

1

2

2

R584
1K_0402_1%
256@

C749
0.047U_0402_16V4Z
256@

Close to U13

1

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6

VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5

C745
0.1U_0402_16V4Z
256@

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

1

2

2

CS

FBCWE#

K3

WE

FBCRAS#

K7

RAS

FBCCAS#

L7

CAS

FBCDQM#5
FBCDQM#7

F3
B3

LDM
UDM

K9

ODT

FBCDQS5
FBCDQS#5

F7
E8

LDQS
LDQS

FBCDQS7
FBCDQS#7

B7
A8

UDQS
UDQS

J2

VREF

(SSTL-1.8) VREF = .5*VDDQ

A2
E2

L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

+VRAM_VREFD

A3
E3
J3
N1
P9

L8

FBCODT0

C684
1U_0402_6.3V4Z
256@

1

FBCCS0#

C309
0.047U_0402_16V4Z
256@

Close to U14

X76@ HY5PS561621F-25

FBCODT0

16,21 FBCODT0

+1.8VS

FBC_CKE

16,21 FBC_CKE

FBCRAS#

16,21 FBCRAS#

FBCCAS#

16,21 FBCCAS#

FBCWE#

16,21 FBCWE#

FBCCS0#

16,21 FBCCS0#
1

2

1

C289
0.1U_0402_16V4Z
256@

2

C

C120
1U_0402_6.3V4Z
256@

FBCCLK1

16 FBCCLK1

1

L8

FBC_BA1

16,21 FBC_BA1

R170
120_0402_5%
256@
2

C

FBCCS0#

+1.8VS

FBC_BA0

16,21 FBC_BA0

X76@ HY5PS561621F-25

FBCCLK1#

16 FBCCLK1#

Close to U14
B

DDR2 BGA MEMORY

+1.8VS

2
2
1000P_0402_50V7K

B

+1.8VS

0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
1
C750
C751
C699
C738
C747
C748
C721
256@

R170 is 120 Ohm (SD028120080) for G72MV
R170 is 481 Ohm (SD00000CA80) for G73M

DDR2 BGA MEMORY

256@

256@

2
2
0.01U_0402_16V7K

256@

256@

2
2
1U_0402_6.3V4Z

256@

256@

1

2
2
0.1U_0402_16V4Z

C737
0.01U_0402_16V7K
256@

1

0.01U_0402_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
1
1
C307
C306
C305
C304
C233
C246

1

C277

256@

2

2
1000P_0402_50V7K

256@

256@

2
2
0.01U_0402_16V7K

256@

256@

2
2
1U_0402_6.3V4Z

256@

256@

2
2
0.1U_0402_16V4Z

C273
0.01U_0402_16V7K
256@

A

A

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

VRAM DDRD
Size Document Number
Custom

Rev
0.3

HBL50 LA-2921P

Date:

Sheet

Friday, November 11, 2005
1

22

of

59


5

4

3

2

1

LCD POWER CIRCUIT

+3VS

+3VALW
+LCDVDD
1

1

W=60mils
1

R493
100K_0402_5%

R485
300_0402_5%

3
2
R496

1

1K_0402_5%
1
C600

AOS 3413

SI2301BDS_SOT23
+LCDVDD

W=60mils

0.047U_0402_16V7K
2

Q1
2N7002_SOT23
3

Q28

2

1

D

2
G
1

R494 1

15 ENVDD

GM@
2 0_0402_5%
VGA@
0_0402_5%
2

1

3

R495 1

G

2
G
S

8 GMCH_ENVDD

D

2

D
Q25

2N7002_SOT23

D

1 2

2

C12
4.7U_0805_10V4Z

S

D

1

S

1

C593

4.7U_0805_10V4Z
2

C597
0.1U_0402_16V4Z

2

R490
10K_0402_5%

2

1

+3VS

R492

BKOFF#

1

2

4.7K_0402_5%
40 BKOFF#

D27
2 RB751V_SOD323

DISPOFF#

TXOUT0TXOUT0+

R25
R26

1
1

2 VGA@ 0_0402_5%
2 VGA@ 0_0402_5%

LVDSA0LVDSA0+

LVDSA0- 15
LVDSA0+ 15

TXOUT1TXOUT1+

R27
R28

1
1

2 VGA@ 0_0402_5%
2 VGA@ 0_0402_5%

LVDSA1LVDSA1+

LVDSA1- 15
LVDSA1+ 15

TXOUT2+
TXOUT2-

R29
R30

1
1

2 VGA@ 0_0402_5%
2 VGA@ 0_0402_5%

LVDSA2+
LVDSA2-

LVDSA2+ 15
LVDSA2- 15

TXCLKTXCLK+

R31
R32

1
1

2 VGA@ 0_0402_5%
2 VGA@ 0_0402_5%

LVDSACLVDSAC+

LVDSAC- 15

LVDSAC+ 15

TZOUT0TZOUT0+

R33
R34

1
1

2 VGA@ 0_0402_5%
2 VGA@ 0_0402_5%

LVDSB0LVDSB0+

LVDSB0- 15
LVDSB0+ 15

TZOUT1+
TZOUT1-

R35
R36

1
1

2 VGA@ 0_0402_5%
2 VGA@ 0_0402_5%

LVDSB1+
LVDSB1-

LVDSB1+ 15
LVDSB1- 15

TZOUT2+
TZOUT2-

R37
R38

1
1

2 VGA@ 0_0402_5%
2 VGA@ 0_0402_5%

LVDSB2+
LVDSB2-

LVDSB2+ 15
LVDSB2- 15

TZCLKTZCLK+

R39
R40

1

1

2 VGA@ 0_0402_5%
2 VGA@ 0_0402_5%

LVDSBCLVDSBC+

LVDSBC- 15
LVDSBC+ 15

I2CC_SCL
I2CC_SDA

R41
R42

1
1

2 GM@ 0_0402_5%
2 GM@ 0_0402_5%

GMCH_LCD_CLK
GMCH_LCD_DATA

TXOUT0TXOUT0+

R509 1
R508 1

2 GM@ 0_0402_5%
2 GM@ 0_0402_5%

GMCH_TXOUT0GMCH_TXOUT0+

TXOUT1TXOUT1+

R507 1
R506 1

2 GM@ 0_0402_5%
2 GM@ 0_0402_5%

GMCH_TXOUT1GMCH_TXOUT1+

TXOUT2+
TXOUT2-

R505 1
R504 1

2 GM@ 0_0402_5%
2 GM@ 0_0402_5%

GMCH_TXOUT2+
GMCH_TXOUT2-

TXCLKTXCLK+

R503 1

R502 1

2 GM@ 0_0402_5%
2 GM@ 0_0402_5%

GMCH_TXCLKGMCH_TXCLK+

TZOUT0TZOUT0+

R525 1
R524 1

2 GM@ 0_0402_5%
2 GM@ 0_0402_5%

GMCH_TZOUT0GMCH_TZOUT0+

TZOUT1+
TZOUT1-

R523 1
R522 1

2 GM@ 0_0402_5%
2 GM@ 0_0402_5%

GMCH_TZOUT1+
GMCH_TZOUT1-

TZOUT2+

TZOUT2-

R521 1
R520 1

2 GM@ 0_0402_5%
2 GM@ 0_0402_5%

GMCH_TZOUT2+
GMCH_TZOUT2-

TZCLKTZCLK+

R519 1
R518 1

2 GM@ 0_0402_5%
2 GM@ 0_0402_5%

GMCH_TZCLKGMCH_TZCLK+

C

LCD/PANEL BD. Conn.
JP1
+INVPWR_B+
+3VS
15 I2CC_SCL
15 I2CC_SDA

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

I2CC_SCL
I2CC_SDA
TZOUT0TZOUT0+
TZOUT1+
TZOUT1TZOUT2+
TZOUT2TZCLKTZCLK+

B

DAC_BRIG
INVT_PWM
DISPOFF#

20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

DAC_BRIG 40
INVT_PWM 40
+LCDVDD

(60 MIL)

TXOUT0TXOUT0+
TXOUT1TXOUT1+
TXOUT2+
TXOUT2TXCLKTXCLK+

ACES_88107-4000G

(SAME AS ACES_87216-4016)
+LCDVDD
+INVPWR_B+
L1
2
1
KC FBM-L11-201209-221LMAT_0805
L2
2
1
KC FBM-L11-201209-221LMAT_0805
C930
680P_0603_50V7K

1

1

2

2

+3VS

B+

C

1

2

1

C11
0.1U_0402_16V4Z

2

C586
10U_0805_10V4Z

1

2

C591
0.1U_0402_16V4Z

GMCH_LCD_CLK 8
GMCH_LCD_DATA 8
GMCH_TXOUT0- 8
GMCH_TXOUT0+ 8
GMCH_TXOUT1- 8

GMCH_TXOUT1+ 8
GMCH_TXOUT2+ 8
GMCH_TXOUT2- 8

B

GMCH_TXCLK- 8
GMCH_TXCLK+ 8
GMCH_TZOUT0- 8
GMCH_TZOUT0+ 8
GMCH_TZOUT1+ 8
GMCH_TZOUT1- 8
GMCH_TZOUT2+ 8
GMCH_TZOUT2- 8
GMCH_TZCLK- 8
GMCH_TZCLK+ 8

C10
68P_0402_50V8K

A

A

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

LCD Connector
Size
B
Date:

Document Number

Rev

0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
1

23

of

59


A

B

C

D

CRT Connector

W=40mils
+5VS

+R_CRT_VCC
D22

1

1

D20
D21
D26
@
@
@
DAN217_SC59 DAN217_SC59 DAN217_SC59
1

E

2

1

1

1

W=40mils

2
1.1A_6VDC_FUSE
1

C575
0.1U_0402_16V4Z
2

3

1 R474
0_0603_5%

2

GM@ 2

3

+2.5VS

2

1 R475
0_0603_5%

3

PM@ 2

2

RB411D_SOT23
+3VS

+CRT_VCC

F1

+CRT_PULLUP

1

VGA:8P_0402_50V8K
UMA:10P_0402_50V8J

Place closed to chipset

JP15

CRT_G

0_0402_5%
0_0402_5%

CRT_B

0_0402_5%

2

150_0402_1%

R483

2

R477

1

R487

150_0402_1%

C592
PM@
8P_0402_50V8K
150_0402_1% 2

1

C581
PM@

2
8P_0402_50V8K

1

1

C571
PM@

8P_0402_50V8K
2

C580
8P_0402_50V8K
2
PM@

1

DDC_MD2

1

C578
8P_0402_50V8K
PM@ 2

2

C576
8P_0402_50V8K
PM@
1

C573

SUYIN_070549FR015S208CR

+CRT_VCC

P
8 GMCH_CRT_HSYNC

2

CRT_HSYNC 2

A

1
10K_0402_5%

1
L40

CRT_HSYNC_L
2
FCM1608C-121T_0603

2
100P_0402_50V8J

CRT_VSYNC_L
2
FCM1608C-121T_0603

Y

CRT_HSYNC_B

4

C577
10P_0402_50V8K

SN74AHCT1G125DCKR_SC70-5

1

1

2

2

DSUB_12
1

U35

G

2
PM@ 0_0402_5%
2
GM@ 39_0402_5%

1

5

2
R489

3

1
R105
1
R106

15 VGA_CRT_HSYNC

1
L38

2
0.1U_0402_16V4Z

OE#

1
C584

6
11
1
7
12

2
8
13
3
9
14
4
10
15
5

C574

C579 2
68P_0402_50V8K

10P_0402_50V8K

2
0.1U_0402_16V4Z

2

5

CRT_VSYNC 2

A

U36

Y

CRT_VSYNC_B

4

G

2
PM@ 0_0402_5%
2
GM@ 39_0402_5%

C572
68P_0402_50V8K

+3VS
+CRT_VCC

SN74AHCT1G125DCKR_SC70-5

1

8 GMCH_CRT_VSYNC

3

1
R115
1

R116

15 VGA_CRT_VSYNC

1

2
P

1
C590

OE#

Place closed to chipset

DSUB_15
1

+CRT_VCC

Place closed to chipset
R781
4.7K_0402_5%
PM@

R479
4.7K_0402_5%

15 VGA_TV_COMPS

8 GMCH_TV_COMPS

TV_CRMA

0_0402_5%
TV_COMPS
0_0402_5%
0_0402_5%

R486

R488

R484
1
C589

150_0402_1%

150_0402_1%

2

2

2

150_0402_1%

2

C596

1

C583

1

2005/09/22

2
2
150P_0402_50V8J

150P_0402_50V8J

C587

1

150P_0402_50V8J
2

C594

GM@ 0_0402_5%
1

GMCH_CRT_DATA 8

D

S

2
1
R129
GM@ 0_0402_5%

GMCH_CRT_CLK 8
3

2 R476
PM@ 0_0402_5%

VGA_DDC_CLK 15

TV_LUMA_L

1

1

C585

2
150P_0402_50V8J

2005/10/18

3
6
7
5
2
4
1
8
9

2

JP14
TV_CRMA_L
TV_COMPS_L

R782
4.7K_0402_5%
PM@
1

8 GMCH_TV_CRMA

0_0402_5%

3

1

C582 1
22P_0402_50V8J
2
1
2
L39 PM@ FCM1608C-121T_0603
C595 1
22P_0402_50V8J
2
1
2
L43 PM@ FCM1608C-121T_0603
C588 1
22P_0402_50V8J
2
1
2
L41 PM@ FCM1608C-121T_0603

TV_LUMA
0_0402_5%

1

15 VGA_TV_CRMA

0_0402_5%

1

8 GMCH_TV_LUMA

2
PM@
2
GM@
2
PM@
2
GM@
2
PM@
2
GM@

1

1
R66
1
R74
1
R75
1
R79
1
R62
1
R65

1

Q26
2N7002_SOT23

+3VS
15 VGA_TV_LUMA

VGA_DDC_DATA 15

2
G

D
3

2

3

2

2

3

DSUB_15

Place closed to chipset

R98
2

3

Q27
2N7002_SOT23

3

2 R480
PM@ 0_0402_5%

2
G

2
4.7K_0402_5%
1

DSUB_12

1

1

R478
2

D24

@
DAN217_SC59

1

D23
@
DAN217_SC59

1

D1
@
DAN217_SC59

S

TV-OUT Conn.

1

1

+3VS

2

R89

1

1

0_0402_5%
0_0402_5%

2 CRT_R_L
L36
FCM2012C-800_0805
1
2 CRT_G_L
L37
FCM2012C-800_0805
1
2 CRT_B_L
L42
FCM2012C-800_0805
1

1

15 VGA_CRT_B
8 GMCH_CRT_B

1
1

CRT_R

2

R87
R88

0_0402_5%

1

R83
R84

15 VGA_CRT_G
8 GMCH_CRT_G

2 PM@
2
GM@
2 PM@
2
GM@
2 PM@
2
GM@

1
1

1

R80

15 VGA_CRT_R
8 GMCH_CRT_R

+3VS
SUYIN_030107FR007SX08FU

150P_0402_50V8J
2

(ECQ60)

150P_0402_50V8J

VGA:82P_0402_50V8J
UMA:6P_0402_50V8J

L39, L41, L43 must change to SM010006T00 for VGA
L39, L41, L43 must change to SM010010710 for UMA

4

4

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

CRT & TV-OUT Connector
Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Sheet

Friday, November 11, 2005
E

24

of

59


5

4

1

+3VS

1

C5
7307@
10U_0805_10V4Z
2

C3

7307@

2

0.1U_0402_16V4Z
1

C9
7307@
0.1U_0402_16V4Z
2

1

1

C4
7307@
10U_0805_10V4Z
2

C8
7307@

2

+3VS
+2.5VS

1

C6
7307@
0.1U_0402_16V4Z
2

D

SDVOB_INT+
SDVOB_INT-

8 SDVOB_R
8 SDVOB_R#

37
38

SDVOB_R+
SDVOB_R-

8 SDVOB_G
8 SDVOB_G#

40
41

SDVOB_G+
SDVOB_G-

8 SDVOB_B

8 SDVOB_B#

43
44

SDVOB_B+
SDVOB_B-

8 SDVOB_CLK
8 SDVOB_CLK#

46
47

SDVOB_CLK+
SDVOB_CLK-

AS

AS
26,36,39 PLT_RST_BUF#

27
26

ATPG
SCEN

1

AS
RESET#
VSWING

R5
10K_0402_5%
7307@

DVI_TXCDVI_TXC+
DVI_TXD0DVI_TXD0+
DVI_TXD1DVI_TXD1+
DVI_TXD2DVI_TXD2+

TLC#
TLC
TDC0#
TDC0
TDC1#
TDC1
TDC2#
TDC2

13
14
16
17
19
20
22
23

HPDET

29

DVI_DET

SC_DDC
SD_DDC

11
10

DVI_SCLK
DVI_SDATA

SC_PROM
SD_PROM

9
8

SPD
SPC

5
4

BOM structure

SDVO_SDAT
SDVO_SCLK

DVI from SDVO

DVI from Discrete VGA

7307@

Stuff

VGA@

No_Stuff

Stuff

@

No_Stuff

No_Stuff

No_Stuff

SDVO_SDAT 8
SDVO_SCLK 8

Keep 30mil spacing to other signals

+2.5VS
C

7307@ CH7307_LQFP48
SDVO_SDAT
R12

2

R1
10K_0402_5%
7307@
2

R6
1.2K_0402_5%
7307@

2

C

1

1

2

R9
10K_0402_5%

@

3
2
25

DGND
DGND
AGND
AGND
AGND
TGND
TGND
AGND_PLL

32
33

7
30
31
39
45
18
24
6

R10
10K_0402_5%
7307@

1

2

1

+2.5VS

DVDD
DVDD
AVDD_PLL
TVDD
TVDD
AVDD
AVDD
AVDD

U1

8 SDVO_INT
8 SDVO_INT#

NC
NC

1

12
28

1
15
21
36
42
48

0.1U_0402_16V4Z

D

2

34
35

+2.5VS

3

SDVO_SCLK
R11

DVI-D Connector
+DVI_VCC

1

2
7307@ 5.6K_0402_5%

1

2
7307@ 5.6K_0402_5%

D25
DVI@ RB411D_SOT23

JP16
1
2
RP27
1
2
RP26
1
2
RP25

15 VGA_DVI_TXD015 VGA_DVI_TXD0+
15 VGA_DVI_TXD115 VGA_DVI_TXD1+
15 VGA_DVI_TXD215 VGA_DVI_TXD2+

DVI_TXD04
DVI_TXD0+
3
DVI@ 10_0404_4P2R_5%
DVI_TXD14
DVI_TXD1+

3
DVI@ 10_0404_4P2R_5%
DVI_TXD24
DVI_TXD2+
3
DVI@ 10_0404_4P2R_5%

B

2
1
RP28

15 VGA_DVI_TXC+
15 VGA_DVI_TXC-

DVI_TXC+
3
DVI_TXC4
DVI@ 10_0404_4P2R_5%

17
18

TMDS_DATA0TMDS_DATA0+

9
10

TMDS_DATA1TMDS_DATA1+

1
2

TMDS_DATA2TMDS_DATA2+

12
13

TMDS_DATA3TMDS_DATA3+

4
5

TMDS_DATA4TMDS_DATA4+

20
21

TMDS_DATA5TMDS_DATA5+

23
24

TMDS_Clock+
TMDS_Clock-

Place close to CH7307C

+5V

14

1

W=40mils

DDC_CLOCK

DVI_SCLK

DDC_DATA

7

DVI_SDATA

16

TMDS_DATA2/4 shield
TMDS_DATA1/3 shield
TMDS_DATA0/5 shield
TMDS_Clock shield

3
11
19
22

GND

15

+5VS

C1
0.1U_0402_16V4Z
DVI@

2
6

Hot Plug Detect

2

1

B

+DVI_VCC

1

2 DVI@ 0_0402_5%

DVI_SDATA

1

1

R3

R2
DVI_DET

15 DVI_DET

1

DVI_SCLK
D2
@ SKS10-04AT_TSMA

2
20K_0402_5%
DVI@
R7
VGA@
100K_0402_5%

A

2

15 VGA_DVI_SDATA

2 DVI@ 0_0402_5%

DVI@ SUYIN_070939FR024S531PL

2

A

1

R482
4.7K_0402_5%
DVI@
2

2
15 VGA_DVI_SCLK

R4

Analog VSYNC

1

1

8
R481
4.7K_0402_5%
DVI@

(HDQ70)

2005/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/20

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

CH7307 & DVI-D Connector

Size
B
Date:

Document Number

Rev
0.3

HBL50 LA-2921P
Friday, November 11, 2005

Sheet
1

25

of

59