Acer aspire e5 432 (compal LA c371p) robin BA MB A4WAL LA c371p r10 1 acer aspire e14 e5 432g 2

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Model Name : A4WAL
File Name : LA-C371P

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m

1

se
fix
.co

Compal Confidential

2

2

.ro

A4WAL M/B Schematics Document

w
w
w

Intel Braswell-M/D + N16X

3

2015-03-04
REV:1.0

3

4

4

PCB@
DAX PCB 1BW LA-C371P REV0 MB 1

Part Number
DA6001BJ000

Description
PCB 1BW LA-C371P REV0 MB 1

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/19

2015/03/18

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Cover Page
Rev
1.0

A4WAL_Braswell-M/D_LA-C371P

Date:
A

B

C

D

Wednesday, March 04, 2015

Sheet
E

1

of

55


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B

C

D

E

CRT Conn.
P.27

eDP Conn.
Nvidia N16V-GL
with DDR3 x8

port 0/1

port 2

1

P.13

PCIe 2.0 x 2
5GT/s

P.24

port 1

204pin DDR3L-SO-DIMM X1

page 15~23

DP to VGA
Realtek RTD2168P.26

1

Memory BUS

204pin DDR3L-SO-DIMM X1

Dual Channel

port 0

P.14

1.35V DDR3L 1600
P.25

DDI x3

P.25

USB2.0 x4

port 0

port 1

port 2

port 3

HDMI Conn.
port 3

RJ45 Conn.

port 4

PCIE 2.0 x1

Braswell-M/D

LAN(GbE) / Card Reader
RTL8411B

USB 3.0
Conn P.33

P.28

2

USB 3.0
Conn P.33

Touch Panel
Conn.

HD Camera
Conn. P.24

USB HUB
GL850G

P.24

P.31
2

SOC

Card Reader
2 in 1(SD) P.29

Port1

USB Charger
SLG55594

FCBGA 1170 Pin

USB3.0 x2
port 0

SATA 3.0 x2
P.32

port 1

P.32

Port2

USB 2.0
Conn P.33

port 1

NGFF
WLAN/BT

PCIE 2.0 x1

P.30

port 0
page 05~12

HD Audio

HDA Codec
ALC283/255
P.36

I2C BUS

LPC BUS

SPI

SATA ODD Conn.

3

3

EC
ENE KB9022

SATA HDD Conn.

RTC CKT.

SPI ROM
1.8V (8MB)

Speaker

Int. MIC

P.36

P.07

P.36

UAJ
on Sub/B

P.33

P.34

P.08
P.35

P.35

DC/DC Interface CKT.
P.38

Sub Board
Power Circuit DC/DC
P.39~P.52

4

LS_XXXXP USB/Audio

P.33

Touch Pad
PS2/I2C

Int.KBD

LED/Power On/Off

4

P.35

Fan Control

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

P.37

2014/03/19

2015/03/18

Deciphered Date

Title

Block Diagrams

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
A

B

C

D

Wednesday, March 04, 2015

Sheet
E

2

of

55

Rev
1.0


A

B

C

Voltage Rails

2

E

Board ID / SKU ID Table for AD channel

Power Plane

1

D

Description

S0

S3

S4/S5

+19V_VIN

19V Adapter power supply

ON

ON

ON

BATT+

12V Battery power supply

ON

ON

ON

+19VB

AC or battery power rail for power circuit. (19V/12V)

ON

ON

ON

+RTCVCC

RTC Battery Power

ON

ON

ON

+1.05VALW

+1.05v Always power rail

ON

ON

ON

+1.15VALW

+1.15v Always power rail

ON

ON

ON

+1.24VALW

+1.24v Always power rail

ON

ON

ON

+1.8VALW

+1.8v Always power rail

ON

ON

ON

+3VALW

+3.3v Always power rail

ON

ON

ON

+5VALW

+5.0v Always power rail

ON

ON

ON

+1.35V

+1.35V power rail for DDR3L

ON

ON

OFF

+3V_PTP

+3.3V power rail for PTP

ON

ON

OFF

+SOC_VCC

Core voltage for SOC

ON

OFF

OFF

BOARD ID Table_LA-C371P

Board ID
01
02
03

PCB Revision
EVT_LA-C371PR01
DVT_LA-C371PR02
PVT_LA-C371PR10
1

+SOC_VGG

GFX voltage for SOC

ON

OFF

OFF

+0.675VS

+0.675V power rail for DDR3L Terminator

ON

OFF

OFF

+1.8VS

+1.8v system power rail

ON

OFF

OFF

+3VS

+3.3v system power rail

ON

OFF

OFF

+5VS

+5.0v system power rail

ON

OFF

OFF

+3VSDGPU

+3.3V dGPU power rail

ON**

OFF

OFF

+VGA_CORE

Core voltage for dGPU

ON**

OFF

OFF

+1.5VSDGPU

+1.5V dGPU power rail

ON**

OFF

OFF

4319X5BOL01

SMT MB AC371 A4WAL UMA HDMI

1DMIC@/255@/EMC@/HDD@/HUB@/NBYOC@/KB@/PCB@/LPC3V@/TSI@/UMA@/QHAX@

+1.05VSDGPU

+1.05V dGPU power rail

ON**

OFF

OFF

4319X5BOL02

SMT MB AC371 A4WAL DIS N16V-GM HDMI

1DMIC@/255@/EMC@/NGC6@/HDD@/HUB@/NBYOC@/KB@/PCB@/VGM@/LPC3V@/TSI@/VGA@/QHAW@

4319X5BOL03

SMT MB AC371 A4WAL DIS N16S-GT HDMI

1DMIC@/255@/EMC@/GC6@/HDD@/HUB@/NBYOC@/KB@/PCB@/SGT@/LPC3V@/TSI@/VGA@/QHAW@

4319X5BOL04

SMT MB AC371 A4WAL DIS N16V-GM 4G HDMI

1DMIC@/255@/EMC@/NGC6@/HDD@/HUB@/NBYOC@/KB@/PCB@/VGM@/LPC3V@/TSI@/VGA@/DR@/QHAW@

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

4319X5BOL05

SMT MB AC371 A4WAL DIS N16S-GT 4G HDMI

1DMIC@/255@/EMC@/GC6@/HDD@/HUB@/NBYOC@/KB@/PCB@/SGT@/LPC3V@/TSI@/VGA@/DR@/QHAW@

Note : ON** dGPU optimus on

4319X5BOL06

SMT MB AC371 A4WAL UMA QHAW HDMI

1DMIC@/255@/EMC@/HDD@/HUB@/NBYOC@/KB@/PCB@/LPC3V@/TSI@/UMA@/QHAW@

4319X5BOL07

SMT MB AC371 A4WAL DIS GM2G QHAX HDMI

1DMIC@/255@/EMC@/NGC6@/HDD@/HUB@/NBYOC@/KB@/PCB@/VGM@/LPC3V@/TSI@/VGA@/QHAX@

4319X5BOL08

SMT MB AC371 A4WAL DIS GM4G QHAX HDMI

1DMIC@/255@/EMC@/NGC6@/HDD@/HUB@/NBYOC@/KB@/PCB@/VGM@/LPC3V@/TSI@/VGA@/DR@/QHAX@

43 level BOM table
43 Level

Description

BOM Structure
2

EC SMBUS Routing Table
EC
EC_SMB_CK1
EC_SMB_DA1

Power

BAT

CHGR

SOC

DGPU

+3VALW

V

V

X

X

EC_SMB_CK2
EC_SMB_DA2
3

+3VS

X

X

V

BOM Option Table

V

SOC SMBUS Routing Table
Power

SOC

DIMM1 DIMM2 NGFF

XDP

EC

DGPU

RTD2168

X

V

V

V

SMB Address
SOC_SMBCLK
SOC_SMBDATA

+1.8VALW
to +3VS

V

V

V

I2C Map
Power

I2C Address
+1.8VALW to +TS_PWR
I2C Port2
I2C Port5

+1.8VALW to +3V_PTP

Touch PAD

0xXX
X
V

Touch Panel

0xXX

Item
BOM Structure
Unpop
@
CONN@
Connector
EMC requirement
EMC@
EMC requirement depop
@EMC@
Touch Screen I2C
TSI@

KB BL
KB@
TPM
TPM@
NTPM
NTPM@
DBG@
Power Button
dGPU
VGA@
N16S-GT SKU
SGT@
N16V-GM SKU
VGM@
CODEC(ALC255)
255@
CODEC(ALC283)
283@
Non GPU CG6 Function
NGC6@
GPU CG6 Function
GC6@

BOM Option Table
Item
X76 VRAM
with BYOC
without BYOC
EA Serial HDD
BA Serial HDD

non USB HUB
USB HUB
Dual Rank
G-sensor
CPU QHAX
CPU QHAW

BOM Structure
X76@
BYOC@
NBYOC@
HDD@
BA@
NHUB@
HUB@
DR@
GSEN@
QHAX@
QHAW@

3

V
X

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/19

2015/03/18

Deciphered Date

Title

Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
A

B

C

D

Wednesday, March 04, 2015

Sheet
E

3

of

55

Rev
1.0


A

B

VR_ON

NCP81201MNTXG 7000mA
(PU901)
NCP81201MNTXG
(PU902)

1

C

EC_EN_1.05VALW

11000mA

SY8288RAC
(PU601)

5400mA

RT8207MZQW
(PU501)

5900mA

D

E

+SOC_VCC
+SOC_VGG

+1.05VALWP

VGA_PWROK

EM5209VF
(U60)

1

1060mA

+1.05VSDGPU

ADAPTER
SYSON

+1.35VP

SUSP#

PJ501

+19VB

CHARGER

3V_EN

SY8286BRAC
(PU401)

+0.675VSP
+1.35V

+3VALWP

BATTERY

SUSP#

SY8003DFC
(PU701)

700mA

+1.24VALW_PWRGD

SY8032ABC
(PU702)

597mA

+1.05VALW_PWRGD

G971ADJF11U
(PU801)

550mA

2

+1.15VALWP

PJ701

+1.15VALW

110mA

EM5209VF
(U59)

+1.8VALWP
+1.24VALWP

PJ802

+1.8VS
2

+1.24_1.35VALW

0 ohm

+1.24_1.35VALW_ICLK

0 ohm

+1.24_1.35VALW_USBVDDQ
SUSP#

EM5209VF
(U11)

3135mA

LAN_PWR_EN

SY6288C20AAC
(U67)

1400mA

JP8

+3VS

+3VS_WLAN

ENVDD

G5243AT11U
(U8)

+LCDVDD

DGPU_PWR_EN

G5243T11U
(U12)

+3VSDGPU_AON

G5243T11U
(U14)

+3VSDGPU_MAIN

+3V_LAN

3VSDGPU_MAIN_EN
3

3

EC_ON

SY8286CRAC
(PU402)

+5VALWP

SUSP#

4868mA

EM5209VF
(U11)

J1

+5VS

+VDDA

0 ohm

ODD_EN

USB_PWR_EN

+3VSDGPU_AON

4

1.5VS_DGPU_PWR_EN

RT8812AGQW
(PU1201)

26000mA

SY8288RAC
(PU1101)

10000mA

+VGA_CORE

SY6288C20AAC
(U25)

USB_CHARGE_2A

+5VS_HDD
G5243AT11U
(U13)

+5VS_ODD

+USB3_VCCA

SY6288C20AAC
(U25)

+USB3_VCCB

4

+1.5VSDGPU

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/19

2015/03/18

Deciphered Date

Title

Power Rail

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

A4WAL_Braswell-M/D_LA-C371P

Date:
A

B

C

D

Wednesday, March 04, 2015

Sheet
E

4

of

55


5

4

3

DDR_A_D[0..63]

DDR_A_DQS#[0..7]
DDR_A_MA[0..15]

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

D

<13>
<13>
<13>

BD49
BD47
BF44
BF48
BB49
BJ45
BE52
BD44
BE46
BB46
BH48
BD42
BH47
BJ48
BC42
BB47
BF52
AY40
BH46

DDR_A_BS2
DDR_A_BS1
DDR_A_BS0

BG45
BA40
BH44
AU38
AY38

<13> DDR_A_CAS#
<13> DDR_A_RAS#
<13> DDR_A_WE#
<13> DDR_A_CS1#
<13> DDR_A_CS0#

BD38
BF38
AY42

<13> DDR_A_CLK1
<13> DDR_A_CLK1#
<13> DDR_A_CKE1

BD40
BF40
BB44

<13> DDR_A_CLK0
<13> DDR_A_CLK0#
<13> DDR_A_CKE0

AT30

AU30

C

<13>
<13>

AV36
BA38

DDR_A_ODT0
DDR_A_ODT1

AT28
AU28

+DDRA_SOC_VREFCA
+DDRA_SOC_VREFDQ

BA42
AV28

<13> DDR_A_RST#
<43> DDR_PWROK

DDRA_RCOMP BA28
<13>

DDR_A_DM[0..7]

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0

BH30
BD32
AY36
BG41
BA53
AP44
AT48
AP52

DDR_A_DQS7 BH32
DDR_A_DQS#7 BG31
DDR_A_DQS6 BC30
DDR_A_DQS#6 BC32
DDR_A_DQS5 AT32
DDR_A_DQS#5 AT34
DDR_A_DQS4 BH40
DDR_A_DQS#4 BG39
DDR_A_DQS3 AY52
DDR_A_DQS#3 BA51
DDR_A_DQS2 AT42
DDR_A_DQS#2 AT41

DDR_A_DQS1 AV47
DDR_A_DQS#1 AV48
DDR_A_DQS0 AM52
DDR_A_DQS#0 AM51

B

DDR_B_D[0..63]

<13>

DDR_B_DQS[0..7]

<13>

DDR_B_DQS#[0..7]

CHV_MCP_EDS

USOC1A

<14>
DDR3_M0_DQ_63
DDR3_M0_DQ_62
DDR3_M0_DQ_61
DDR3_M0_DQ_60
DDR3_M0_DQ_59
DDR3_M0_DQ_58
DDR3_M0_DQ_57
DDR3_M0_DQ_56

DDR3_M0_DQ_55
DDR3_M0_DQ_54
DDR3_M0_DQ_53
DDR3_M0_DQ_52
DDR3_M0_DQ_51
DDR3_M0_DQ_50
DDR3_M0_DQ_49
DDR3_M0_DQ_48

DDR3_M0_BS_2
DDR3_M0_BS_1
DDR3_M0_BS_0

DDR3_M0_DQ_47
DDR3_M0_DQ_46
DDR3_M0_DQ_45
DDR3_M0_DQ_44
DDR3_M0_DQ_43
DDR3_M0_DQ_42
DDR3_M0_DQ_41
DDR3_M0_DQ_40

DDR3_M0_CASB
DDR3_M0_RASB
DDR3_M0_WEB
DDR3_M0_CSB_1
DDR3_M0_CSB_0
DDR3_M0_CK_1
DDR3_M0_CKB_1
DDR3_M0_CKE_1

DDR3_M0_DQ_39
DDR3_M0_DQ_38
DDR3_M0_DQ_37
DDR3_M0_DQ_36
DDR3_M0_DQ_35
DDR3_M0_DQ_34
DDR3_M0_DQ_33
DDR3_M0_DQ_32

DDR3_M0_CK_0
DDR3_M0_CKB_0
DDR3_M0_CKE_0
RSVD1
RSVD2
DDR3_M0_ODT_0
DDR3_M0_ODT_1
DDR3_M0_OCAVREF
DDR3_M0_ODQVREF
DDR3_M0_DRAMRSTB
DDR3_DRAM_PWROK
DDR3_M0_RCOMPPD
DDR3_M0_DM_7
DDR3_M0_DM_6
DDR3_M0_DM_5
DDR3_M0_DM_4
DDR3_M0_DM_3
DDR3_M0_DM_2
DDR3_M0_DM_1
DDR3_M0_DM_0

DDR3_M0_DQ_31
DDR3_M0_DQ_30
DDR3_M0_DQ_29
DDR3_M0_DQ_28
DDR3_M0_DQ_27
DDR3_M0_DQ_26
DDR3_M0_DQ_25
DDR3_M0_DQ_24
DDR3_M0_DQ_23
DDR3_M0_DQ_22
DDR3_M0_DQ_21
DDR3_M0_DQ_20
DDR3_M0_DQ_19
DDR3_M0_DQ_18
DDR3_M0_DQ_17
DDR3_M0_DQ_16
DDR3_M0_DQ_15
DDR3_M0_DQ_14
DDR3_M0_DQ_13
DDR3_M0_DQ_12
DDR3_M0_DQ_11
DDR3_M0_DQ_10
DDR3_M0_DQ_9
DDR3_M0_DQ_8

DDR3_M0_DQS_7
DDR3_M0_DQSB_7
DDR3_M0_DQS_6
DDR3_M0_DQSB_6

DDR3_M0_DQS_5
DDR3_M0_DQSB_5
DDR3_M0_DQS_4
DDR3_M0_DQSB_4
DDR3_M0_DQS_3
DDR3_M0_DQSB_3
DDR3_M0_DQS_2
DDR3_M0_DQSB_2
DDR3_M0_DQS_1
DDR3_M0_DQSB_1
DDR3_M0_DQS_0
DDR3_M0_DQSB_0

DDR3_M0_DQ_7
DDR3_M0_DQ_6
DDR3_M0_DQ_5
DDR3_M0_DQ_4
DDR3_M0_DQ_3
DDR3_M0_DQ_2
DDR3_M0_DQ_1
DDR3_M0_DQ_0

BG33
BH28
BJ29
BG28
BG32
BH34
BG29
BJ33

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56

BD28
BF30
BA34
BD34
BD30
BA32
BC34
BF34

DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48

AV32
AV34

BD36
BF36
AU32
AU34
BA36
BC36

DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40

BH38
BH36
BJ41
BH42
BJ37
BG37
BG43
BG42

DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35

DDR_A_D34
DDR_A_D33
DDR_A_D32

BB51
AW53
BC52
AW51
AV51
BC53
AV52
BD52

DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24

AV42
AP41
AV41
AT44
AP40
AT38
AP42
AT40

DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16

AV45
AY50
AT50
AP47
AV50
AY48
AT47
AP48

DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8

AP51
AR53

AK52
AL53
AR51
AT52
AL51
AK51

DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

DDR_B_MA[0..15]

<14>
<14>
<14>

DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8

DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

BD5
BD7
BF10
BF6
BB5
BJ9
BE2
BD10
BE8
BB8
BH6
BD12
BH7
BJ6
BC12
BB7
BF2
AY14
BH8

DDR_B_BS2

DDR_B_BS1
DDR_B_BS0

BG9
BA14
BH10
AU16
AY16

<14> DDR_B_CAS#
<14> DDR_B_RAS#
<14> DDR_B_WE#
<14> DDR_B_CS1#
<14> DDR_B_CS0#

BD16
BF16
AY12

<14> DDR_B_CLK1
<14> DDR_B_CLK1#
<14> DDR_B_CKE1

BD14
BF14
BB10

<14> DDR_B_CLK0
<14> DDR_B_CLK0#
<14> DDR_B_CKE0

AT24
AU24
<14>
<14>

AV18
BA16

DDR_B_ODT0
DDR_B_ODT1

AT26
AU26

+DDRB_SOC_VREFCA
+DDRB_SOC_VREFDQ

<9>

BA12
AV26

<14> DDR_B_RST#
DDR_CORE_PWROK

DDRB_RCOMP BA26
<14>

DDR_B_DM[0..7]

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

BH24
BD22
AY18
BG13
BA1
AP10
AT6
AP2

DDR_B_DQS7 BH22
DDR_B_DQS#7 BG23
DDR_B_DQS6 BC24
DDR_B_DQS#6 BC22
DDR_B_DQS5 AT22
DDR_B_DQS#5 AT20
DDR_B_DQS4 BH14
DDR_B_DQS#4 BG15
AY2
DDR_B_DQS3
DDR_B_DQS#3 BA3

DDR_B_DQS2 AT12
DDR_B_DQS#2 AT13
DDR_B_DQS1 AV7
DDR_B_DQS#1 AV6
DDR_B_DQS0 AM2
DDR_B_DQS#0 AM3

1 OF 13
BSW-MCP-EDS_FCBGA1170

<14>
<14>
<14>

CHV_MCP_EDS

USOC1B

DDR0

DDR3_M0_MA_15
DDR3_M0_MA_14
DDR3_M0_MA_13
DDR3_M0_MA_12
DDR3_M0_MA_11
DDR3_M0_MA_10
DDR3_M0_MA_9
DDR3_M0_MA_8
DDR3_M0_MA_7
DDR3_M0_MA_6

DDR3_M0_MA_5
DDR3_M0_MA_4
DDR3_M0_MA_3
DDR3_M0_MA_2
DDR3_M0_MA_1
DDR3_M0_MA_0

1

<13>

DDR_A_DQS[0..7]

<13>

2

DDR3_M1_MA_15
DDR3_M1_MA_14
DDR3_M1_MA_13
DDR3_M1_MA_12
DDR3_M1_MA_11
DDR3_M1_MA_10
DDR3_M1_MA_9
DDR3_M1_MA_8
DDR3_M1_MA_7
DDR3_M1_MA_6
DDR3_M1_MA_5
DDR3_M1_MA_4
DDR3_M1_MA_3

DDR3_M1_MA_2
DDR3_M1_MA_1
DDR3_M1_MA_0

DDR1

DDR3_M1_DQ_63
DDR3_M1_DQ_62
DDR3_M1_DQ_61
DDR3_M1_DQ_60
DDR3_M1_DQ_59
DDR3_M1_DQ_58
DDR3_M1_DQ_57
DDR3_M1_DQ_56
DDR3_M1_DQ_55
DDR3_M1_DQ_54
DDR3_M1_DQ_53
DDR3_M1_DQ_52
DDR3_M1_DQ_51
DDR3_M1_DQ_50
DDR3_M1_DQ_49
DDR3_M1_DQ_48

DDR3_M1_BS_2
DDR3_M1_BS_1
DDR3_M1_BS_0

DDR3_M1_DQ_47
DDR3_M1_DQ_46
DDR3_M1_DQ_45

DDR3_M1_DQ_44
DDR3_M1_DQ_43
DDR3_M1_DQ_42
DDR3_M1_DQ_41
DDR3_M1_DQ_40

DDR3_M1_CASB
DDR3_M1_RASB
DDR3_M1_WEB
DDR3_M1_CSB_1
DDR3_M1_CSB_0
DDR3_M1_CK_1
DDR3_M1_CKB_1
DDR3_M1_CKE_1

DDR3_M1_DQ_39
DDR3_M1_DQ_38
DDR3_M1_DQ_37
DDR3_M1_DQ_36
DDR3_M1_DQ_35
DDR3_M1_DQ_34
DDR3_M1_DQ_33
DDR3_M1_DQ_32

DDR3_M1_CK_0
DDR3_M1_CKB_0
DDR3_M1_CKE_0
RSVD1
RSVD2

DDR3_M1_DQ_31
DDR3_M1_DQ_30
DDR3_M1_DQ_29
DDR3_M1_DQ_28
DDR3_M1_DQ_27
DDR3_M1_DQ_26
DDR3_M1_DQ_25
DDR3_M1_DQ_24

DDR3_M1_ODT_0
DDR3_M1_ODT_1
DDR3_M1_OCAVREF
DDR3_M1_ODQVREF
DDR3_M1_DRAMRSTB
DDR3_VCCA_PWROK

DDR3_M1_DQ_23
DDR3_M1_DQ_22
DDR3_M1_DQ_21
DDR3_M1_DQ_20
DDR3_M1_DQ_19
DDR3_M1_DQ_18
DDR3_M1_DQ_17
DDR3_M1_DQ_16

DDR3_M1_RCOMPPD
DDR3_M1_DM_7
DDR3_M1_DM_6
DDR3_M1_DM_5
DDR3_M1_DM_4

DDR3_M1_DM_3
DDR3_M1_DM_2
DDR3_M1_DM_1
DDR3_M1_DM_0

DDR3_M1_DQ_15
DDR3_M1_DQ_14
DDR3_M1_DQ_13
DDR3_M1_DQ_12
DDR3_M1_DQ_11
DDR3_M1_DQ_10
DDR3_M1_DQ_9
DDR3_M1_DQ_8

DDR3_M1_DQS_7
DDR3_M1_DQSB_7
DDR3_M1_DQS_6
DDR3_M1_DQSB_6
DDR3_M1_DQS_5
DDR3_M1_DQSB_5
DDR3_M1_DQS_4
DDR3_M1_DQSB_4
DDR3_M1_DQS_3
DDR3_M1_DQSB_3
DDR3_M1_DQS_2
DDR3_M1_DQSB_2
DDR3_M1_DQS_1
DDR3_M1_DQSB_1
DDR3_M1_DQS_0
DDR3_M1_DQSB_0

DDR3_M1_DQ_7
DDR3_M1_DQ_6
DDR3_M1_DQ_5
DDR3_M1_DQ_4
DDR3_M1_DQ_3
DDR3_M1_DQ_2
DDR3_M1_DQ_1
DDR3_M1_DQ_0

BG21
BH26
BJ25
BG26
BG22
BH20
BG25
BJ21

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56

BD26
BF24

BA20
BD20
BD24
BA22
BC20
BF20

DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48

AV22
AV20
BD18
BF18
AU22
AU20
BA18
BC18

DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43

DDR_B_D42
DDR_B_D41
DDR_B_D40

BH16
BH18
BJ13
BH12
BJ17
BG17
BG11
BG12

DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32

BB3
AW1
BC2
AW3
AV3
BC1
AV2
BD2

DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24

AV12
AP13
AV13
AT10
AP14
AT16
AP12
AT14

DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16

AV9
AY4

AT4
AP7
AV4
AY6
AT7
AP6

DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8

AP3
AR1
AK2
AL1
AR3
AT2
AL3
AK3

DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3

DDR_B_D2
DDR_B_D1
DDR_B_D0

D

C

B

2 OF 13
BSW-MCP-EDS_FCBGA1170

close to SOC pin
Close To SOC Pin
182_0402_1%
182_0402_1%

1
1

2 R963
2 R964

Close To SOC Pin

DDRA_RCOMP
DDRB_RCOMP
+1.35V_SOC

EMC@
1
2 DDR_CORE_PWROK
C1159
.1U_0402_16V7K

V0.2 modify

1

2
@
R980
4.7K_0402_1%

1

2
@
R974
4.7K_0402_1%

+DDRA_SOC_VREFCA

+1.35V_SOC

V0.2 modify

@
1

1

@
C1136
.1U_0402_16V7K

2

1

+DDRB_SOC_VREFCA

2
R1064
4.7K_0402_1%
@
2
R979
4.7K_0402_1%

1

2

@
C1138
.1U_0402_16V7K

ESD request 0211
+1.35V_SOC

A

S IC FH8066501715905 QHAX B1 1.36G FCBGA15 1380
SA00008GO00

USOC1
QHAW@

+DDRA_SOC_VREFDQ

1

2
@
R965
4.7K_0402_1%

1

1

2
@
R966
4.7K_0402_1%

2

USOC1

QHAX@

Issued Date

+DDRB_SOC_VREFDQ

@
2
R971
4.7K_0402_1%
@
1
2
R967
4.7K_0402_1%
1

@
C1132
.1U_0402_16V7K

1

2

2014/03/19

@
C1137
.1U_0402_16V7K

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

S IC FH8066501715905 QHAW B1 1.36G FCBGA15 1380
SA00008GO10

+1.35V_SOC

2015/03/18

Deciphered Date

Title

VLV-M SOC Memory DDR3L

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
5

4

3

2

Wednesday, March 04, 2015

Sheet
1

5

of

55

Rev
1.0


4

3

2

1

+1.8VALW
5

eDP

NC
A

M42
K42

<24> EDP_AUXP
<24> EDP_AUXN
<31>

R51

EDP_HPD#

<24>

DDI1_ENBKL
DDI1_PWM
ENVDD
1 R986
2 DDI1_RCOMPP
402_0402_1% DDI1_RCOMPN

ENVDD

F40
G40

<26> SOC_DDI2_TXP0
<26> SOC_DDI2_TXN0

J40
K40

<26> SOC_DDI2_TXP1
<26> SOC_DDI2_TXN1

F42
G42

DP to CRT
Translater

D44
F44
D48
C49

<26> SOC_DDI2_AUXP
<26> SOC_DDI2_AUXN
SOC_DDI2_HPD#

U51

T51
T52
B53
A52
E52
D52
B50
B49
E53
C53
A51
A49
G44

VGA GPIO reserve
VGA_SELECT3

RSVD17
RSVD16
MCSI_COMP

DDI1_TXP_0
DDI1_TXN_0

1.35V

DDI1_TXP_1
DDI1_TXN_1

1.35V

DDI1_TXP_2
DDI1_TXN_2

1.35V

DDI1_TXP_3
DDI1_TXN_3

1.35V

DDI1_AUXP
DDI1_AUXN
HV_DDI1_HPD

DDI1

1.8V

GP_CAMERASB09
GP_CAMERASB10
GP_CAMERASB11

1.35V

1.35V

DDI2_TXP_2
DDI2_TXN_2

1.35V

DDI2_TXP_3
DDI2_TXN_3

1.35V

DDI2_AUXP
DDI2_AUXN

1.35V

1.8V

SDMMC1

DDI2

SDMMC1_D0
SDMMC1_D1
SDMMC1_D2
SDMMC1_D3_CD_B
MMC1_D4_SD_WE
MMC1_D5
MMC1_D6
MMC1_D7
MMC1_RCLK
SDMMC1_RCOMP
SDMMC2_CLK
SDMMC2_CMD

1.8V

HV_DDI2_DDC_SCL
HV_DDI2_DDC_SDA
RSVD6
RSVD3
RSVD9
RSVD8
RSVD5
RSVD4
RSVD10
RSVD7
RSVD2
RSVD1
RSVD11

SDMMC1_CLK
SDMMC1_CMD

1.35V

DDI2_TXP_1
DDI2_TXN_1

HV_DDI2_HPD

3
R1003

1.8V

SDMMC2

SDMMC2_D0
SDMMC2_D1
SDMMC2_D2
SDMMC2_D3_CD_B

1.8V
1.8V/3.3V

SDMMC3_CLK
SDMMC3_CMD
SDMMC3_CD_B

NC's

EC_KBRST#

1.8V/3.3V
SDMMC3

SDMMC3_D0
SDMMC3_D1
SDMMC3_D2
SDMMC3_D3

1.8V SDMMC3_1P8_EN
1.8V SDMMC3_PWR_EN_B

1.8V/3.3V SDMMC3_RCOMP

M6
M4
P9
P7
T6
T7
T10
T12
T13
P13

DGPU_PWR_EN1 <38>
DGPU_HOLD_RST#_SOC1.8V

SOC_DDI2_HPD#

<31>

D

2
G

Q79
L2N7002LT1G_SOT23-3

DDI2_HPD

<26>

S

TP_INT#

<31>

K10
K9

+1.8VALW

DGPU_PRSNT#

V0.2 modify
R641 1
R642 1
R970 1

@
@

210K_0402_5%
210K_0402_5%

GP_CAMERASB08
GP_CAMERASB09

UMA

H

DIS

L*

+1.8VALW

UMA@
R1046
10K_0402_5%

2 100_0402_1%
DGPU_PRSNT#

MMC1_RCOMP If unused, terminate 100 ? ±1% resistor near to SoC.
Braswell PDG_0p95 P.200

M12
M10
K7
K6

G_INT_R

B

VGA@
R1045

10K_0402_5%

<31>

EC_LID_OUT#

<34>

F2
D2
K3

VRAM RANK GPIO

J1
J3
H3
G2

N16S-GT GPIO

VGA_SELECT2

K2
L3
P12
R969
80.6_0402_1%

BSW-MCP-EDS_FCBGA1170

VGA_SELECT1

+1.8VALW

Dual Rank

H

Single Rank

L

R992
1K_0402_5%
DR@
VGA_SELECT2

+1.8VALW

N16S-GT

H

N16V-GM

L

R1036
1K_0402_5%

SGT@
VGA_SELECT1

V0.2 modify
R1008
20K_0402_5%
@

Checklist R0.95 Page 194
RCOMP=80ohm_1% (not exist in ISPD)

V0.2 modify

C

R637
10K_0402_5%

<34>

2

1
2

2 150_0402_1%

R1037
10K_0402_5%
VGM@

2

VGA_SELECT3

NL17SZ07DFT2G_SC70-5
SA00004BV00

M7
P6

3 OF 13
R1033
1K_0402_5%
@

L

1

GP_CAMERASB09
TP_INT#

+1.8VALW

H

100K_0804_8P4R_5%

<24>

DP to VGA

AB41
AB45
AB44
DGPU_PRSNT#
AC53
DGPU_PWR_EN1
AB51 DGPU_HOLD_RST#_SOC1.8V
AB52
VGA_SELECT1
AA51
VGA_SELECT2
AB40
VGA_SELECT3
Y44
GP_CAMERASB08
Y42
Y41
V40

INVT_PWM_SOC

+1.8VALW

T50
T48
P44

INVT_PWM_SOC

1.8V

PANEL1_BKLTEN 1.8V
PANEL1_BKLTCTL 1.8V
PANEL1_VDDEN
1.8V
DDI1_PLLOBS_P
1.35V
DDI1_PLLOBS
DDI2_TXP_0
DDI2_TXN_0

GP_CAMERASB00
GP_CAMERASB01
GP_CAMERASB02
GP_CAMERASB03
GP_CAMERASB04
GP_CAMERASB05
GP_CAMERASB06
GP_CAMERASB07
GP_CAMERASB08

P47
P45
M48
M47

2

B

P51
P52
R53
F47
F49

1.8V
1.8V
1.8V
1.35V

4

Y
A

1

M52
M51

eDP Panel

PANEL0_BKLTEN
PANEL0_BKLTCTL
PANEL0_VDDEN
DDI0_PLLOBS_P

DDI0_PLLOBS

MCSI_2_DP_0
MCSI_2_DN_0
MCSI_2_DP_1
MCSI_2_DN_1

1.8V

NC

2

L53
L51

HV_DDI0_DDC_SCL
HV_DDI0_DDC_SDA

2

DDI1_PWM

1

K51
K52

<24> EDP_TXP1
<24> EDP_TXN1

1.8V

1
P50
P48

1
2
3
4

2

J51
H51

<24> EDP_TXP0
<24> EDP_TXN0

C

MCSI_2_CLKP
MCSI_2_CLKN

U64

8
7
6

5

1

1 R968
2 DDI0_RCOMPP
402_0402_1% DDI0_RCOMPN

Y51
Y52
V52
V51
W53
F38
G38

1.35V

DDI1_ENBKL
ENVDD
DDI1_PWM

2

HDMI_DDCCLK
HDMI_DDCDATA

HV_DDI0_HPD

RP41

+1.8VALW

1

<25>
<25>

DDI0_AUXP
DDI0_AUXN

1.24V

2

1 0_0402_5%

@

2

HDMI_HPD#

1.35V

INVT_PWM_SOC 1
4.7K_0402_5%
R1161

A

A

1

R1035
20K_0402_5%
@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/19

2015/03/18

Deciphered Date

Title

VLV-M SOC Display

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
5

D

1

W51

<25>

1.35V

DDI0_TXP_3
DDI0_TXN_3

2

1

H47
H46

DDI0_TXP_2
DDI0_TXN_2

Y47
Y48
V45
V47
V50
V48
T41
T42

1
ENBKL
@
4.7K_0402_5%
R1159

3

G53
G52

MCSI_1_DP_0
MCSI_1_DN_0
MCSI_1_DP_1
MCSI_1_DN_1
MCSI_1_DP_2
MCSI_1_DN_2
MCSI_1_DP_3
MCSI_1_DN_3

+3VS

T44
T45

5

HDMI_CLK+
HDMI_CLK-

DDI0

R1142 2

P

HDMI_TX0+
HDMI_TX0-

<25>
<25>

MCSI_1_CLKP
MCSI_1_CLKN

<34>

G

<25>
<25>

1.35V

K48
K47

3

F53
F52

DDI0_TXP_1
DDI0_TXN_1

RSVD14
RSVD13

ENBKL

NL17SZ07DFT2G_SC70-5
SA00004BV00
@

1

H49
H50

1.35V

2

HDMI_TX1+
HDMI_TX1-

DDI0_TXP_0
DDI0_TXN_0

ENBKL

1

<25>
<25>

D50
C51

M44
K44

1

HDMI_TX2+
HDMI_TX2-

MCSI and Camera interface

HDMI

<25>
<25>

4

Y

2

D

RSVD15
RSVD12

U61

P

1
DDI1_ENBKL

G

CHV_MCP_EDS

USOC1C

2

5

4

3

2

Wednesday, March 04, 2015

Sheet
1

6

of

55

Rev
1.0


5

4

3

2

1

Follow DVR1044_ACER_HSIO Mapping Design Guide_V1p0

D

D

CHV_MCP_EDS

USOC1D

<15> PEG_HTX_C_GRX_P0
<15> PEG_HTX_C_GRX_N0
<15> PEG_GTX_C_HRX_P0
<15> PEG_GTX_C_HRX_N0

dGPU

<15> PEG_HTX_C_GRX_P1
<15> PEG_HTX_C_GRX_N1
<15> PEG_GTX_C_HRX_P1
<15> PEG_GTX_C_HRX_N1

WLAN

<30> PCIE_PTX_C_DRX_P2
<30> PCIE_PTX_C_DRX_N2
<30> PCIE_PRX_DTX_P2
<30> PCIE_PRX_DTX_N2

PCIE LAN

<28> PCIE_PTX_C_DRX_P3
<28> PCIE_PTX_C_DRX_N3
<28> PCIE_PRX_DTX_P3
<28> PCIE_PRX_DTX_N3

VGA@
VGA@

CC17 1
CC21 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

PEG_HTX_GRX_P0
PEG_HTX_GRX_N0
PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_N0

C24
B24
G20
J20

VGA@
VGA@

CC18 1
CC19 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

PEG_HTX_GRX_P1
PEG_HTX_GRX_N1
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_N1

A25
C25
D20
F20

C1135 1
C1000 1

2 .1U_0402_16V7K
2 .1U_0402_16V7K

C1133 1
C1134 1

C

<31>

2 .1U_0402_16V7K

2 .1U_0402_16V7K

VGA_CLKREQ#

<30> WLAN_CLKREQ#
<28> LAN_CLKREQ#

dGPU
WLAN
LAN
1
R991

@

PCIE_PTX_DRX_P2
PCIE_PTX_DRX_N2
PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N2

PCIE_PTX_DRX_P3 A27
PCIE_PTX_DRX_N3 C27
PCIE_PRX_DTX_P3 G24
PCIE_PRX_DTX_N3 J24
VGA_CLKREQ#
PCIE_CLKREQ_1#
WLAN_CLKREQ#
LAN_CLKREQ#

AM10

AM12
AK14
AM14

CLK_DIFF_P_4
CLK_DIFF_N_4

A21
C21
C19
B20
C18
B18
C17
A17
C16
B16

<15> CLK_PEG_VGA
<15> CLK_PEG_VGA#
<30>
<30>
<28>
<28>

CLK_PCIE_WLAN
CLK_PCIE_WLAN#
CLK_PCIE_LAN
CLK_PCIE_LAN#

2 CLK_DIFF_P_4
402_0402_1%
CLK_DIFF_N_4

B26
C26
D22
F22

2
R975 1 PCIE_RCOMPP
402_0402_1% PCIE_RCOMPN

D26
F26
V14
Y13
Y12
V13
V12

PCIE_TXP0
PCIE_TXN0
PCIE_RXP0
PCIE_RXN0

3.3V

PCIE_TXP1
PCIE_TXN1

PCIE_RXP1
PCIE_RXN1
PCIE_TXP2
PCIE_TXN2
PCIE_RXP2
PCIE_RXN2

SATA_LEDN
SATA_GP0
SATA_GP1
1.8V SATA_GP2
SATA_GP3

SATA

PCIe

1.05V

PCIE_TXP3
PCIE_TXN3
PCIE_RXP3
PCIE_RXN3

SATA_OBSP
SATA_OBSN
FST_SPI_CLK

PCIE_CLKREQ0B
PCIE_CLKREQ1B

PCIE_CLKREQ2B
PCIE_CLKREQ3B
CLK_DIFF_P_0
CLK_DIFF_N_0
CLK_DIFF_P_1
CLK_DIFF_N_1
CLK_DIFF_P_2
CLK_DIFF_N_2
CLK_DIFF_P_3
CLK_DIFF_N_3
CLK_DIFF_P_4
CLK_DIFF_N_4

FST_SPI_CS0_B
FST_SPI_CS1_B
FST_SPI_CS2_B

1.8V

FST_SPI_D0
FST_SPI_D1
FST_SPI_D2
FST_SPI_D3

FAST SPI

1.8V
1.05V

MF_HDA_RSTB

MF_HDA_SDI1
MF_HDA_CLK
1.8V/ MF_HDA_SDI0
MF_HDA_SYNC
1.5V
MF_HDA_SDO
MF_HDA_DOCKENB
MF_HDA_DOCKRSTB

PCIE_OBSP
PCIE_OBSN

AUDIO

SPI1_CLK
SPI1_CS0_B
SPI1_CS1_B
SPI1_MISO
SPI1_MOSI

SATA_TXP0
SATA_TXN0
SATA_RXP0
SATA_RXN0
SATA_TXP1
SATA_TXN1
SATA_RXP1
SATA_RXN1

SPI

1.8V

1.8V

1.8V

SPKR

GP_SSP_2_CLK
GP_SSP_2_FS
GP_SSP_2_TXD
GP_SSP_2_RXD

C31
B30
N28
M28
C29
A29
J28
K28
AH3
AH2
AG3
AG1
AF3
N30
M30

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
SATA_PRX_DTX_P0
SATA_PRX_DTX_N0
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
SATA_PRX_DTX_P1
SATA_PRX_DTX_N1
R639 1
DEVSLP0_SOC
DEVSLP1_SOC

<32>
<32>
<32>
<32>
<32>
<32>
<32>
<32>

@

HDD
ODD

2 10K_0402_5%

+1.8VS

Checklist P.24 requset

TS_INT_R#

<31>

T188 @
T192 @

SATA_RCOMPP 2
R972 1
SATA_RCOMPN 402_0402_1%

W3 SOC_SPI_CLK
V4 SOC_SPI_CS0#
V6 SOC_SPI_CS1#
V7

C

T193@

+1.8VALW
RP40

V2
V3
U1
U3

SOC_SPI_MOSI
SOC_SPI_MISO
SOC_SPI_WP#
SOC_SPI_HOLD#

AF13
AD6
AD9
AD7
AF12
AF14
AB9
AB7

HDA_RST#

H4

SOC_SPKR

HDA_BIT_CLK
HDA_SDIN0
HDA_SYNC
HDA_SDOUT

1
2
3
4

VGA_CLKREQ#
PCIE_CLKREQ_1#
WLAN_CLKREQ#
LAN_CLKREQ#

8
7
6
5
10K_0804_8P4R_5%

T189

@
RP55
HDA_SDIN0

T191

<36>

HDA_SYNC
HDA_SDOUT
HDA_BIT_CLK
HDA_RST#

@

SOC_SPKR

<36>

1
2
3
4

8
7
6
5

HDA_SYNC_AUDIO
<36>
HDA_SDOUT_AUDIO <36>
HDA_BITCLK_AUDIO <36>
HDA_RST_AUDIO# <36>

75_0804_8P4R_1%

AK9
AK10
AK12
AK13

4 OF 13
BSW-MCP-EDS_FCBGA1170

B

B

Checklist suggest PU 100K
Follow VC(V0.1)
+BIOS_SPI
+BIOS_SPI
R999 1

2 3.3K_0402_5%

SPI_CS0#

R1001 1

2 20K_0402_5%

SPI_WP#

R1000 1

2 20K_0402_5%

SPI_HOLD#

+1.8VALW
R998 1

C1013

2 0_0402_5%

@
2

1 .1U_0402_16V7K

From CPU
SOC_SPI_CS0# 1 EMC@ 2 SPI_CS0#
R2581
33_0402_5%
SOC_SPI_WP# 1 EMC@ 2 SPI_WP#
R2580
10_0402_5%
RP37
SOC_SPI_HOLD# 4
SOC_SPI_MOSI 3
SOC_SPI_MISO 2
1
SOC_SPI_CLK
A

5
6
7
8

SPI_HOLD#
SPI_MOSI
SPI_MISO
SPI_CLK

SPI ROMU56( 8MByte ) 1.8V
1
2
3
4

SPI_CS0#
SPI_MISO
SPI_WP#

CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)

8
7
6
5

+BIOS_SPI

SPI_HOLD#
SPI_CLK
SPI_MOSI

W25Q64DWSSIG_SO8

U56 change to SA00006ZV10 for Quad-I/O
A

10_0804_8P4R_5%
EMC@

Reserve for EMI(Near SPI ROM)
SPI_CLK

1
2
@EMC@ R1002
33_0402_5%

2
1
@EMC@ C1014
10P_0402_50V8J

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/19

2015/03/18

Deciphered Date

Title

VLV-M SOC SATA/PCI-E/HDA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
5

4

3

2

Wednesday, March 04, 2015

Sheet
1

7

of

55

Rev
1.0


5

4

3

USOC1E

V0.2 modify

3

2

GND

4

GND

2

1

3

1
2

C1005
15P_0402_50V8J

D

1

ICLK_ICOMP
ICLK_RCOMP

C1023
15P_0402_50V8J

J26
N26
P20
N20
P26
K26
M26

AH45
A9
C9
B8
B7
B5
B4

19.2MHZ_10PF_7M19200019

Change P/N to SJ10000N700
19.2MHz_12pF

R984 1
R985 1

2 2.49K_0402_1% ICLK_ICOMP
2 49.9_0402_1% ICLK_RCOMP
SOC_GPIO_DFX5
SOC_GPIO_DFX6

49.9_1% for RCOMP
2.49K_1% for ICOMP

+1.8VALW

<34>

R959
0_0402_5%

2
EC_SCI# 1
@

EC_SCI#

<34>

EC_SMI#

V0.2 modify
+1.8VALW

1

C

R1016 1
R1022 1

R995
100_0402_1%

2 20K_0402_5% SOC_GPIO_DFX5
2 20K_0402_5% SOC_GPIO_DFX6

1.05V

RSVD13
RSVD17

ICLKICOMP
ICLKRCOMP
RSVD18
RSVD14
RSVD16
RSVD1
MF_PLT_CLK0
MF_PLT_CLK1
MF_PLT_CLK2
MF_PLT_CLK3
MF_PLT_CLK4
MF_PLT_CLK5
GPIO_DFX0
GPIO_DFX1
GPIO_DFX2
GPIO_DFX3
GPIO_DFX4
GPIO_DFX5
GPIO_DFX6
GPIO_DFX7
GPIO_DFX8

RSVD3
RSVD2
RSVD9
RSVD8
RESERVED

iCLK

1.8V

RSVD5
RSVD7
RSVD4
RSVD6
RSVD11
RSVD10
RSVD12
RSVD15
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA

1.8V

GPIO_SUS0
GPIO_SUS1
GPIO_SUS2
GPIO_SUS3
1.8V
GPIO_SUS4
GPIO_SUS5
GPIO_SUS6
GPIO_SUS7
SEC_GPIO_SUS9
SEC_GPIO_SUS8
SEC_GPIO_SUS10
SEC_GPIO_SUS11

GPIO0_RCOMP
GPIO_ALERT

I2C2_SCL
I2C2_SDA

I2C

1.8V

I2C3_SCL
I2C3_SDA
I2C4_SCL
I2C4_SDA
I2C5_SCL
I2C5_SDA
I2C6_SCL
I2C6_SDA
I2C_NFC_SCL
I2C_NFC_SDA

MF_SMB_CLK
MF_SMB_DATA
MF_SMB_ALERTB

SMBUS

1.8V

C11

B10
F12
F10
D12
E8
C7
D6
D

J12
F7
J14
L13
AK6
AH7
AF6
AH6
AF9
AF7

SOC_I2C2_CLK
SOC_I2C2_DATA

AE4
AD2
AC1
AD3
AB2
AC3

SOC_I2C5_CLK
SOC_I2C5_DATA

AA1
AB3
AA3
Y2

I2C_NFC_SCL
I2C_NFC_SDA

T213@
T214@

AM6
AM7
AM9

PCU_SMB_CLK
PCU_SMB_DATA
PCU_SMB_ALERT#

R1155 2
R1180 2
R1181 2

+1.8VALW
@
@
@

1 1K_0402_5%
1 1K_0402_5%
1 1K_0402_5%

C

V0.2 modify

5 OF 13
BSW-MCP-EDS_FCBGA1170

2

@
@

AD51
AD52
AH50
AH48
SOC_GPIO_SUS4 AH51
SOC_GPIO_SUS5 AH52
SOC_GPIO_SUS6 AG51
AG53
EC_SMI#
AF52
SOC_GPIO_SUS9
AF51
SOC_GPIO_SUS8

AE51
AC51
GPIO_RCOMP AH40
Y3
DDI0_ENABLE
DDI1_ENABLE
SOC_GPIO_SUS2

V1.0 modify

R1175
4.7K_0402_5%
1
2 DDI0_ENABLE
1
2 DDI1_ENABLE
R1176
4.7K_0402_5%

AM40
AM41
AM44
AM45
AM47
AK48
AM48
AK41
AK42

OSCIN

OSCOUT

PLTFM CLK's

Y7

GPIO_DFX

P24
XTAL_19.2M_IN
XTAL_19.2M_OUT M22

1

1

2 XTAL_19.2M_OUT
200K_0402_5%

GPIO_SUS

XTAL_19.2M_IN1
R1004

2

CHV_MCP_EDS

SOC_GPIO_SUS4:
BIOS Boot Selection

0 = LPC
1 = SPI
(internal PU)

For Touch Screen
SOC_GPIO_SUS8:
ICLK, USB 2.0,
DDI SFR supply
select :
0 = Supply is 1.25V
1 = Supply is 1.35V

5

5

G

SOC_I2C2_CLK_L
SOC_I2C2_DATA_L

D

1R2566
1R2565

I2C2_SCL_PNL

<24>

I2C2_SDA_PNL

<24>

2

S

2.2K_0402_5% 2 TSI@
2.2K_0402_5% 2 TSI@

3
4 I2C2_SCL_PNL
TSI@ Q2511A
DMN63D8LDW-7_SOT363-6
SB000013K00
1
SOC_I2C2_DATA_L 6
I2C2_SDA_PNL
TSI@ Q2511B
DMN63D8LDW-7_SOT363-6
SB000013K00
SOC_I2C2_CLK_L

D

4
3
TSI@Q2512A
PJT138KA 2N SOT363-6

SB000016K00
1
6
SOC_I2C2_DATA
TSI@Q2512B
PJT138KA 2N SOT363-6
SB000016K00
SOC_I2C2_CLK

+3VALW

V0.2 modify

G

SOC_GPIO_SUS6:
Halt Boot Strap:
1= Normal Operation

S

1
2
R1048
4.7K_0402_5%

SOC_GPIO_SUS8
SOC_GPIO_SUS9

V0.2 modify

+TS_PWR

D

2 10K_0402_5%

2 TSI@
1 I2C2_SCL_PNL
2.2K_0402_5%
R1147
2 TSI@
1 I2C2_SDA_PNL
2.2K_0402_5%
R1150

G

V1.0 modify
@

+1.8VALW
+TS_PWR

G

SOC_GPIO_SUS6

D

SOC_GPIO_SUS4

2 4.7K_0402_1%

2

2 100K_0402_5%

R981 1

(v0.1)

1 R1143 SOC_I2C2_DATA
1 R1144 SOC_I2C2_CLK

@
@

S

R977 1

1K_0402_5% 2
1K_0402_5% 2

S

+1.8VALW

R1040 1

Spec & CRB is reserve. VC pop

+1.8VALW

V0.2 modify

For Touch Pad
B

B

Spec & CRB is reserve. VC pop (v0.1)
SOC_GPIO_SUS5:
Security Flash Descriptors
0 = Override
1 = Normal Operation (Internal PU)

BIOS/EFI Top Swap

+1.8VALW
1K_0402_5% 2
1K_0402_5% 2

@
@

1 R1153 SOC_I2C5_DATA
1 R1152 SOC_I2C5_CLK

+1.8VALW

+3V_PTP

+1.8VALW

SOC_I2C5_CLK_L
SOC_I2C5_DATA_L

2

G

D

S

Issued Date
C151
.1U_0402_16V7K

2014/03/19

2015/03/18

Deciphered Date

Title

4

DDR_SMB_DA

<13,14>

A

DDR<13,14>

V0.2 modify

VLV-M SOC CLK/PMU/SPI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
5

<13,14>

2

2

S

1

DDR_SMB_CK

Compal Electronics, Inc.

Compal Secret Data

Security Classification

3

3
4
Q2507A
DMN63D8LDW-7_SOT363-6
SB000013K00
1
PCU_SMB_DATA_L 6
Q2507B
DMN63D8LDW-7_SOT363-6
SB000013K00
PCU_SMB_CLK_L

S

3

PCU_SMB_CLK 4
Q2502A
PJT138KA 2N SOT363-6
SB000016K00
1
6
PCU_SMB_DATA
Q2502B
PJT138KA 2N SOT363-6
SB000016K00

D

W=20mils

DDR_SMB_CK
DDR_SMB_DA

S

1R2570
1R2569

D

2.2K_0402_5%2
2.2K_0402_5%2

+3VS

G

V0.2 modify

W=10mil

BAS40-04_SOT23-3

<35>

G

W=20mils

I2C5_SDA_TP

5

PCU_SMB_CLK_L
PCU_SMB_DATA_L

5

1R2562
1R2561

+RTCVCC

2

<35>

2

+1.8VALW

+3VS

D22

I2C5_SCL_TP

V0.2 modify

A

1

D

G

1R2564
1R2563

+3VALW
2.2K_0402_5%2
2.2K_0402_5%2

+CHGRTC

5
G

S

2.2K_0402_5%2
2.2K_0402_5%2

TXE_DBG <34>

SOC_GPIO_SUS2: Top Swap( A16 Override )
0 = Change Boot Loader address
1 = Normal Operation
Reference checklist 0.92 P.37
+RTCBATT

D

2

S

+3VALW

3
4 I2C5_SCL_TP
Q2508A
DMN63D8LDW-7_SOT363-6
SB000013K00

1
SOC_I2C5_DATA_L 6
I2C5_SDA_TP
Q2508B
DMN63D8LDW-7_SOT363-6
SB000013K00
SOC_I2C5_CLK_L

G

3

R1051
0_0402_5%
2
G
Q62
L2N7002LT1G_SOT23-3

3
SOC_I2C5_CLK 4
Q2509A
PJT138KA 2N SOT363-6
SB000016K00
1
6
SOC_I2C5_DATA
Q2509B
PJT138KA 2N SOT363-6
SB000016K00

D

1

2

2
1
2

V1.0 modify

For BOM

S

S

2

I2C5_SDA_TP

D

D

1

I2C5_SCL_TP

S

SOC_GPIO_SUS5
@
R1011
10K_0402_5%

@

1
R1156
1
R1157

G

SOC_GPIO_SUS2

2
2.2K_0402_5%
2
2.2K_0402_5%

EC programing :
"High"for Flash BIOS

R978
10K_0402_5%

D

R1006
10K_0402_5%

G

1

5

+3V_PTP

1

+1.8VALW

3

2

Wednesday, March 04, 2015

Sheet
1

8

of

55

Rev
1.0


4

3

USOC1F

1.24V

USB_HSIC_1_STROBE
USB_HSIC_1_DATA
USB_HSIC_RCOMP

RSVD5
RSVD2
RSVD8
RSVD9

UART1_TXD
UART1_RXD
UART1_CTS_B
UART1_RTS_B

1.8V

RSVD12
RSVD13

UART2_TXD
UART2_RXD
UART2_CTS_B
UART2_RTS_B

P16
P14
B46
B47
A48

USB20_P3
USB20_N3

<24>
<24>

Touch screen

USB20_P4
USB20_N4

<31>
<31>

USB2.0 Hub
USB_OC1#

USB_OC0#

USB2_OBSP
USB_VBUSSNS
USB2_RCOMP 2
R988 1
113_0402_1%

1

M36
N36

5

2
R1032
0_0402_5%

RP39

Y6
Y7
V9
V10

PMC_CORE_PWROK

10K_0804_8P4R_5%
2

1K_0402_5%
2
R485
100K_0402_5%
@EMC@
2 0.047U_0402_25V7K
C1007 1

DDR_CORE_PWROK

EMC@
2 .1U_0402_16V7K
C1158 1

PMC_PLTRST#

@EMC@
2 22P_0402_50V8J
C1006 1

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

2 R1014 LPC_CLK_0
2 R1017 LPC_CLK_1

@
@

P2
R3
T3
P3
M3
M2
N3
N1

2 R1013 LPC_RCOMP
SOC_SERIRQ

100_0402_1%1

T4
T2

GPU_EVENT#
GC6_FB_EN_R
DGPU_PWR_EN2

DGPU_PWR_EN2

<38>
1

R990 1

EC_RSMRST#

@
R1015
49.9_0402_1%

V0.2 modify

2

2

15P_0402_50V8J

+1.8VALW

R1023
20K_0402_1%
1
2

C1010
<15,34>

15P_0402_50V8J

H_PROCHOT#

RSVD6
RSVD7
RSVD4
RSVD3

RSVD1
RSVD2
PROCHOT_B 1.8V

Internal PD 2K
@EMC@
C1002
10P_0402_50V8J

Y8 change P/N to SJ10000LV00 for ESR<50k ohm

2

SVID0_CLK
SVID0_DATA
SVID0_ALERT_B

CORE_VCC0_SENSE
CORE_VSS0_SENSE
CORE_VCC1_SENSE
CORE_VSS1_SENSE
DDI_VGG_SENSE
UNCORE_VSS_SENSE2
UNCORE_VSS_SENSE1

Reserved

1

1

V0.2 modify

P28
P30
AF50
AF48
AF44
AF45
AD50

1.8V

D18
G16
F18
J16
G18

1
C1008

RTC_RST#
PMC_CORE_PWROK
EC_RSMRST#
RTC_TEST#

2
.1U_0402_16V7K

EC_RSMRST#
2
R1052

AE3
D14
C15
C12
B14
AF2
F14
C14
C13
A13
B12
N16
M16
P18

@

1

R1042 1

@

2 0_0402_5%

AG32

AJ32
AD29
AF27
AD24
AD22
AC27

U71

<34>

1
2
3

SOC_SERIRQ

VCCB
EO
B4

T195@

PBTN_OUT#

<34>

R1034
10K_0402_5%
@

VR_SVID_CLK <47,48>
VR_SVID_DATA <47,48>
VR_SVID_ALERT# <47,48>
2
2
2
2

+1.8VALW
6
5
4

EC_SERIRQ

<34>
+1.8VALW

@
@
@
@

<34>

V1.0 modify

@ C1017
.1U_0402_16V7K

1
2

G2129TL1U_SC70-6
EC_SLP_S4#

R1073 1
R1074 1
R1075 1
R1076 1

<34,35>

EC_SLP_S3#_1P8

LPC3V@

VCCA
GND
A4

T207@

EC_SERIRQ

0_0402_5% EC_SLP_S3#

+3VALW_EC

V1.0 modify

<34>

PMC_PCIE_WAKE#
PBTN_OUT#

VCC0_SENSE
VSS0_SENSE
VCC1_SENSE
VSS1_SENSE
VGG_SENSEP
VGG_SENSEN
VNN_SENSE

0_0402_5% EC_SERIRQ

@ C1016 +1.8VALW
.1U_0402_16V7K
1
2

T212@

+3V_SOC

R1038
10K_0402_5%
@

3

1

EC_SLP_S3#

<34>

@
Q83
MESS138W-G_SOT323-3

B

V1.0 modify

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

VCC_SENSE

<47>

For UART
debug

+1.8VALW

VSS_SENSE <47>

VGG_SENSEP <48>
VGG_SENSEN <48>
VNN_SENSE <44>

V1.0 modify

7 OF 13
BSW-MCP-EDS_FCBGA1170

1

R1025 2

PMC_SLP_S3#
AD42
AD41
AD40

C

R1021 2

PMC_SLP_S3#

1
10K_0402_5%

PMC_SUSPWRDNACK

PMC_SUS_STAT#

PMC_SUSCLK
EC_SLP_S4#
PMC_SLP_S3#
PMC_RSTBTN#
PMC_PLTRST#
PMC_BATLOW#
PMC_ACIN
PMC_SLP_S0#

LPC1P8V@
1

SOC_SERIRQ

D

V1.0 modify

32.768KHZ_12.5PF_Q13FC135000040
2
Y8 1
C1009

PWM0
PWM1

M18 ILB_RTC_X1
K18 ILB_RTC_X2
F16 ILB_RTC_EXTPAD

2 100K_0402_5%

@EMC@
2 22P_0402_50V8J
C1155 1

S

1
2
R994
10M_0402_5%

RTC

LPC_HVT_RCOMP
ILB_SERIRQ

H5
H7

ILB_RTC_X1
ILB_RTC_X2
B

3.3V/
1.8V

1

G

LPC-25MHz

MF_LPC_AD0
MF_LPC_AD1
MF_LPC_AD2
MF_LPC_AD3

SRTCRST_B
COREPWROK
RSMRST_B
RTEST_B
RSVD_VSS

SUSPWRDNACK
SUS_STAT_B
PMU_SUSCLK
PMU_SLP_S4_B
PMU_SLP_S3_B
PMU_RESETBUTTON_B
PMU_PLTRST_B
1.8V PMU_BATLOW_B
PMU_AC_PRESENT
PMU_SLP_S0IX_B
PMU_SLP_LAN_B
PMU_WAKE_B
PMU_PWRBTN_B
PMU_WAKE_LAN_B

MF_LPC_CLKOUT0
MF_LPC_CLKOUT1
LPC_CLKRUNB
LPC_FRAMEB

R2025

2

<34,35>
<34,35>
<34,35>
<34,35>

0_0402_5%1
0_0402_5%1

1

PMC_RSTBTN#

Sch. chelist PU 1k

1

LPC_CLK_EC
LPC_CLK_TPM
LPC_CLKRUN#
LPC_FRAME#

CX_PRDY_B
CX_PREQ_B
RSVD5

LPC

<34>
<35>
<35>
<34,35>

3.3V

AD45
SOC_H_PRDY#
SOC_H_PREQ_BUF#AF41
M13

@T208

V0.2 modify

BRTCX1_PAD
BRTCX2_PAD
BVCCRTC_EXTPAD

1.8V

8
7

6
5

USB2_OBSP

PMU

2 51_0402_5% SOC_H_TCK
2 51_0402_5% SOC_H_TRST#

TCK
TDI
TDO
TMS
TRST_B

PWM

R989 1
R1026 1

AF42
AD47
AF40
AD48
AB48

SOC_H_TCK
SOC_H_TDI
SOC_H_TDO

SOC_H_TMS
SOC_H_TRST#

51_0804_8P4R_5%

1
2
3
4

PMC_PCIE_WAKE#
PMC_BATLOW#
USB_OC0#
USB_OC1#

R2047
@
10K_0402_1%

CHV_MCP_EDS

USOC1G

SVID

SOC_H_TDI
SOC_H_TDO
SOC_H_TMS
SOC_H_PREQ_BUF#

JTAG/ITP

5
6
7
8

2

P

2

3

R2057
40.2K_0402_1%
@

<33>
<33>

+1.8VALW
4
3
2
1

<15,28,30,34,35>

NL17SZ07DFT2G_SC70-5
SA00004BV00
+1.8VALW

BSW-MCP-EDS_FCBGA1170

RP52

3.3V
PLT_RST_BUF#

D

K38 Change 45.3_1% for Intel request
M38
N38 HSIC_RCOMP
1
2
R1012 45.3_0402_1%
AD10 DBG_UART_TXD
AD12 DBG_UART_RXD
AD13 DBG_UART_CTS#
T209@
AD14 DBG_UART_RTS#
T211@

Voltage sense

C

A

+5VALW

6 OF 13

Refer PDG 0.92 Page 268

4

Y

2

PMC_PLTRST#

Camera

R982
4.7K_0402_5%

U53

NC

G

<24>
<24>

USB_OC1#
USB_OC0#

1

1

USB20_P2
USB20_N2

1

2

B40
C40

1.8V

1

USB2.0

USB_HSIC_0_STROBE
USB_HSIC_0_DATA

RSVD4
RSVD1
RSVD7
RSVD6

RSVD11
RSVD10

N34
P34

V1.0 modify

USB_OC1_B
USB_OC0_B

RSVD3
USB_VBUSSNS
USB_RCOMP

USB3_OBSP
USB3_OBSN

C38
B38
G36
J36

GC6_FB_EN_R

USB_DP4
USB_DN4

R2024 @
1K_0402_5%

2

1

D34
F34

1.8V

C45
A45

USB3.0 Port

<33>
<33>

1

A

NL17SZ07DFT2G_SC70-5
SA00004BV00

4

G

GC6_FB_EN

Y

2

3

<15>

GC6_FB_EN

2

P

5

GC6@
U2515
1
NC

USB3_TXP3
USB3_TXN3
USB3_RXP3
USB3_RXN3

C37
A37
F36

D36
M34
M32

GC6@
R1009
10K_0402_5%

1.05V

C41
A41

USB3.0 Port

USB20_P1
USB20_N1

2

2
R987 1 USB3_RCOMPP
402_0402_1% USB3_RCOMPN

+1.8VALW
+3V_SOC

USB3_TXP2
USB3_TXN2
USB3_RXP2

USB3_RXN2

C35
A35
G34
J34

2

GPU_EVENT#

GPU_EVENT#

USB_DP3
USB_DN3

C43
B44

PLT_RST# Buffer

+3VS

@
T190
USB20_P0 <33>
USB20_N0 <33>

2

<15>

USB_DP2
USB_DN2

USB3.0

1

@
R1151
10K_0402_5%

TO DGPU

USB3_TXP1
USB3_TXN1
USB3_RXP1
USB3_RXN1

C34
B34
G32
J32

+1.8VALW

D

USB_DP1

USB_DN1

B48 USB_OTG_ID
C42
B42

1

A33
C33
F30
D30

<33> PCH_USB3_TX1_P
<33> PCH_USB3_TX1_N
<33> PCH_USB3_RX1_P
<33> PCH_USB3_RX1_N

USB3 Port 1

USB3_TXP0
USB3_TXN0
USB3_RXP0
USB3_RXN0

UART

USB3 Port 0

+1.8VALW

USB_OTG_ID
USB_DP0
USB_DN0

RESERVED

<33> PCH_USB3_TX0_P
<33> PCH_USB3_TX0_N
<33> PCH_USB3_RX0_P
<33> PCH_USB3_RX0_N

1

2

B32
C32
F28
D28

2

CHV_MCP_EDS

HSIC

5

+SOC_VCC

DBG_UART_TXD R1189 1
DBG_UART_RXD R1188 1

2 1K_0402_5%
2 1K_0402_5%
+3VS_WLAN

UART_TXD_NGFF R1183 2
UART_RXD_NGFFR1160 2

For BOM

@
@

1 2.2K_0402_5%
1 2.2K_0402_5%
+3VS_WLAN

+RTCVCC

ESD request 0926

3.3V

PMC_CORE_PWROK 2

PMC_CORE_PWROK

A

CLR_CMOS#

@

V1.0 modify

@

CLR_CMOS#

1.35V
DDR_CORE_PWROK

JCMOS1
0_0603_5%

DBG_UART_RXD

4

<5>
+1.05VALW

NL17SZ07DFT2G_SC70-5
SA00004BV00

<34>

VNN_SENSE

Clear CMOS
Close to RAM door

R983 2

1
2.2K_0402_5%
D40
RB751V-40_SOD323-2
2
1

PMC_ACIN

V0.2 modify

R1031 1

2 100_0402_1%

V0.2 modify

+1.8VALW
<34,41>

Issued Date

2014/03/19

4

VREF2

SCL1

SCL2

SDA1

SDA2

7
6
5

UART_TXD_NGFF

<30>

UART_RXD_NGFF

<30>

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
ACIN

VREF1

G3401A91G ADFN3X2 8P
SA00006YA00
2 0_0402_5%
R2583 1
@
2 0_0402_5%
R2584 1
@

2015/03/18

Deciphered Date

Title

VLV-M SOC USB/LPC/SMBus

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
5

8
EN
3

2

J9
0_0603_5%

1
Y

A

4

DBG_UART_TXD

1

2
R1088
1
R1089

1

RTC_RST#

1
@
0_0402_5%
2
@
0_0402_5%

2

RTC_TEST#

U55

NC

3

<34>

1

2 100_0402_1%
2 100_0402_1%

@
U2509

GND

5

C1012
1U_0402_6.3V6K

2
VGG_SENSEP R1019 1
VGG_SENSEN R1020 1

1
@
R2576
200K_0402_5%

1

2

+SOC_VGG
R993
10K_0402_5%

2

1

+3VALW

1
20K_0402_1%

2

+3V_UART_LS

+1.35V_SOC

P

1 R997

2

2 100_0402_1%
2 100_0402_1%

G

2

RTC_RST#

R1077 1
R1078 1

+1.8VALW

R996

20K_0402_1%
2
1

RTC_TEST#

C1011
1U_0402_6.3V6K

VCC_SENSE
VSS_SENSE

3

2

Wednesday, March 04, 2015

Sheet
1

9

of

55

Rev
1.0

5

4

3

2

1

D

D

USOC1H

CHV_MCP_EDS

3.5A (can merge with V1P05A)

+SOC_VCC

+1.15VALW

700mA

CORE_V1P15_S0ix Back side : 1uF *4
Package edge : 1uF *2

C1028
C1029
C1030
C1031
C1032
C1033

1
1
1
1
1
1

2
2
2
2
2
2

1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K

AD16
AD18

AD19
AF16
AF18
AF19
AF21
AF22
AJ19
AG16
AG18
AG19
AG21
AG22
AG24
AJ21
AJ22
AJ24
AK24
AK30
AK35
AK36
AM29
AK33
AJ35

B

DDI_V1P15_S0ix Back side : 1uF *1
Package edge : 1uF *2

C1034

C1035

1
1

2 1U_0402_6.3V6K
2 1U_0402_6.3V6K

AM19
AK21

DDI_VGG_S0IX1
DDI_VGG_S0IX2
DDI_VGG_S0IX3
DDI_VGG_S0IX4
DDI_VGG_S0IX5
DDI_VGG_S0IX6
DDI_VGG_S0IX7
DDI_VGG_S0IX8
DDI_VGG_S0IX15
DDI_VGG_S0IX9
DDI_VGG_S0IX10
DDI_VGG_S0IX11
DDI_VGG_S0IX12
DDI_VGG_S0IX13
DDI_VGG_S0IX14
DDI_VGG_S0IX16
DDI_VGG_S0IX17
DDI_VGG_S0IX18
DDI_VGG_S0IX19

iCLK

11A

DDR

+SOC_VGG

RSVD1
UNCORE_V1P15_S0IX6
UNCORE_V1P15_S0IX1
UNCORE_V1P15_S0IX2
UNCORE_V1P15_S0IX3
UNCORE_V1P15_S0IX4
UNCORE_V1P15_S0IX5
UNCORE_V1P15_S0IX7
UNCORE_V1P15_S0IX8
UNCORE_V1P15_S0IX9
UNCORE_V1P15_S0IX10

CORE_V1P15_S0IX1
CORE_V1P15_S0IX2
CORE_V1P15_S0IX3
CORE_V1P15_S0IX4

ICLK_GND_OFF2
ICLK_GND_OFF1
DDR_V1P05A_G31
DDR_V1P05A_G34

DDR_V1P05A_G32
DDR_V1P05A_G35
DDR_V1P05A_G36
DDR_V1P05A_G33

PCIe

C

CORE_VCC1_S0IX2
CORE_VCC1_S0IX4
CORE_VCC1_S0IX5
CORE_VCC1_S0IX6
CORE_VCC1_S0IX11
CORE_VCC1_S0IX12
CORE_VCC1_S0IX13
CORE_VCC1_S0IX1

PCIE_V1P05A_G31
PCIE_V1P05A_G32

SATA

AF30
AG27
AG29
AG30
AJ27
AJ29
AJ30

AF29

UNCORE_VNN_S41
UNCORE_VNN_S42
UNCORE_VNN_S43
UNCORE_VNN_S44
UNCORE_VNN_S45
UNCORE_VNN_S46
UNCORE_VNN_S47
UNCORE_VNN_S48
UNCORE_VNN_S49
UNCORE_VNN_S410
UNCORE_VNN_S411
UNCORE_VNN_S412
UNCORE_VNN_S413
UNCORE_VNN_S414

CORE_VCC1_S0IX3
CORE_VCC1_S0IX7
CORE_VCC1_S0IX8
CORE_VCC1_S0IX9
CORE_VCC1_S0IX10
CORE_VCC1_S0IX14
CORE_VCC1_S0IX15
CORE_VCC1_S0IX16

SATA_V1P05A_G32
SATA_V1P05A_G31

USB

AF36
AG33
AG35
AG36
AG38
AJ33
AJ36
AJ38

USB3_V1P05A_G32
USB3_V1P05A_G31
USBSSIC_V1P05A_G3

FUSE_V1P15_S0IX2
FUSE_V1P15_S0IX1

FUSE

6400mA

DDI_V1P15_S0IX2
DDI_V1P15_S0IX1

FUSE3_V1P05A_G5
FUSE_V1P05A_G3

AA18
AA19
AA21

AA22
AA24
AA25
AC18
AC19
AC21
AC22
AC24
AC25
AD25
AD27

+1.05VALW

V0.2 modify

+1.05VALW

AA30
V33
AA32
AA33
AA35
AA36
AC32
Y30
Y32
Y33
Y35

1900mA

Confirmd with Intel , these pin use +1.05V power
C

1
1
1
1
1

C1042
C1043
C1044
C1050
C1049
R1178 1

V19
V18

+1.05VALW_ICLK_GND_OFF

AM21
AM33
AM22
AN22
AN32
AM32

C1059
@ C1109

2
2
2
2
2
@

1
1

1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2 0_0805_5%

UNCORE_V1P15_S0ix Back side : 1uF *3
Package edge : 1uF *2

+1.05VALW

2 1U_0402_6.3V6K
2 1U_0402_6.3V6K

ICLK_GND_OFF - Back side : 1uF *1
+1.05VALW

C1080
C1054
C1053

1
1
1

2 22U_0603_6.3V6M
2 22U_0603_6.3V6M
2 1U_0402_6.3V6K

V22
V24

C1055

1

2 1U_0402_6.3V6K

PCIE_V1P05A_G3 - Back side : 1uF *1

U24
U22

C1056

1

2 1U_0402_6.3V6K

SATA_V1P05A_G3

- Back side : 1uF *1

USB3_V1P05A_G3

- Back side : 1uF *1

C1057

1

2 1U_0402_6.3V6K

V27
U27
V29

C1089
C1090

1
1

2 1U_0402_6.3V6K
2 1U_0402_6.3V6K

N18
U19

C1103

1

2 1U_0402_6.3V6K

8 OF 13

C1104
C1105

1
1

1900mA
DDR_V1P05A_G3 - Back side : 1uF *1
Package edge : 22uF *2

USBSSIC_V1P05A_G3 - Back side : 1uF *1
Package edge : 1uF *1

2 1U_0402_6.3V6K
2 1U_0402_6.3V6K

BSW-MCP-EDS_FCBGA1170

FUSE_V1P05A_G5

- Package edge : 1uF *1

FUSE_V1P05A_G3

- Back side : 1uF *2

B

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/19

2015/03/18

Deciphered Date

Title

VLV-M SOC Power

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
5

4

3

2

Wednesday, March 04, 2015

Sheet
1

10

of

55

Rev

1.0


5

4

3

2

1

(pin_AN27)DDR_VDDQ_G_S4 Back side : 1uF *1
Package edge : 22uF *1

+1.35V_SOC

+1.24VALW_ICLK
@

2 0_0805_5%
1

@ C1107
1U_0402_6.3V6K

+1.35V_DDRSFR_VDDQ
1
1

C1075
C1051

2 22U_0603_6.3V6M
2 1U_0402_6.3V6K

+1.24VALW

+1.35V_SOC
2 0_0805_5%
1

@ C1108
1U_0402_6.3V6K

+1.35V

AN27
AM25

2 22U_0603_6.3V6M
2 1U_0402_6.3V6K

(pin_AM25)DDRSFR_VDDQ_G_S4 Back side : 1uF *1
Package edge : 22uF *1

@EMC@ L62
2
1

HCB2012KF-121T50_2P
@EMC@ L63
2
1
HCB2012KF-121T50_2P
JP3 JP@

1900mA

JUMP_43X118
2
2
2
2

22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M

2

2

+VDD_SD3

550mA
C1091
C1092
C1093

C1094
C1095

GPIO_V1P8A_G3 pin_Y18 - Back side*1
other pin - Package edge*2

1
1
1
1
1

2
2
2
2
2

1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K

USBHSIC_V1P2A_G3
USB_VDDQ_G32
USB_VDDQ_G33
USB_VDDQ_G31
USBSSIC_V1P2A_G3
USB_V1P8A_G3

USB_V3P3A_G32
USB_V3P3A_G31

SDIO_V3P3A_V1P8A_G31
SDIO_V3P3A_V1P8A_G32
SDIO_V3P3A_V1P8A_G33
UNCORE_V1P8A_G32
UNCORE_V1P8A_G31
GPIO_V1P8A_G35
GPIO_V1P8A_G31
GPIO_V1P8A_G33
GPIO_V1P8A_G32
GPIO_V1P8A_G34

RTC_V3P3RTC_G52
RTC_V3P3RTC_G51
RTC_V3P3A_G51
RTC_V3P3A_G52
FUSE_V1P8A_G3
FUSE1_V1P05A_G4
FUSE0_V1P05A_G3
RSVD_VSS
RSVD1
RSVD2

Y27
Y25

+1.24VALW_ICLK

2

V1.0 modify
@ C1110
1U_0402_6.3V6K

C1047
C1048

1
1

2 1U_0402_6.3V6K
2 1U_0402_6.3V6K

CORE_VSFR_G3 - Back side : 1uF *2

C1046

1

2 1U_0402_6.3V6K

CORE_VSFR_G3 - Back side : 1uF *1

C1087

@
1

2 1U_0402_6.3V6K

USBHSIC_V1P24A_G3 - Back side : 1uF *1

C1061
C1062

1
1

2 1U_0402_6.3V6K
2 1U_0402_6.3V6K

USB_VDDQ_G3 - pin_U35,V35 - Back side : 1uF *2

C1088

@
1

2 1U_0402_6.3V6K

USBSSIC_1P24A_G3 -

DDI_VDDQ_G3 - Back side : 1uF *1
ICLK_VSFR_G3 - Back side : 1uF *1

2 1U_0402_6.3V6K
2 1U_0402_6.3V6K

MIPI_V1P24A_G3 - Back side : 1uF *1
Package edge : 1uF *1

+1.24VALW_USBVDDQ

+1.24VALW

R1209 1
P38
V30
AC30

C1081
1U_0402_6.3V6K
AF35
AD35
AD38
AC36

V1.0 modify

M41
U35
V35
H44
P41

+1.24V_SOC
+1.24VALW_USBVDDQ

1

1

2

2

@

2 0_0805_5%

V1.0 modify
@ C1111
1U_0402_6.3V6K

USB_VDDQ_G3 pin_H44 - Back side : 1uF *1

Package edge : 1uF *1

AA29
+1.8VALW

C23
B22

+3V_SOC

C5
B6

D4
E3

+RTCVCC
+3V_SOC
1

U16

+1.8VALW

H10
G10
A3
K20
M20

1

+1.05VALW
1

2
9 OF 13
BSW-MCP-EDS_FCBGA1170

2

2
C1102

1U_0402_6.3V6K

+1.8VALW

CORE_VSFR_G34
CORE_VSFR_G32
CORE_VSFR_G33
CORE_VSFR_G31

+1.24V_SOC

2 1U_0402_6.3V6K

C1101
1U_0402_6.3V6K

+VDD_LPC
+VDD_AUDIO

CORE_VSFR_G35
CORE_VSFR_G36
PCIE_V1P05A_G31

C1086

1
@
1
@
1

C1058
C1085

T40
P40

C1106
1U_0402_6.3V6K

E1
E2
G1
AH4
AF4
Y18
AD33
AK18
AF33
AK19

ICLK_VSFR_G32
ICLK_VSFR_G31

V1.0 modify

1

2

C1100
1U_0402_6.3V6K

@

MIPI_V1P2A_G32
MIPI_V1P2A_G31

V36
Y36

1

2

1

2

1

2

USB_V1P8A_G3 - Back side : 1uF *1
Package edge : 1uF *1

C1082
1U_0402_6.3V6K

DDR_VDDQ_G_S4 Package edge : 22uF *4

1
1
1
1

DDR_VDDQ_G_S416
DDR_VDDQ_G_S419
DDR_VDDQ_G_S426
DDR_VDDQ_G_S427
DDR_VDDQ_G_S428
DDR_VDDQ_G_S429
DDR_VDDQ_G_S425
DDR_VDDQ_G_S424
DDR_VDDQ_G_S423
DDR_VDDQ_G_S422
DDR_VDDQ_G_S417
DDR_VDDQ_G_S421
DDR_VDDQ_G_S420
DDR_VDDQ_G_S430
DDR_VDDQ_G_S431
DDR_VDDQ_G_S414
DDR_VDDQ_G_S415
DDR_VDDQ_G_S413
DDR_VDDQ_G_S410
DDR_VDDQ_G_S418
DDR_VDDQ_G_S412
DDR_VDDQ_G_S411
DDR_VDDQ_G_S49
DDR_VDDQ_G_S48

DDR_VDDQ_G_S47
DDR_VDDQ_G_S46
DDR_VDDQ_G_S45
DDR_VDDQ_G_S44
DDR_VDDQ_G_S43
DDR_VDDQ_G_S41

DDI_VDDQ_G31
DDI_VDDQ_G32

C1083
1U_0402_6.3V6K

C1069
C1071
C1072
C1074

JP3,JP4 short

DDRSFR_VDDQ_G_S4
DDR_VDDQ_G_S42

C1084
1U_0402_6.3V6K

BE1
BE53
BJ2
BJ3

BJ49
BJ5
BH50
BH5
BH49
BH4
BE3
BG51
BG3
BJ51
BJ52
AY10
AY44
AV44
AV10
BE51
AV38
AV16
AU36
AU18
AN36
AN35
AN19
AN18
AM36
AM18

2

@EMC@ L61

2
1
HCB2012KF-121T50_2P

C

1

D

1
1

C1079
C1052

+1.35V_SOC

JUMP_43X118
JP4 JP@

1

+1.35V_DDR_VDDQ

USB

@

RTC

R1177 1

C1060
1U_0402_6.3V6K

CHV_MCP_EDS

USOC1I

DDR

D

+1.24VALW
R1179
0_0805_5%
1
@

550mA

2

FUSE

R1158 1

USB_V3P3A_G3 -

C

Package edge : 1uF *1

RTC_V3P3RTC_G5 - Package edge side : 1uF *1
RTC_V3P3A_G5 - Package edge side : 1uF *1
FUSE_V1P8A_G3 - Back side : 1uF *1
FUSE_V1P05A_G4 - Package edge : 1uF *1

Confirm with VC Team already(V0.1)

V1.0 modify
+1.24VALW

+VDD_SD3

@

2 0_0603_5%

UNCORE_V1P8A_G3 - Back side : 1uF *1

V0.2 modify

+1.8VALW
1

2

2

R1218
1
@

2 0_0603_5%

SDIO_V3P3A_V1P8A_G3 pin_E1,E2 - Back side : 1uF *2

1

2

1

2

@
C1098
1U_0402_6.3V6K

2

+1.8VALW

2 0_0603_5%

+1.24V_SOC

@

R1212
0_0603_5%

1

1

R1210 1

C1099
1U_0402_6.3V6K

B

R1211
1
@

+1.8VS

@

SDIO_V3P3A_V1P8A_G3 pin_G1 - Back side : 1uF *1

148mA

C1096
1U_0402_6.3V6K

+3V_SOC

R1208 1 LPC3V@2 0_0603_5%

C1097
1U_0402_6.3V6K

R1207 1

+VDD_AUDIO

2

LPC1P8V@
2 0_0603_5%

+1.8VALW

+VDD_LPC

R1213
0_0603_5%

B

1

V0.2 modify

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/19

2015/03/18

Deciphered Date

Title

VLV-M SOC Power

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
5

4

3

2

Wednesday, March 04, 2015

Sheet
1

11

of

55

Rev
1.0


5

4

3

2

1

D

D

ball_B52 :
if connect to GND , layout side need use 3mil-core and will cost up ,
so left NC pin_B52 (Intel CRB also left NC)

CHV_MCP_EDS
USOC1J

C

CHV_MCP_EDS
USOC1K

Power-VSS

AN3
AN29
AN25
AN24
AN16
AN14
AN12
AN11
AN1
AM50

AM42
AM4
AM38
AM35
AH44
AM30
AM27
U25
P10
AM16
AD4
AK7
AK50
AK47
AK45
AK44
AK40
AK4
AK38
AK32
AK27
AK25
AM24
AK16
AJ53
AJ51
AJ3
AJ25
AJ16
AJ1

AH9
AH47
AH42
AH41
AH14
AH13
AH12
AH10
AG25
AF47

B

VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS60
VSS84
VSS83

VSS100
VSS99
VSS81
VSS31
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS82
VSS69
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS59
VSS58
VSS57
VSS56
VSS55

VSS54
VSS53
VSS52

VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS30
VSS23
VSS29
VSS28
VSS27
VSS26

VSS25
VSS24
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1

AF38
AF32
AF25
AF10
AE9

AE8
AE6
AE53
AE50
AE48
AE46
AE45
AE43
AE42
AE40
AE14
AE12
AE11
AE1
AD44
AD36
AC29
AD32
AD30
AD21
AC38
AC35
AC33
AC16
AB6
AB50
AB47
AB42
AB4
AB14

AB13
AB12
AB10
AA53
AA38
AA27
AA16
A47
A43
A39
A31
A23
A19
A15
A11

AN21
BG30
BG27
BG24
BG20
BG19
BG18
BG16
BG14
BF42
BF32
BF28
BF27
BF26

BF22
BF12
BE35
BE19
C20
BD53
BG7
BD35
BD27
BD19
BD1
BC44
BC40
BC38
BC28
BC26
BC16
BC14
BC10
BB35
BB27
BB19
BA35
BA30
BA27
BA24
BA19
B36
B28
AY7

AY51
AY47
AY34
AY32
AY30
AY3
AN30
AY45

10 OF 13
BSW-MCP-EDS_FCBGA1170

VSS5
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85

VSS103
VSS84
VSS102
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS60
VSS59
VSS58
VSS56
VSS55

VSS54
VSS53
VSS6
VSS57

CHV_MCP_EDS

CHV_MCP_EDS
USOC1L

Power-VSS

VSS61
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS4
VSS3
VSS2
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39

VSS38
VSS1
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10

VSS9
VSS8
VSS7

11 OF 13
BSW-MCP-EDS_FCBGA1170

AY9
AY28
AY26
AY24
AY22
AY20
AW35
AW27
AW19
AM13
AK29
AK22
AV40
AV35
AV30
AV27
AV24
AV19
AV14
AJ18
AU53
AU51
AU3

AU1
AT9
AT51
AT45
AT36
AT35
AT3
AT27
AT19
AT18
AP9
AP50
AP45
AP4
AN9
AN8
AN6
AN53
AN51
AN5
AN49
AN48
AN46
AN45
AN43
AN42
AN40
AN38

AN33

P32
P27
P22
P19
AF24
N53
N51
N32
N24
N22
M9
K45
M40
M35
M27
AW13
M19
M14
L35
L27
L19
L1
K50
T47
K4
K36
K34
K32
K30
K24

K22
K16
K14
K12
J53
M45
J38
J35
J30
J27
J22
J19
J18
H8
E46
H35
H27
H19
M50
V25

VSS2
VSS99
VSS98
VSS97
VSS96
VSS1
VSS95
VSS94
VSS93

VSS92
VSS91
VSS90
VSS77
VSS87
VSS86
VSS85
VSS3
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS100
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
VSS67
VSS66
VSS88
VSS64
VSS63

VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS40
VSS56
VSS55
VSS54
VSS89
VSS101

C

USOC1M

Power-VSS

Power-VSS

Y24
G30
G28
G26
G22
G14
G12
F5
F35

F32
F27
F24
F19
E51
E35
E19
D42
D40
D38
D32
D27
D24
D16
D10
J42
C47
C39
C36
C30
C3
C28
C22
AW41
BJ7
BJ47
BJ43
BJ39
BJ35
BJ31

BJ27
BJ23
BJ19
BJ15
BJ11
BG5
BG49
BG40
BG38
BG36
BG35
BG34

VSS102
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS39
VSS38
VSS37

VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS65
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS4
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9

VSS8
VSS7
VSS6
VSS5

F1
C1
BH53
BH52
BH2
BH1
BG53
BG1
B52
B2
A6
A5
M24
A7
BF50
BF4
BB50
BB4
BG47
Y9
Y50
Y45
Y40
Y4
Y38

Y29
Y22
Y21
Y19
Y16
Y14
Y10
P4
L41
P36

VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS10
VSS5
VSS4
VSS2
VSS1
VSSA
VSS3
VSS9
VSS8
VSS7
VSS6
VSS11

VSS70
VSS69
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58

VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42

VSS41
VSS40
VSS39
VSS38
VSS37
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS36
VSS29
VSS28
VSS27
VSS26
VSS23
VSS25
VSS24

W1
V44
V42
V41
V38
V32
V21
V16
U9
U8

U6
U53
U5
U49
U48
U46
U45
U43
U42
U40
U38
U33
U32
U30
U29
U21
U18
U36
U14
U12
U11
T9
P42
T14
R1

B

VSS22
VSS19

P35
VSS21 13 OF 13 VSS20
BSW-MCP-EDS_FCBGA1170

12 OF 13
BSW-MCP-EDS_FCBGA1170

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/19

2015/03/18

Deciphered Date

Title

VLV-M SOC GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
5

4

3

2

Wednesday, March 04, 2015

Sheet
1

12

of

55

Rev
1.0

A

B

C

+DDR_A_VREF_DQ

+1.35V

DDR_A_D0
DDR_A_D1
DDR_A_DM0
DDR_A_D2
DDR_A_D5
DDR_A_D13
DDR_A_D12
1

DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D22
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D23
DDR_A_D18

All VREF traces should
have 10 mil trace width

DDR_A_D28
DDR_A_D30
DDR_A_DM3
DDR_A_D26
DDR_A_D24

<5>

DDR_A_CKE0

<5>

DDR_A_BS2
DDR_A_MA12
DDR_A_MA9

2

DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<5>
<5>

DDR_A_CLK0
DDR_A_CLK0#

DDR_A_MA10

<5>

DDR_A_BS0

<5>
<5>

DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13

<5>

DDR_A_CS1#

DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D36
DDR_A_D37

3

DDR_A_DM4

Swap D4->D5,D5->D6,D6->D4

DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D56
DDR_A_D59
DDR_A_DM7
DDR_A_D62
DDR_A_D60

+3VS

2

@
R212
0_0402_5%

2

0_0402_5%

C125
.1U_0402_16V7K

1

1
4

@
R211

1

2

+0.675VS

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101

103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161

163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0

VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33

VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58

DQ59
VSS
SA0
VDDSPD
SA1
VTT
GND1
BOSS1

E

+1.35V

CONN@
JDIMM1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

D

VSS
DQ4
DQ5
VSS
DQS0#
DQS0

VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37

VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62

DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
BOSS2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102

104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162

164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208

LCN_DAN06-K4406-0100
Part Number = SP07000N300
LCN_DAN06-K4406-0100_204P

<Address: SA1:SA0=00 (A0H)>

DIMM_1 STD H:4mm

DDR_A_D7
DDR_A_D3

DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D[0..63]

DDR_A_D6
DDR_A_D4

DDR_A_MA[0..15]
DDR_A_DM[0..7]

DDR_A_D9
DDR_A_D8

<5>
<5>
<5>
<5>
<5>
1

DDR_A_DM1

DDR_A_RST#

<5>

DDR_A_D14
DDR_A_D15
EMC@
2 .1U_0402_16V7K
DDR_A_RST# C1077 1

DDR_A_D16
DDR_A_D19
DDR_A_DM2

ESD request 0211

DDR_A_D20
DDR_A_D21
DDR_A_D27
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D29
DDR_A_D31

Signal voltage level = 0.675 V
PLACE TWO 4.7K RESISTORS CLOSE TO
DIMMS ON DIMM_VREF_CA / DIMM_VREF_DQ
Decoupling caps are needed; one 0.1 µF placed close to VREF pins of each DDR3 SODIMM.
DDR_A_CKE1

<5>

DDR_A_MA15
DDR_A_MA14

+1.35V

DDR_A_MA11
DDR_A_MA7

+DDR_A_VREF_DQ
2

1

2
R1027
4.7K_0402_1%
1
2
R1028
4.7K_0402_1%

DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

1

2

C1076
.1U_0402_16V7K

DDR_A_CLK1 <5>
DDR_A_CLK1# <5>
+1.35V

DDR_A_BS1 <5>
DDR_A_RAS# <5>
DDR_A_CS0#
DDR_A_ODT0

<5>
<5>

DDR_A_ODT1

<5>

+DDR_A_VREF_CA
1
1

2
R1029
4.7K_0402_1%
2

R1030
4.7K_0402_1%

1

2

C1078
.1U_0402_16V7K

+DDR_A_VREF_CA
DDR_A_D52
DDR_A_D53
DDR_A_DM6

Layout Note:
Place near JDIMM1

DDR_A_D54
DDR_A_D55

For EMI request 2/5

DDR_A_D32
DDR_A_D33

V1.0 modify

+1.35V

Follow KV_50

+1.35V

DDR_A_DQS#4
DDR_A_DQS4

+1.35V

DDR_A_D34
DDR_A_D35

EMC@ C120
EMC@ C127
EMC@ C121
EMC@ C126
EMC@ C118
EMC@ C119
EMC@ C148
EMC@ C149
EMC@ C150

DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43

1
1

1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2

.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K

C111
C112

C113
C114

1
1
1
1

2
2
2
2

10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M

C110
C109
C108
C107
C115
C116
C117

1
1
1
1

1
1
1

2
2
2
2
2
2
2

.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K

1
+

3

@
C185
330U_2.5V_M

2

SF000002Z00
330U 2.5V H4.2
17mohm OSCON

DDR_A_D63
DDR_A_D58
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D61
DDR_A_D57

+0.675VS

DDR_SMB_DA
DDR_SMB_CK

<8,14>
<8,14>

+0.675VS

C123 1

2 10U_0603_6.3V6M

C124 1
C122 1

2 1U_0402_6.3V6K

2 1U_0402_6.3V6K

V0.2 modify

Channel A

4

Layout Note:
Place near JDIMM1.203,204

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/08/21

2015/08/21

Deciphered Date

Title

DDR3L DIMMA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
A

B

C

D

Wednesday, March 04, 2015

Sheet
E

13

of

55

Rev
1.0

A

B

+DDR_B_VREF_DQ

C

+1.35V

D

E

+1.35V
CONN@
JDIMM2

DDR_B_D0
DDR_B_D1
DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9

1

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11
DDR_B_D22
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D23

All VREF traces should
have 10 mil trace width

DDR_B_D28
DDR_B_D30
DDR_B_DM3
DDR_B_D24
DDR_B_D26

<5>

DDR_B_CKE0

<5>

DDR_B_BS2

2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
<5>
<5>

DDR_B_CLK0
DDR_B_CLK0#
DDR_B_MA10

<5>

DDR_B_BS0

<5>
<5>

DDR_B_WE#
DDR_B_CAS#

<5>

DDR_B_CS1#

DDR_B_MA13

DDR_B_D48
DDR_B_D49
DDR_B_DQS#6

DDR_B_DQS6
DDR_B_D50
DDR_B_D51
3

DDR_B_D36
DDR_B_D37
DDR_B_DM4

Swap D4->D5,D5->D6,D6->D4

DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
+3VS
2

DDR_B_D56
DDR_B_D59
DDR_B_DM7

R229
10K_0402_5%
1

DDR_B_D61
DDR_B_D57

+3VS
+0.675VS

2

R231
0_0402_5%
@
1

C147
.1U_0402_16V7K

73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159

161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207

2
1

4

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

61
63
65
67
69
71

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#

DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD

A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49

VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
GND1
BOSS1

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6

DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD

A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4

VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS

EVENT#
SDA
SCL
VTT
GND2
BOSS2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46

48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106

108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166

168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208

LCN_DAN06-K4406-0100
Part Number = SP07000N300
LCN_DAN06-K4406-0100_204P

<Address: SA0:SA1=10 (A2H)>
SA0/SA1 Follow INTEL demo board

DIMM_2 STD H:4mm

DDR_B_DQS#[0..7]

DDR_B_D4
DDR_B_D5

DDR_B_DQS[0..7]

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D[0..63]
DDR_B_MA[0..15]

DDR_B_D6
DDR_B_D7

DDR_B_DM[0..7]

<5>
<5>
<5>
<5>
<5>

DDR_B_D12
DDR_B_D13

1

DDR_B_DM1
DDR_B_RST#

<5>

DDR_B_D14
DDR_B_D15
DDR_B_RST# C84

EMC@
1
2 .1U_0402_16V7K

DDR_B_D19
DDR_B_D16
DDR_B_DM2

FOR EMI/ESD Require 0926

DDR_B_D20
DDR_B_D21
+1.35V

DDR_B_D25
DDR_B_D27

+DDR_B_VREF_DQ
1

2

R1069
4.7K_0402_1%
1
2
R1067
4.7K_0402_1%

DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D31
DDR_B_D29

DDR_B_CKE1

1

2

C128
.1U_0402_16V7K

<5>
+1.35V

DDR_B_MA15
DDR_B_MA14

+DDR_B_VREF_CA
1

DDR_B_MA11
DDR_B_MA7
1
DDR_B_MA6
DDR_B_MA4

2
2

R1070
4.7K_0402_1%
2
R1068
4.7K_0402_1%

1

2

C142
.1U_0402_16V7K

DDR_B_MA2
DDR_B_MA0
DDR_B_CLK1 <5>
DDR_B_CLK1# <5>

+1.35V

DDR_B_BS1 <5>

DDR_B_RAS# <5>
DDR_B_CS0#
DDR_B_ODT0

<5>
<5>

DDR_B_ODT1

<5>

+DDR_B_VREF_CA
DDR_B_D52
DDR_B_D53

C133
C134
C135
C136

1
1
1
1

2
2
2
2

10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M

C129
C130
C131
C132
C137
C138
C139

1
1
1
1
1
1
1

2
2
2
2
2
2
2

.1U_0402_16V7K

.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K

DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D32
DDR_B_D33

Layout Note:
Place near JDIMM2

3

DDR_B_DQS#4
DDR_B_DQS4
+0.675VS

DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41

C143 1

2 10U_0603_6.3V6M

DDR_B_DM5

C145 1
C146 1

2 1U_0402_6.3V6K
2 1U_0402_6.3V6K

DDR_B_D42
DDR_B_D43
DDR_B_D63
DDR_B_D58

Layout Note:
Place near JDIMM2.203,204

DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D60

DDR_SMB_DA
DDR_SMB_CK

<8,13>
<8,13>

+0.675VS

V0.2 modify

Channel B

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/08/21

2015/08/21

Deciphered Date

Title

DDR3L DIMMB

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
A

B

C

D

Wednesday, March 04, 2015

Sheet
E

14

of

55

Rev
1.0


A

B

C

D

E

UGPU1A
+3VSDGPU_AON

Part 1 of 6

C6
B2
D6
C7
F9
A3
A4
B6
A6
F8
C5
E7
D7
B4
B3
C3
D5
D4
C2
F7

E6
C4

GC6_FB_EN

GC6_FB_EN

<9>
GPIO8_OVERT
GPIO9_ALERT

3VSDGPU_MAIN_EN

3VSDGPU_MAIN_EN
GPU_EVENT#_1

<38,51>

ACIN_BUF

5

GC6@
U2514
1
NC

DGPU_VID
ACIN_BUF
PSI

<9>
<51>

DGPU_VID
PSI

A

NL17SZ07DFT2G_SC70-5
SA00004BV00

<51>

4

Y

2

GPU_EVENT#

GPU_EVENT#_1

GC6@

2
D2000

GPU_PEX_RST_HOLD#

1

DGPU_AC_DETECT
RB751V-40_SOD323-2
VGA@

<34>

AG3
AF4
AF3
5

@
U2513
1
NC

R2056

2

@

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2

PEX_TX2_N
PEX_TX3
PEX_TX3_N
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

AE3
AE4

NC
NC

I2CS_SDA

R2000

1 VGA@

2 1.8K_0402_1%

I2CS_SCL

R2001

1 VGA@

2 1.8K_0402_1%

PSI

R2052

2 VGA@

1 10K_0402_5%

1 VGA@
R2009

PEG_CLKREQ#

2
10K_0402_5%
PEG_CLKREQ#

<7>
<7>

AE8
AD8
AC6

CLK_PEG_VGA
CLK_PEG_VGA#

2 @
R2010

PEX_TSTCLK_OUT+
1
PEX_TSTCLK_OUT200_0402_1%

AF22
AE22

2 VGA@
R2011

PLTRST_VGA#
1
PEX_TREMP
2.49K_0402_1%

AC7
AF25

3

A

2

H_PROCHOT#

NL17SZ07DFT2G_SC70-5
SA00004BV00

I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA

B7
A7

R2003
R2004

1 VGA@
1 VGA@

2 1.8K_0402_1%
2 1.8K_0402_1%

C9
C8

R2005
R2006

1 VGA@
1 VGA@

2 1.8K_0402_1%
2 1.8K_0402_1%

A9
B9

R2007
R2008

1 VGA@
1 VGA@

2 1.8K_0402_1%
2 1.8K_0402_1%

1
6
GPU_OVERT
VGA@
DMN66D0LDW-7_SOT363-6
Q2000A
PLTRST_VGA#

GPIO9_ALERT

D9
D8

I2CS_SCL
I2CS_SDA

I2CS_SCL
I2CS_SDA

L6
M6

+PLLVDD

1

C2000
2 .1U_0402_16V7K
VGA@

1

C2001
2 .1U_0402_16V7K
VGA@

N6
+GPU_PLLVDD

PLTRST_VGA#

+3VSDGPU_AON

0_0402_5% 1

1
R1165

@

2R1164

@

2
0_0402_5%

I2CS_SCL

PEX_REFCLK

PEX_REFCLK_N
PEX_CLKREQ_N

Place Under M6

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
PEX_RST_N
PEX_TERMP

C11 XTALIN
B10 XTALOUT

XTAL_IN
XTAL_OUT

PLTRST_VGA#

A10 XTAL_SSIN
C10 XTAL_OUTBUFF

XTAL_SSIN
XTAL_OUTBUFF

R2012 1 VGA@
R2013 1 VGA@

2
2

<34>

V1.0 modify

4
3
GPU_ALERT
VGA@
DMN66D0LDW-7_SOT363-6
Q2000B

Place Under L6
PLLVDD
SP_PLLVDD

LCD_BL_PWM

GPIO3

O

LCD_VCC

GPIO4

O

LCD_BL_EN

GPIO5

O

3V3_MAIN_EN

GPIO6

I

GPU_EVENT#

GPIO7

O

3D Vision

GPIO8

I

SYS_PEX_RST_MON#

GPIO9

I/O

ALERT

GPIO10

O

MEM_VREF_CTL

GPIO11

O

PWM_VID

GPIO12

I

PWR_LEVEL

GPIO13

O

PSI

1

PLTRST_VGA#

V0.2 modify
2

I2CA_SCL
I2CA_SDA

MEM_VDD_CTL

O

<9,34>

GPIO8_OVERT

CLK

<31>

Y

W5
AE2
AF2

NC
TSEN_VREF
NC

NC
+3VSDGPU_AON

4

ACIN_BUF

O

GPIO2

GPIO14

I

HPD_A

GPIO15

I

HPD_C

GPIO16

I

FRAME_LOCK#

GPIO17

I

HPD_D

GPIO18

I

HPD_E

GPIO19

I

HPD_F or HPD_B

2

5

2

AC9
AB9
AB10
AC10
AD11
AC11
AC12
AB12
AB13
AC13
AD14
AC14

AC15
AB15
AB16
AC16
AD17
AC17
AC18
AB18
AB19
AC19
AD20
AC20
AC21
AB21
AD23
AE23
AF24
AE24
AG24
AG25

GPIO1

1 10K_0402_5%

10K_0402_5%
10K_0402_5%

0_0402_5% 1

V1.0 modify

GPIO20

Reserved

GPIO21

O

GPU_PEX_RST_HOLD#

GPIO22

1
6
EC_SMB_CK2
VGA@
DMN66D0LDW-7_SOT363-6
Q2001A

<26,30,34,37>

GPIO23
GPIO24

V1.0 modify

2R1174

@

<34>

2

PEG_GTX_HRX_P0
PEG_GTX_HRX_N0
PEG_GTX_HRX_P1
PEG_GTX_HRX_N1

USAGE

3

+3VSDGPU_AON

1
@
R1168

GM108-ES-S-A1_FCBGA595
@

2
0_0402_5%

I2CS_SDA

5

.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K

G

2
2
2
2

3

1
1
1
1

DACs

CV11
CV12
CV13
CV14

PCI EXPRESS

VGA@

VGA@
VGA@
VGA@

PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_N0
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_N1

I2C

<7>
<7>
<7>
<7>

GC6_FB_EN

+3VSDGPU_AON

SYS_PEX_RST_MON#
+1.8VALW

NC
NC
NC

O

+3VSDGPU_AON

RP2001
10K_0804_8P4R_5%
8
1
GPU_EVENT#_1
7
2
3VSDGPU_MAIN_EN
3
GPU_PEX_RST_HOLD# 6
5
4
GC6_FB_EN

V1.0 modify

ACIN_BUF

I/O

GPIO0

VGA@

P

GPIO8_OVERT
GPIO9_ALERT

AB6

PEX_WAKE_NC

RP2000
10K_0804_8P4R_5%
8
1
7
2
6
3
5
4

+1.8VALW

G

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
OVERT
GPIO9
GPIO10
GPIO11

GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

P

1

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

3

AG6
AG7
AF7
AE7
AE9
AF9
AG9
AG10
AF10
AE10

AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22

PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_N1

GPIO

<7>
<7>
<7>
<7>

GPIO

4
3
EC_SMB_DA2
VGA@
DMN66D0LDW-7_SOT363-6
Q2001B

<26,30,34,37>

SM010019400 3000ma 33ohm@100mhz DCR 0.05

38mA
VGA@
1.5VS_DGPU_PWR_EN

1

BAV70W_SOT323-3
R2016
0_0402_5%
1 NGC6@ 2

1.5VS_DGPU_PWR_EN

<38,50>

PLL_VDD
0.1Ux1, 22Ux1
30ohm(ESR0.05)x1

GC6@
R2014
200K_0402_5%

2

1

+3VSDGPU_AON

5

R2017
10K_0402_5%
VGA@
SYS_PEX_RST_MON#

2

GPU_PEX_RST_HOLD#

1

B

Y
A

SP_PLLVDD+VID_PLLVDD
0.1Ux2, 10Ux1,47Ux1
300ohm(ESR0.2)x1

U2002
GC6@

4

BAT54A-7-F_SOT23-3
@

R2018
10K_0402_5%
GC6@

Reserved from NV suggest
B

1

XTALIN

1
C2005

2

VGA@

2
HCB1608KF-301T20_2P

C2007
VGA@
47U_0805_6.3V6M

4

Near GPU

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/08/28

2016/08/28

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

N16X PEG 1/9

A4WAL_Braswell-M/D_LA-C371P

Date:
A

1

1

GND
GND
VGA@
X2000
4
2

PLTRST_VGA#

MC74VHC1G08DFT2G_SC70-5

PLTRST_VGA#

2

3

1

3

C2006
10U_0603_6.3V6M
2
VGA@

2

GPU_PEX_RST_HOLD#

<17>

P

check
1

1

R2019

0_0402_5%
NGC6@

R2055
10K_0402_5%
@

2

2

SYS_PEX_RST_MON#

G

G

+3VSDGPU_AON

D2002
SYS_PEX_RST_MON#

1

4SYS_PEX_RST_MON#

3

Y

A
MC74VHC1G08DFT2G_SC70-5

1

B

1

Crystals must have a max ESR of 80 ohm

VGA@

1
L2001

2

1

C2004

+GPU_PLLVDD

2

2

VGA@

17mA

5

DGPU_HOLD_RST#

DGPU_HOLD_RST#

P

PLT_RST_BUF#

PLT_RST_BUF#

3

<31>

27MHZ_10PF_7V27000023

3

XTALOUT
C2003
VGA@
22U_0603_6.3V6M

SM01000AG00 2A 300ohm@100mhz DCR 0.1

V0.2 modify

<9,28,30,34,35>

2

2
CHILISIN PBY160808T-330Y-N

Near GPU

+3VSDGPU_AON
U2001
VGA@

4

1

2

3

VGA_PWROK

1
L2000

+PLLVDD

1

GC6@

10P_0402_50V8J

2

GC6_FB_EN

<31,38,51>

+1.05VSDGPU

D2001

10P_0402_50V8J

GC6 2.0 function

C

D

Wednesday, March 04, 2015

Sheet
E

15

of

55

Rev
1.0


A

B

C

D

E

VRAM Interface
+1.5VSDGPU

RP33
CMDA23
A5MUB exchange
CMDA21

1
2
3
4

UGPU1B
1

N16S-GT
SGT@

<20,21>

MDA[15..0]

<20,21>

MDA[31..16]

<22,23>

MDA[47..32]

<22,23>

MDA[63..48]

Part 2 of 6

CMDA[31..0]

MDA[31..16]

MDA[63..48]

UGPU1

N16V-GM
VGM@

SA000088R00

2

NV 15x DG-06803-V03
NV 16x DG-07158-V04

SM010019400 3000ma 33ohm@100mhz DCR 0.05
+1.05VSDGPU

15+55mA
+FB_PLLAVDD

Place Near GPU

change to 1.35VSDGPU

2

1

2

VGA@

1

2

C2009
.1U_0402_16V7K

2

1

VGA@
C2010
.1U_0402_16V7K

C2008
VGA@

VGA@
C2011
.1U_0402_16V7K

1

22U_0603_6.3V6M

VGA@
2
1
L2002

CHILISIN PBY160808T-330Y-N

F16
P22
T97 @ D23

H22

Place Under F16 P22 H22

+1.5VSDGPU

E18
F18
E16
F17
D20
D21
F20
E21
E15
D15
F15
F13
C13
B13
E13
D13
B15
C16

A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24
T22
R23
N25
N26
N23
N24
V23
V22
T23
U22
Y24
AA24
Y22
AA23

AD27
AB25
AD26
AC25
AA27
AA26
W26
Y25
R26
T25
N27
R27
V26
V27
W27
W25

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12

MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42

MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

MDA[47..32]

SA000087F00

3

+1.5VSDGPU

1 VGA@ 2
FB_CLAMP
10K_0402_5%
R2028

60.4_0402_1%
60.4_0402_1%

1
1

@
@

2
2

R2020FBA_CMD34
R2022FBA_CMD35

F3
F22
J22

FBA_D00
FBA_D01
FBA_D02
FBA_D03
FBA_D04
FBA_D05

FBA_D06
FBA_D07
FBA_D08
FBA_D09
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35

FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_CMD0

FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

FBA_CMD31

FB_PLLAVDD_1
FB_PLLAVDD_2
FB_VREF_PROBE
FB_DLLAVDD
FB_CLAMP
FBA_CMD34
FBA_CMD35

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3

FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22

J23
J25
J24
K27
K25
J27
J26

CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20
CMDA21

CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30
CMDA31

CMDA24

<20,21,22,23>

A5MUB exchange
CMDA26

1
2
3
4

A5MUB exchange
CMDA22

1
2
3
4

8
7
6
5
VGA@
100_0804_8P4R_5%

+1.5VSDGPU

CMDA12

1
2
3
4

1

+1.5VSDGPU

1

C2085
.1U_0402_16V7K
@

+1.5VSDGPU

2

8
7
6
5
VGA@
100_0804_8P4R_5%

1

2

C2086
.1U_0402_16V7K
1
@

8
7
6
5
VGA@
100_0804_8P4R_5%

C2083
.1U_0402_16V7K
@

+1.5VSDGPU

2

RP44
CMDA4
A5MUB exchange

2

C2084
.1U_0402_16V7K
1
@

RP43
CMDA10

+1.5VSDGPU

2

RP42

MEMORY
INTERFACE A

UGPU1

MDA[15..0]

8

7
6
5
VGA@
100_0804_8P4R_5%

2

C2088
.1U_0402_16V7K
1
@

1

C2087
.1U_0402_16V7K
@

RP45
CMDA8
A5MUB exchange
CMDA14

1
2
3
4

PVT modify 01/13

DQSA, DQSA# reverse

DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

F19
C14
A16
A22
P25
W22
AB27
T27

DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7

E19

C15
B16
B22
R25
W23
AB26
T26

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

DQMA[3..0]

<20,21>

DQMA[7..4]

<22,23>

A5MUB exchange

CMDA29

CMDA5

CMDA13

DQSA#[7..4]

1
2
3
4

8
7
6
5
VGA@
100_0804_8P4R_5%

+1.5VSDGPU

<20,21>

1
2
3
4

CMDA6
A5MUB exchange
CMDA7

DQSA[3..0]

<20,21>

DQSA[7..4]

<22,23>

1
2
3
4

2

C2090
.1U_0402_16V7K
1
@

8
7
6
5
VGA@
100_0804_8P4R_5%

+1.5VSDGPU

1

2

C2091
.1U_0402_16V7K
1
@

8
7
6
5
VGA@
100_0804_8P4R_5%

1

CMDA30

1
2
3
4

C2092
.1U_0402_16V7K
@

+1.5VSDGPU

2

RP49
CMDA27

C2089
.1U_0402_16V7K
@

+1.5VSDGPU

2

RP48

<22,23>

+1.5VSDGPU

2

RP47
A5MUB exchange

DQSA#[3..0]

2

RP46
CMDA9

D19
D14
C17
C22
P24
W24
AA25
U25

8
7
6
5
VGA@
100_0804_8P4R_5%

8
7
6
5
VGA@
100_0804_8P4R_5%

1

C2093
.1U_0402_16V7K
@

RP50

CMDA28
A5MUB exchange

FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N

D24
D25
N22
M22

CMDA25

CLKA0 <20,21>
CLKA0# <20,21>

1
2
3
4

CLKA1 <22,23>
CLKA1# <22,23>

8
7
6
5
VGA@
100_0804_8P4R_5%

3

RP51

D18
C18
D17
D16
T24
U24
V24
V25

CMDA15
A5MUB exchange
CMDA11

1
2

3
4

8
7
6
5
VGA@
100_0804_8P4R_5%

GM108-ES-S-A1_FCBGA595
@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/08/28

2016/08/28

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

N16X VRAM 2/9

A4WAL_Braswell-M/D_LA-C371P

Date:
A

B

C

D

Wednesday, March 04, 2015

Sheet
E

16

of

55

Rev
1.0


A

B

C

D

MULTI LEVEL STRAPS

UGPU1C

T2
T3
T1
R1
R2
R3
N2
N3
V3
V4

U3
U4
T4
T5
R4
R5

M4
M5
L3
L4
K4
K5
J4

J5
N4
N5
P3
P4
J2
J3

NC
NC
NC
NC
NC
NC
NC

NC

GPIO8
NC
NC
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
NC

NC
NC
NC
NC
NC
NC
NC

THERMDP
THERMDN

VDD_SENSE

GND_SENSE

NC
NC
NC

NC
NC
NC

SERIAL

1

1

1

1

1

1

1

R2032
@
4.99K_0402_1%

R2033
@
10K_0402_1%

R2035
X76@

30K_0402_1%

R2036
VGM@
4.99K_0402_1%

R2037
VGM@
4.99K_0402_1%

2

2

2

2

2

2

2

strap4

1

STRAP0
STRAP1

STRAP2
STRAP3
STRAP4

SYS_PEX_RST_MON#

SYS_PEX_RST_MON#

2

2

R2044
X76@
4.99K_0402_1%

R2045
SGT@
4.99K_0402_1%

1

R2042
VGM@
45.3K_0402_1%

R2046
SGT@
4.99K_0402_1%

2

R2041
VGM@
4.99K_0402_1%

1

R2040
@
15K_0402_1%

2

1

R2039
VGM@
45.3K_0402_1%

1

1

R2038
@
4.99K_0402_1%

2

1

For GC62.0 use
N14x for CEC ,NC
N15x for GPIO8

2 10K_0402_5%

@

2

1

ROM_SI
ROM_SO
ROM_SCLK

1

R2050

<15>

E10
F10
D1
D2
E4
E3

D3
C1

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

N16VGM Option Component

F6
F4
F5

MULTI_STRAP_REF0_GND
R2051

1 VGA@

--->

R2029 2 VGM@1 45.3K_0402_1% SD034453280

2
40.2K_0402_1%
2

F12
E12

F2

VCCSENSE_VGA

F1

VSSSENSE_VGA

VCCSENSE_VGA

<51>

VSSSENSE_VGA

<51>

AD9
AE5
AE6
AF6
AD6
AG4

Decive ID : 0x1347

For N16S-GT Binary strap table
GPU

TEST

TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

strap3

R2031
VGM@
10K_0402_1%

VRAM
Voltage

RANK

X76

Freq

Memory Size

X76615BOL13
NC
NC
NC

strap2

R2030
@
4.99K_0402_1%

2

R2029
SGT@
49.9K_0402_1%

D10
E9

+3VSDGPU_MAIN

strap1

1

strap0

2

D11

+3VSDGPU_AON

STRAP0

MULTI_STRAP_REF0_GND
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

F11
AD10
AD7
B19
V5
V6
G1
G2
G3
G4
G5
G6
G7
V1
V2
W1
W2

W3
W4

1

BUFRST_N
NC

NC
NC
NC
NC
NC
NC
NC
NC

2

N1
M1
M2
M3
K2
K3
K1
J1

NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

GENERAL

AB5
AB4
AB3
AB2
AD3
AD2
AE1
AD1
AD4
AD5

LVDS/TMDS

1

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
FBA_CMD32
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

2

Part 3 of 6

AC3
AC4
Y4
Y3
AA3
AA2
AB1
AA1
AA4
AA5

E

TESTMODE
R2054 1 VGA@ 2 10K_0402_5%
PAD @ T24
JTAG_TCK_VGA
JTAG_TDI
PAD @ T1
PAD @ T186
JTAG_TDO
PAD @ T3
JTAG_TMS
JTAG_RST
R2053 1 VGA@ 210K_0402_5%

N16S-GT

+1.5V

Dual

X76615BOL12

1GHz

256Mx16x8
4G

strap1

strap2

strap3

strap4

1GHz

256Mx16x4
2G

X76615BOL04

ROM_SI

ROM_SO

ROM_SCLK

PD 4.99K

PD 4.99K

PU 24.9K

0x1 (SA000077K20) Micron MT41J256M16HA-093G:E

PD 10K

0x2 (SA000076P20) Samsung K4W4G1646D-BC1A

X76615BOL03
+1.5V Single

strap0

0xC (SA00008DN10) Hynix H5TC4G63CFR-N0C

X76615BOL05
X76615BOL11

Memory Config

PU 49.9K

NC

NC

NC

NC

PD 15K

0x5 (SA00008DN10) Hynix H5TC4G63CFR-N0C

PD 30.1K

0x1 (SA000077K20) Micron MT41J256M16HA-093G:E

PD 10K

0x2 (SA000076P20) Samsung K4W4G1646D-BC1A

PD 15K

3

3

H3
H4

ROM_CS_N
ROM_SI

ROM_SO
ROM_SCLK

For N16V-GM Binary strap table

D12
B12 ROM_SI
A12 ROM_SO
C12 ROM_SCLK

GPU

VRAM
Voltage

RANK

X76

Freq

Memory Size

X76615BOL09

GM108-ES-S-A1_FCBGA595
@

+1.35V

Dual

N16V-GM

VGA Power Sequence

X76615BOL08

900MHz

256Mx16x8
4G

X76615BOL02

strap0

strap1

strap2

strap3

strap4

0xD (SA000077K20) Micron MT41J256M16HA-093G:E

256Mx16x4
2G

ROM_SO

ROM_SCLK

PU 4.99K

PU 4.99K

PU 30.1K
PU 24.9K
PU 45.3K

0x9 (SA00008DN10) Hynix H5TC4G63CFR-N0C
1GHz

ROM_SI
PU 15K

0xC (SA000076P20) Samsung K4W4G1646D-BC1A

X76615BOL01
+1.5V Single

Memory Config
0xA (SA00008DN10) Hynix H5TC4G63CFR-N0C

X76615BOL10
X76615BOL07

Decive ID : 0x1299

PD 45.3K

PU 10K

PD 4.99K

PD 45.3K
PU 10K

0x1 (SA000077K20) Micron MT41J256M16HA-093G:E

PD 10K

0x4 (SA000076P20) Samsung K4W4G1646D-BC1A

PD 24.9K

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/08/28

2016/08/28

Deciphered Date

Title

N16X LVDS 3/9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
A

B

C

D

Wednesday, March 04, 2015

Sheet
E

17

of

55

Rev
1.0


A

B

C

D

E

NV 15x DG-06803-V03
NV 16x DG-07158-V04

1

1

+1.05VSDGPU

UGPU1D

2

2

D22 FB_CAL_PD_VDDQ 1 VGA@ 2
40.2_0402_1% R2078

2

Under GPU

+3VSDGPU_MAIN

VGA@

2

1

1

VGA@

2

VGA@

1

2

VGA@

Near GPU

+3VSDGPU_AON

286mA

AB8

2

1
AA14
AA15

VGA@

1

2

1

VGA@

2

3

VGA@

Near GPU

130mA

+1.05VSDGPU
R2075
1
@

+PEX_PLLVDD

2

GM108-ES-S-A1_FCBGA595
@

1

1

VGA@

2

Under GPU

VGA@

Near GPU

1

2

2 0_0603_5%

C2043
4.7U_0603_6.3V6K

PEX_PLLVDD_1
PEX_PLLVDD_2

VGA@

Near GPU

Under GPU

PEX_SVDD_3V3

2

C2054

4.7U_0603_6.3V6K

2

1

PEX_PLL_HVDD_1
PEX_PLL_HVDD_2

1

FB_CAL_PU_GND 1 VGA@ 2
42.2_0402_1% R2079

B25 FB_CAL_TERM_GND1 VGA@ 2
51.1_0402_1% R2080

AA8
AA9

VGA@

C2053
1U_0402_6.3V6K

C24

1

VGA@

C2050
4.7U_0603_6.3V6K

56mA

C2049
1U_0402_6.3V6K

G10
G12
G8
G9

1

FB_CAL_TERM_GND

NC
NC
NC
NC
NC

C2017
22U_0603_6.3V6M

AA22
AB23
AC24

AD25
AE26
AE27

C2036
4.7U_0603_6.3V6K

3V3_AON
3V3_AON
VDD33_3
VDD33_4

FB_CAL_PD_VDDQ

IFPD_PLLVDD_2
NC
IFPD_RSET
NC

C2016
10U_0603_6.3V6M

Midway GPU & Power supply

+1.5VSDGPU

3

J7
K7

K6
H6
J6

Near GPU

C2042
1U_0402_6.3V6K

T7
R7
U6
R6

NC
NC
NC
NC

VGA@

+3VSDGPU_AON

FB_CAL_PU_GND
M7
N7
T6
P6

2

C2052
.1U_0402_16V7K

NC
NC
NC
NC
NC

2

1

VGA@

C2035
4.7U_0603_6.3V6K

V7
W7
AA6
W6
Y6

1

C2048
.1U_0402_16V7K

2

PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6

Under GPU

2

VGA@

C2051
.1U_0402_16V7K

Near GPU

2

VGA@

2

1

VGA@

C2034
.1U_0402_16V7K

2

VGA@

1

1

C2041
.1U_0402_16V7K

1

C2047
22U_0603_6.3V6M

Under GPU

PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9

PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14

C2014
4.7U_0603_6.3V6K

1

VGA@

FBVDDQ_01
FBVDDQ_02
FBVDDQ_03
FBVDDQ_04
FBVDDQ_05
FBVDDQ_06
FBVDDQ_07
FBVDDQ_08
FBVDDQ_09
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_AON
FBVDDQ_AON
FBVDDQ_AON

FBVDDQ_AON
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27

AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27

C2013
1U_0402_6.3V6K

1

VGA@

2

1.275A

Part 4 of 6

B26
C25
E23
E26
F14
F21
G13
G14
G15
G16
G18
G19
G20
G21
H24
H26
J21
K21
L22
L24
L26

M21
N21
R21
T21
V21
W21

C2022
.1U_0402_16V7K

2

VGA@

2

C2021
.1U_0402_16V7K

VGA@

C2033
1U_0402_6.3V6K

2

1

C2045
10U_0603_6.3V6M

2

VGA@

1

C2032
1U_0402_6.3V6K

2

VGA@

1

C2040
4.7U_0603_6.3V6K

1

C2039
4.7U_0603_6.3V6K

3.24A

POWER

+1.5VSDGPU

VGA@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/08/28

2016/08/28

Deciphered Date

Title

N16X POWER & GND 4/9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
A

B

C

D

Wednesday, March 04, 2015

Sheet
E

18

of

55

Rev
1.0


A

B

C

UGPU1F

+VGA_CORE

UGPU1E

D

+VGA_CORE

2

GND

1

GND_001
GND_002
GND_003
GND_004
GND_005
GND_006
GND_007
GND_008
GND_009
GND_010
GND_011

GND_012
GND_013
GND_014
GND_015
GND_016
GND_017
GND_018
GND_019
GND_020
GND_021
GND_022
GND_023
GND_024
GND_025
GND_026
GND_027
GND_028
GND_029
GND_030
GND_031
GND_032
GND_033
GND_034
GND_035
GND_036
GND_037
GND_038
GND_039
GND_040
GND_041

GND_042
GND_043
GND_044
GND_045
GND_046
GND_047
GND_048
GND_049
GND_050
GND_051
GND_052
GND_053
GND_054
GND_055
GND_056

Part 5 of 6

GND_057
GND_058
GND_059
GND_060
GND_061
GND_062
GND_063
GND_064
GND_065
GND_066
GND_067
GND_068

GND_069
GND_070
GND_071
GND_072
GND_073
GND_074
GND_075
GND_076
GND_077
GND_078
GND_079
GND_080
GND_081
GND_082
GND_083
GND_084
GND_085
GND_086
GND_087
GND_088
GND_089
GND_090
GND_091
GND_092
GND_093
GND_094
GND_095
GND_096
GND_097
GND_098

GND_099
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112

GND
GND

K11
K13
K15
K17
L10
L12
L14
L16
L18
L2
L23
L25

L5
M11
M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14

U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5

K10
K12
K14
K16
K18
L11
L13
L15
L17
M10
M12
M14
M16
M18
N11

N13
N15
N17
P10
P12

VDD_001
VDD_002
VDD_003
VDD_004
VDD_005
VDD_006
VDD_007
VDD_008
VDD_009
VDD_010
VDD_011
VDD_012
VDD_013
VDD_014
VDD_015
VDD_016
VDD_017
VDD_018
VDD_019
VDD_020

POWER

Part 6 of 6

A2
A26
AB11
AB14
AB17
AB20
AB24
AC2
AC22
AC26
AC5
AC8
AD12
AD13
AD15
AD16
AD18
AD19
AD21
AD22
AE11
AE14
AE17
AE20
AF1
AF11
AF14
AF17
AF20

AF23
AF5
AF8
AG2
AG26
B1
B11
B14
B17
B20
B23
B27
B5
B8
E11
E14
E17
E2
E20
E22
E25
E5
E8
H2
H23
H25
H5

V18
V16

V14
V12
V10
U17
U15
U13
U11
T18
T16
T14
T12
T10
R17
R15
R13
R11
P18
P16
P14

VDD_041
VDD_040
VDD_039
VDD_038
VDD_037
VDD_036
VDD_035
VDD_034
VDD_033
VDD_032

VDD_031
VDD_030
VDD_029
VDD_028
VDD_027
VDD_026
VDD_025
VDD_024
VDD_023
VDD_022
VDD_021

E

NV 15x DG-06803-V03
NV 16x DG-07158-V04
1

DA-07312-V02

GM108-ES-S-A1_FCBGA595
@

2

DA-07314-V02

AA7
AB7

GM108-ES-S-A1_FCBGA595
@

3

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/08/28

2016/08/28

Deciphered Date

Title

N16X POWER & GND 5/9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size

Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
A

B

C

D

Wednesday, March 04, 2015

Sheet
E

19

of

55

Rev
1.0

A

B

VRAM DDR3 chips

<16,21,22,23>

DQMA[7..0]

DQMA[7..0]

<16,21,22,23>

MDA[63..0]

MDA[63..0]

<16,21,22,23>

E

DQSA#[7..0]

DQSA#[7..0]

<16,21,22,23>

D

DQSA[7..0]

DQSA[7..0]

<16,21,22,23>

C

CMDA[30..0]

CMDA[30..0]

Lower Rank 0 BOT SIDE
1

X76
U2004 X76@
+MEM_VREFCA0
+MEM_VREFDQ0

N3
P7
P3
N2
P8
P2
R8
R2

T8
R3
L7
R7
N7
T3
T7
M7

CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14

M2
N8
M3

CMDA29

CMDA13
CMDA27

J7
K7
K9

CLKA0
CLKA0#
CMDA3
CMDA0
CMDA2
CMDA11
CMDA15
CMDA28

K1
L2
J3
K3
L3

DQSA2
DQSA1

F3
C7

DQMA2
DQMA1

E7
D3

DQSA#2
DQSA#1

G3
B7

T2

ZQ0

L8

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4

A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA20
MDA16
MDA21
MDA19
MDA23
MDA18
MDA22
MDA17

D7
C3
C8
C2
A7
A2
B8
A3

MDA12
MDA9
MDA14
MDA11
MDA13
MDA10
MDA15
MDA8

+MEM_VREFCA0 M8
+MEM_VREFDQ0 H1
CMDA7

CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14

Group2

V0.2 modify

Group1

+1.5VSDGPU

BA0
BA1
BA2

VDD
VDD
VDD

VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

B2
D9
G7
K2
K8
N1
N9
R1
R9

CMDA29

CMDA13
CMDA27

CLKA0
CLKA0#
CMDA3

+1.5VSDGPU

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

CMDA0
CMDA2
CMDA11
CMDA15

CMDA28

K1
L2
J3
K3
L3

DQSA3
DQSA0

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA3
DQMA0

E7
D3

DQSA#3
DQSA#0

G3
B7

CMDA20

T2

ZQ1

L8

R2082
VGA@
243_0402_1%

J1
L1
J9
L9

DQU0
DQU1
DQU2
DQU3

DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA25
MDA30
MDA24
MDA28
MDA27
MDA31
MDA26
MDA29

2

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
DQSL
VDDQ
DQSU
VDDQ
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

CMD0

ODT

Rank1

32..63

D7

C3
C8
C2
A7
A2
B8
A3

MDA6
MDA1
MDA4
MDA2
MDA5
MDA0
MDA7
MDA3

Group3

Group0

B2
D9
G7
K2
K8
N1
N9
R1
R9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

CKE

CMD4

A9

A9

CKE
A11

CMD5

A6

A6

A7

A7

CMD6

A3

A3

BA1

BA1

CMD7

A0

A0

A12

A12

CMD8

A8

A8

A8

A8

CMD9

A12

A12

A0

A0

CMD10

A1

A1

A2

A2

CMD11

RAS*

RAS*

RAS*

RAS*

CMD12

A13

A13

A14

A14

CMD13

BA1

BA1

A3

A3

CMD14

A14

A14

A13

A13

CMD15

CAS*

CAS*

CAS*

CAS*

A11

ODT

CS1*

CMD18

CS0*

CMD19

A9
B3
E1
G8
J2
J8

M1
M9
P1
P9
T1
T9

CKE

CKE

CMD20

RST

RST

RST

RST

CMD21

A7

A7

A6

A6

CMD22

A4

A4

A5

A5

CMD23

A11

A11

A9

A9

CMD24

A2

A2

A1

A1

CMD25

A10

A10

WE*

WE*

CMD26

A5

A5

A4

A4

CMD27

BA2

BA2

CMD28

WE*

WE*

A10

A10

CMD29

BA0

BA0

BA0

BA0

BA2

BA2

CMD30

B1
B9
D1
D8
E2
E8
F9

G1
G9

2

ODT

CMD17

A1
A8
C1
C9
D2
E9
F1
H2
H9

1

CS0*

CMD16
+1.5VSDGPU

32..63

ODT

CMD3

Not Available
3

Command Bit

96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96

DDR3

Default Pull-down

ODTx

10k

CKEx

10k

RST

10k

CS*

No Termination

CLKA0

CLKA0

1

<16,21>

0..31
CS1*

CMD2

+1.5VSDGPU

BA0
BA1
BA2

J7
K7
K9

0..31

CMD1
DQL0
DQL1
DQL2

DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

A1
A8
C1

C9
D2
E9
F1
H2
H9

2

J1
L1
J9
L9

R2081
VGA@
243_0402_1%
3

VREFCA
VREFDQ

1

CMDA20

VREFCA
VREFDQ

1

2

M8
H1

U2005 X76@

Rank0

Mode E
Address

2

VGA@
R2087
162_0402_1%
<16,21>

CLKA0#

+1.5VSDGPU

+1.5VSDGPU

CLKA0#
R2085
VGA@
1.33K_0402_1%

R2086
VGA@
1.33K_0402_1%
+MEM_VREFCA0

CMDA0
CMDA3
CMDA16
CMDA19
CMDA20

+1.5VSDGPU

2

VGA@

2

VGA@

2

VGA@

2

VGA@

2

VGA@

2

VGA@

1

2

C2082
.1U_0402_16V7K

VGA@

1

C2081
.1U_0402_16V7K

2

1

C2080
.1U_0402_16V7K

VGA@

1

C2079
.1U_0402_16V7K

2

1

C2078
1U_0402_6.3V6K

VGA@

1

C2077
1U_0402_6.3V6K

2

1

C2076
1U_0402_6.3V6K

VGA@

1

C2075
1U_0402_6.3V6K

2

1

C2074
1U_0402_6.3V6K

VGA@

1

C2073
1U_0402_6.3V6K

2

1

C2072
1U_0402_6.3V6K

1

C2071
1U_0402_6.3V6K

4

R2093 1
R2094 1
R2095 1
R2098 1
R2099 1

VGA@
VGA@
VGA@
VGA@
VGA@

2
2
2
2
2

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

R2091
VGA@
1.33K_0402_1%

+MEM_VREFCA0

1

2

+MEM_VREFDQ0

<21>

C2055
.1U_0402_16V7K
VGA@

+MEM_VREFDQ0

<21>

1

R2092
VGA@
1.33K_0402_1%

2

C2056
.1U_0402_16V7K
VGA@
4

VGA@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/08/28

2016/08/28

Deciphered Date

Title

N16X Upper Rank0 6/9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
A

B

C

D

Wednesday, March 04, 2015

Sheet
E

20

of

55

Rev
1.0


A

B

VRAM DDR3 chips

<16,20,22,23>
<16,20,22,23>

E

DQSA#[7..0]
DQMA[7..0]

DQMA[7..0]

<16,20,22,23>
<16,20,22,23>

D

DQSA[7..0]

DQSA[7..0]
DQSA#[7..0]

<16,20,22,23>

C

MDA[63..0]

MDA[63..0]

CMDA[30..0]

CMDA[30..0]

Lower Rank 1 TOP SIDE

1

1

U2007 X76@
U2006 X76@
+MEM_VREFCA0
+MEM_VREFDQ0

+MEM_VREFCA0 M8
+MEM_VREFDQ0 H1
CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12

CMDA29
CMDA6
CMDA30

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3

VREFCA
VREFDQ
A0
A1
A2

A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
BA0
BA1
BA2

2

<16,20>
<16,20>

CLKA0
CLKA0#

CLKA0
CLKA0#
CMDA3

J7

K7
K9

CMDA0
CMDA1
CMDA11
CMDA15
CMDA25

K1
L2
J3
K3
L3

DQSA2
DQSA1
DQMA2
DQMA1

F3
C7
E7
D3
G3
B7

CMDA20

T2

ZQ2

L8

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ

VDDQ
DQSL
VDDQ
DQSU
VDDQ

DQSL
DQSU

RESET
ZQ/ZQ0

MDA16
MDA20
MDA19
MDA21
MDA17
MDA22
MDA18
MDA23

D7
C3
C8
C2
A7
A2
B8
A3

MDA9
MDA12
MDA11
MDA14
MDA8
MDA15
MDA10
MDA13

+MEM_VREFCA0 M8
+MEM_VREFDQ0 H1

Group2

V0.2 modify

Group1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B2
D9
G7
K2
K8
N1
N9
R1
R9

2

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ

CMDA29
CMDA6
CMDA30

M2
N8
M3

CLKA0
CLKA0#
CMDA3

J7
K7
K9

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2

F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3

MDA30
MDA25
MDA28
MDA24
MDA29
MDA26
MDA31
MDA27
MDA1
MDA6
MDA2
MDA4
MDA3
MDA7
MDA0
MDA5

CMDA0
CMDA1
CMDA11
CMDA15
CMDA25

K1
L2
J3
K3
L3

DQSA3
DQSA0

F3
C7

DQMA3
DQMA0

E7
D3

DQSA#3
DQSA#0

G3
B7

CMDA20

T2

ZQ3

L8

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0

A9
B3
E1

G8
J2
J8
M1
M9
P1
P9
T1
T9

ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET

DR@
R2101
243_0402_1%

B1
B9
D1
D8
E2
E8
F9
G1

G9

J1
L1
J9
L9

ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

ODT

Group3

Group0

+1.5VSDGPU

32..63

ODT

CKE

CMD3

CKE

CMD4

A9

A9

A11

CMD5

A6

A6

A7

A7

CMD6

A3

A3

BA1

BA1

CMD7

A0

A0

A12

A12

CMD8

A8

A8

A8

A8

CMD9

A12

A12

A0

A0

CMD10

A1

A1

A2

A2

CMD11

RAS*

RAS*

RAS*

RAS*

CMD12

A13

A13

A14

A14

A11

CMD13

BA1

BA1

A3

A3

CMD14

A14

A14

A13

A13

CMD15

CAS*

CAS*

CAS*

CAS*

ODT

CMD16

A1
A8
C1
C9
D2
E9
F1
H2
H9

0..31
CS1*

CS1*
CS0*

CMD18
CMD19

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

2

ODT

CMD17

CKE

CKE

CMD20

RST

RST

RST

RST

CMD21

A7

A7

A6

A6

CMD22

A4

A4

A5

A5

CMD23

A11

A11

A9

A9

CMD24

A2

A2

A1

A1

CMD25

A10

A10

WE*

WE*

CMD26

A5

A5

A4

A4

CMD27

BA2

BA2

CMD28

WE*

WE*

A10

A10

CMD29

BA0

BA0

BA0

BA0

BA2

BA2

CMD30

3

Not Available

Command Bit

96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96

96-BALL
SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

32..63

CS0*

CMD2

+1.5VSDGPU

B2
D9
G7
K2
K8
N1
N9
R1
R9

0..31

CMD0

Rank1

CMD1

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

2

DR@
R2100
243_0402_1%

3

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7

N7
T3
T7
M7

CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12

+1.5VSDGPU

ODT/ODT0
CS/CS0
RAS
CAS
WE

DML

DMU

E3
F7
F2
F8
H3
H8
G2
H7

1

DQSA#2
DQSA#1

CK
CK
CKE/CKE0

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1

<20>
<20>

Rank0

Mode E
Address

DDR3

Default Pull-down

ODTx

10k

CKEx

10k

RST
CS*

10k
No Termination

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

2

DR@

2

4

DR@

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Issued Date

1

C2070
.1U_0402_16V7K

2

1

C2069
.1U_0402_16V7K

2

1

C2068
.1U_0402_16V7K

2

1

C2067
.1U_0402_16V7K

2

DR@

1

C2066
1U_0402_6.3V6K

2

1

C2065
1U_0402_6.3V6K

2

1

C2064
1U_0402_6.3V6K

2

1

C2063
1U_0402_6.3V6K

2

1

C2062
1U_0402_6.3V6K

2

1

C2061
1U_0402_6.3V6K

2

4

1

C2060
1U_0402_6.3V6K

1

C2059
1U_0402_6.3V6K

+1.5VSDGPU

2014/08/28

2016/08/28

Deciphered Date

Title

N16X Upper Rank1 7/9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
A

B

C

D

Wednesday, March 04, 2015

Sheet

E

21

of

55

Rev
1.0


A

B

VRAM DDR3 chips

<16,20,21,23>
<16,20,21,23>
<16,20,21,23>

D

E

DQSA[7..0]

DQSA[7..0]

DQSA#[7..0]

DQSA#[7..0]

DQMA[7..0]

DQMA[7..0]

<16,20,21,23>
<16,20,21,23>

C

Upper Rank 0 BOT SIDE

MDA[63..0]

MDA[63..0]

CMDA[30..0]

CMDA[30..0]

1

U2008 X76@
+MEM_VREFCA1 M8
+MEM_VREFDQ1 H1

CMDA16

CMDA18
CMDA11
CMDA15
CMDA28

K1
L2
J3
K3
L3

DQSA4
DQSA7

F3
C7

DQMA4
DQMA7

E7
D3

ZQ5

L8

R2083
VGA@
243_0402_1%

J1
L1
J9
L9

D7
C3
C8
C2
A7
A2
B8
A3

MDA56
MDA59
MDA58
MDA62
MDA57
MDA61
MDA60
MDA63

M8
H1

+MEM_VREFCA1
+MEM_VREFDQ1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

CMDA7
CMDA10
CMDA24
CMDA6
CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9

CMDA12
CMDA14

Group4

V0.2 modify

Group7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDDQ
310mAVDDQ
DQSL
VDDQ
DQSU
VDDQ
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

B2
D9

G7
K2
K8
N1
N9
R1
R9

M2
N8
M3

CMDA29
CMDA13
CMDA27

J7
K7
K9

CLKA1
CLKA1#
CMDA19

+1.5VSDGPU

A1
A8
C1
C9

D2
E9
F1
H2
H9

CMDA16
CMDA18
CMDA11
CMDA15
CMDA28

K1
L2
J3
K3
L3

DQSA6
DQSA5

F3
C7

A9
B3
E1
G8
J2
J8

M1
M9
P1
P9
T1
T9

DQMA6
DQMA5

E7
D3
G3
B7

DQSA#6
DQSA#5

CMDA20

T2

ZQ4

L8

VREFCA
VREFDQ
A0
A1

A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6

DQU7

E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3

MDA50
MDA52
MDA49
MDA53
MDA48
MDA55
MDA51
MDA54
MDA41
MDA44
MDA40

MDA46
MDA43
MDA47
MDA42
MDA45

Group6

Group5

+1.5VSDGPU

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0

CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

DQSL
DQSU

RESET
ZQ/ZQ0

B2
D9
G7
K2
K8
N1
N9
R1
R9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

3

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

R2084
VGA@
243_0402_1%

2

2

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL
SDRAM DDR3

H5TQ2G63BFR-11C_FBGA96

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

Rank0

Mode E
Address

0..31

CMD0

ODT

Rank1

+1.5VSDGPU

ODT

CMD2

CS0*

CMD3

CKE

CMD4

A9

A9

A11

CMD5

A6

A6

A7

A7

CMD6

A3

A3

BA1

BA1

CMD7

A0

A0

A12

A12

CMD8

A8

A8

A8

A8

CMD9

A12

A12

A0

A0

CMD10

A1

A1

A2

A2

CMD11

RAS*

RAS*

RAS*

RAS*

CMD12

A13

A13

A14

A14

CMD13

BA1

BA1

A3

A3

CMD14

A14

A14

A13

A13

CMD15

CAS*

CAS*

CAS*

CAS*

CKE
A11

ODT

CS1*

CMD18

CS0*

CMD19

B1
B9
D1
D8
E2
E8
F9

G1
G9

2

ODT

CMD17

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

1

32..63

CS1*

CMD16

A1
A8
C1
C9
D2
E9
F1
H2
H9

CKE

CKE

CMD20

RST

RST

RST

RST

CMD21

A7

A7

A6

A6

CMD22

A4

A4

A5

A5

CMD23

A11

A11

A9

A9

CMD24

A2

A2

A1

A1

CMD25

A10

A10

WE*

WE*

CMD26

A5

A5

A4

A4

CMD27

BA2

BA2

CMD28

WE*

WE*

A10

A10

CMD29

BA0

BA0

BA0

BA0

BA2

BA2

CMD30
Not Available

96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96

3

Command Bit

DDR3

Default Pull-down

ODTx

10k

CKEx

10k

RST

10k

CS*

+1.5VSDGPU

0..31

32..63

CMD1

1

T2

MDA33
MDA39
MDA32
MDA36
MDA35
MDA37
MDA34
MDA38

1

CMDA20

E3
F7
F2
F8
H3
H8
G2
H7

+1.5VSDGPU

CK

CK
CKE/CKE0

G3
B7

DQSA#4
DQSA#7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BA0
BA1
BA2

J7
K7
K9

CLKA1
CLKA1#
CMDA19

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

CMDA29
CMDA13
CMDA27

2

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

CMDA7
CMDA10
CMDA24
CMDA6

CMDA22
CMDA26
CMDA5
CMDA21
CMDA8
CMDA4
CMDA25
CMDA23
CMDA9
CMDA12
CMDA14

U2009 X76@

No Termination

+1.5VSDGPU

+1.5VSDGPU

2

VGA@

1

2

VGA@

1

2

VGA@

1

2

VGA@

1

2

VGA@

1

2

+MEM_VREFCA1

VGA@
R2096
VGA@
1.33K_0402_1%

4

+MEM_VREFCA1

+MEM_VREFDQ1

<23>

1

2

R2097
VGA@
1.33K_0402_1%

C2057
.1U_0402_16V7K
VGA@

<16,23>

<23>

2014/08/28

CLKA1

CLKA1

VGA@

R2103
162_0402_1%

1

2

C2058
.1U_0402_16V7K
VGA@

<16,23>

CLKA1#

CLKA1#

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

+MEM_VREFDQ1

1

1

R2089
VGA@
1.33K_0402_1%

2

2

VGA@

C2105
.1U_0402_16V7K

1

C2099
.1U_0402_16V7K

2

VGA@

C2101
.1U_0402_16V7K

1

C2102

.1U_0402_16V7K

2

VGA@

C2096
1U_0402_6.3V6K

1

C2100
1U_0402_6.3V6K

2

VGA@

C2097
1U_0402_6.3V6K

1

C2095
1U_0402_6.3V6K

2

VGA@

C2103
1U_0402_6.3V6K

1

C2094
1U_0402_6.3V6K

2

VGA@

C2104
1U_0402_6.3V6K

1

C2098
1U_0402_6.3V6K

R2088
VGA@
1.33K_0402_1%

2016/08/28

Deciphered Date

Title

N16X Lower Rank0 8/9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
A

B

C

D

Wednesday, March 04, 2015

Sheet
E

22

of

55

Rev
1.0


A

B

VRAM DDR3 chips

<16,20,21,22>
<16,20,21,22>

E

DQSA#[7..0]
DQMA[7..0]

DQMA[7..0]

<16,20,21,22>
<16,20,21,22>

D

DQSA[7..0]

DQSA[7..0]

DQSA#[7..0]

<16,20,21,22>

C

MDA[63..0]

MDA[63..0]

CMDA[30..0]

CMDA[30..0]

Upper Rank 1 TOP SIDE
1

1

U2010 X76@
<22>
<22>

+MEM_VREFCA1 M8
+MEM_VREFDQ1 H1

+MEM_VREFCA1
+MEM_VREFDQ1

CMDA9

CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5
CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12

CMDA29
CMDA6
CMDA30

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7

R7
N7
T3
T7
M7
M2
N8
M3

VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
BA0
BA1
BA2

2

CLKA1
CLKA1#

CLKA1
CLKA1#
CMDA19

J7
K7
K9

CMDA16
CMDA17
CMDA11
CMDA15
CMDA25

K1
L2
J3
K3
L3

DQSA4
DQSA7
DQMA4
DQMA7

DQSA#4
DQSA#7

F3
C7
E7
D3
G3
B7

T2

ZQ6

L8

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD

VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

DQSL
DQSU

RESET
ZQ/ZQ0

MDA39
MDA33
MDA36
MDA32
MDA38
MDA34
MDA37

MDA35

D7
C3
C8
C2
A7
A2
B8
A3

MDA59
MDA56
MDA62
MDA58
MDA63
MDA60
MDA61
MDA57

+MEM_VREFCA1 M8
+MEM_VREFDQ1 H1
CMDA9
CMDA24
CMDA10
CMDA13
CMDA26
CMDA22
CMDA21
CMDA5

CMDA8
CMDA23
CMDA28
CMDA4
CMDA7
CMDA14
CMDA12

Group4

V0.2 modify

Group7

+1.5VSDGPU

ODT/ODT0
CS/CS0
RAS
CAS
WE

DML
DMU

E3
F7
F2
F8
H3

H8
G2
H7

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B2
D9
G7
K2
K8
N1
N9
R1
R9

CMDA29
CMDA6
CMDA30

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

2

M2
N8
M3

J7
K7
K9

CMDA16
CMDA17
CMDA11
CMDA15
CMDA25

K1

L2
J3
K3
L3

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA6
DQMA5
DQSA#6
DQSA#5

CMDA20

F3
C7
E7
D3
G3

B7

T2
L8

ZQ7

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1

D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

R2102
243_0402_1%
DR@

2

R2090
243_0402_1%
DR@

3

N3
P7
P3
N2
P8
P2

R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

CLKA1
CLKA1#
CMDA19

DQSA6
DQSA5

1

CMDA20

CK
CK
CKE/CKE0

DQL0
DQL1
DQL2
DQL3

DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12

A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDA52
MDA50
MDA53
MDA49
MDA54
MDA51
MDA55
MDA48

D7
C3
C8
C2
A7
A2
B8
A3

MDA44
MDA41
MDA46
MDA40
MDA45
MDA42
MDA47
MDA43

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK

CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

B2
D9
G7
K2
K8
N1
N9
R1
R9

96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

ODT

32..63

Group6

Group5

A5MUB SWAP

32..63

ODT
CS1*
CKE

CMD3

CKE

CMD4

A9

A9

A11

CMD5

A6

A6

A7

A7

CMD6

A3

A3

BA1

BA1

CMD7

A0

A0

A12

A12

CMD8

A8

A8

A8

A8

CMD9

A12

A12

A0

A0

CMD10

A1

A1

A2

A2

CMD11

RAS*

RAS*

RAS*

RAS*

CMD12

A13

A13

A14

A14

CMD13

BA1

BA1

A3

A3

CMD14

A14

A14

A13

A13

CMD15

CAS*

CAS*

CAS*

CAS*

A11

ODT

CMD16

+1.5VSDGPU

0..31

CS0*

CMD2

+1.5VSDGPU

BA0
BA1
BA2

0..31

CMD0

Rank1

CMD1

CS1*
CS0*

CMD18

CMD19

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9

2

ODT

CMD17

A1
A8
C1
C9
D2
E9
F1
H2
H9

1

<16,22>
<16,22>

U2011 X76@

Rank0

Mode E
Address

CKE

CKE

CMD20

RST

RST

RST

RST

CMD21

A7

A7

A6

A6

CMD22

A4

A4

A5

A5

CMD23

A11

A11

A9

A9

CMD24

A2

A2

A1

A1

CMD25

A10

A10

WE*

WE*

CMD26

A5

A5

A4

A4

CMD27

BA2

BA2

CMD28

WE*

WE*

A10

A10

CMD29

BA0

BA0

BA0

BA0

BA2

BA2

CMD30

3

Not Available

Command Bit

96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96

DDR3

Default Pull-down

ODTx

10k

CKEx

10k

RST
CS*

10k
No Termination

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

DR@

2

DR@

1

2

C2106
.1U_0402_16V7K

2

1

C2108
.1U_0402_16V7K

2

1

C2109
.1U_0402_16V7K

2

1

C2146
.1U_0402_16V7K

2

1

C2152
1U_0402_6.3V6K

2

1

C2107
1U_0402_6.3V6K

2

1

C2149
1U_0402_6.3V6K

2

1

C2148
1U_0402_6.3V6K

2

1

C2150
1U_0402_6.3V6K

2

1

C2147
1U_0402_6.3V6K

2

1

C2151
1U_0402_6.3V6K

1

C2110
1U_0402_6.3V6K

+1.5VSDGPU

DR@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/08/28

2016/08/28

Deciphered Date

Title

N16X Lower Rank1 9/9

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A4WAL_Braswell-M/D_LA-C371P

Date:
A

B

C

D

Wednesday, March 04, 2015

Sheet
E

23

of

55

Rev
1.0


A

B

C

D

E

Place closed to JEDP1
+LCDVDD
+3VS

LCD/ LED PANEL Conn.

LCD POWER CIRCUIT
+3VS

+LCDVDD
U8
5

1

IN

1
C140
1U_0402_6.3V6K

<6>

OUT
GND

4
2

EN

OC

1

W=60mils
+19VB

2

W=60mils

1

3
2

SY6288C20AAC_SOT23-5

1

SM010014520 3000ma
220ohm@100mhz
DCR 0.04

2

EMC@
+INVPWR_B+

L11
HCB2012KF-221T30_2P
1
2

C367
4.7U_0603_6.3V6K

1
C376
.1U_0402_16V7K
EMC@

2

C419
.1U_0402_16V7K
@
1

W=60mils

JEDP1

W=60mils

1
2
3
4

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

35
36
37
38
39
40

+INVPWR_B+
@EMC@
C365
68P_0402_50V8J

1

1

2

2

@EMC@
C364
1000P_0402_50V7K
INVT_PWM_SOC
EC_BKOFF#

ENVDD
<31>

EDP_HPD_CONN

+LCDVDD

EDP_AUXN_C
EDP_AUXP_C
EDP_TXP0_C
EDP_TXN0_C
<34>

EC_BKOFF#

EC_BKOFF#

R280 1
C529

<6>

INVT_PWM_SOC

<6> EDP_TXN0
<6> EDP_TXP0

<6> EDP_TXN1
<6> EDP_TXP1

2 10K_0402_5%
EDP_TXP1_C
EDP_TXN1_C

@EMC@

1
2 220P_0402_50V7K

R393 1

@

2100K_0402_5%

@EMC@
1
2 220P_0402_50V7K
C550

eDP
2

INVT_PWM_SOC

@

C375 1
C409 1

C387 1
C390 1

2
2

2
2

+TS_PWR
<34>

0.1U_0402_16V7K EDP_TXN0_C
0.1U_0402_16V7K EDP_TXP0_C

USB TS

TS_EN

TS_EN

<9> USB20_P3
<9> USB20_N3

I2C2_SCL_PNL
I2C2_SDA_PNL
TS_RST#
TS_INT#

<8> I2C2_SCL_PNL
<8> I2C2_SDA_PNL
<34> TS_RST#
<31> TS_INT#

0.1U_0402_16V7K EDP_TXN1_C
0.1U_0402_16V7K EDP_TXP1_C

+3VS

1
@
0_0402_5%

2
+3VS_Camcra
R1162 USB20_P2_CAMERA
USB20_N2_CAMERA

+3VS
<6> EDP_AUXN
<6> EDP_AUXP

C369 1
C370 1

2 0.1U_0402_16V7K EDP_AUXN_C R613 2
2 0.1U_0402_16V7K EDP_AUXP_C R614 2

@
@

V1.0 modify

1 100K_0402_5%
1 100K_0402_5%

For Touch Panel

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

29
30
31
32
33
34
35
36
37
38
39
40

G1
G2
G3
G4
G5
G6

41
42
43
44
45
46

2

E-T_0871K-F40N-00L

SP010011Z00
CONN@

For Camera

V1.0 modify
+5VS
3

+TS_PWR
R1145
1
@

R427 1
R428 1

@
@

2 0_0402_5%
2 0_0402_5%
3

2 0_0603_5%

SM070003Y00
<9>

USB20_P2

USB20_P2

3

USB20_N2

2

3

4

4

USB20_P2_CAMERA

1

USB20_N2_CAMERA

+3VS
<9>
1

USB20_N2

2
@
R1146

0_0603_5%

2
1
DLW21HN900HQ2L_4P
L27 @EMC@

V0.2 modify

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/19

2015/03/18

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

eDP CONN.

A4WAL_Braswell-M/D_LA-C371P

Date:
A

B

C

D

Sheet

Wednesday, March 04, 2015
E

24

of

55

Rev

1.0


A

B

C

W=40mils

+HDMI_5V_OUT

U52
OUT

1

IN
GND

1

2

2

<6>
<6>

HDMI_TX2+
HDMI_TX2-

C380 2
C379 2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_C_TX2+
HDMI_C_TX2-

<6>
<6>

HDMI_TX1+
HDMI_TX1-

C382 2
C381 2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_C_TX1+
HDMI_C_TX1-

<6>
<6>

HDMI_TX0+
HDMI_TX0-

C384 2
C383 2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_C_TX0+
HDMI_C_TX0-

<6>
<6>

HDMI_CLK+
HDMI_CLK-

C386 2
C385 2

1 .1U_0402_16V7K
1 .1U_0402_16V7K

HDMI_C_CLK+
HDMI_C_CLK-

1 0_0402_5%

HDMI_R_CK-

@

1 0_0402_5%

HDMI_R_CK+

HDMI_C_TX0-

R370 2

@

1 0_0402_5%

HDMI_R_D0-

HDMI_C_TX0+

R371 2

@

1 0_0402_5%

HDMI_R_D0+

HDMI_C_TX1-

R372 2

@

1 0_0402_5%

HDMI_R_D1-

HDMI_C_TX1+

R373 2

@

1 0_0402_5%

HDMI_R_D1+

HDMI_C_TX2-

R374 2

@

1 0_0402_5%

HDMI_R_D2-

HDMI_C_TX2+

R375 2

@

1 0_0402_5%

HDMI_R_D2+

1

V0.2 modify

+5VALW

1 2.2K_0402_5%
1 2.2K_0402_5%

@
@

V0.2 modify

+HDMI_5V_OUT

Level Shifter (Other BOM)

4
3
2
1

HDMI_C_TX0HDMI_C_TX0+
HDMI_C_CLKHDMI_C_CLK+

4
3
2
1

U2507

HDMI_DDCDATA

SCL1
SDA1

SCL2
SDA2

6

HDMI_SCLK

5

HDMI_SDATA

+3VS

G3401A91G ADFN3X2 8P
SA00006YA00

R1060 1

2 20K_0402_5%

@

JHDMI1

+5VS

HDMI_HPD

2

HDMI_R_CK-

2

D

S

D

G

D

HDMI_R_CK+

HDMI_R_D0D2
@EMC@
YSLC05CH_SOT23-3

1

+1.8VALW

HDMI_R_D0+
HDMI_R_D1-

1

2

S

4
Q2513A
DMN63D8LDW-7_SOT363-6
@
SB000013K00
1
HDMI_DDCDATA_L 6
Q2513B
DMN63D8LDW-7_SOT363-6
SB000013K00
G

@

1
6
Q2514B
PJT138KA 2N SOT363-6
SB000016K00
S

3

G

G

@
3

HDMI_DDCCLK_L

D

S

HDMI_SDATA
HDMI_SCLK

5

5

+HDMI_5V_OUT

3

HDMI_R_D1+
HDMI_R_D2-

Reserved for ESD

HDMI_R_D2+

R376
10K_0402_5%

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKCK_shield
CK+
D0D0_shield
D0+
D1D1_shield
D1+
GND
D2GND
D2_shield GND
D2+

GND

20
21
22
23

ZZZ1

HDMI_ROYALTY
ROYALTY HDMI W/LOGO+HDCP

DC232004400

HDMI_HPD#

45@
G

D

2

HDMI_HPD

1

1

S

Q14B
DMN66D0LDW-7_SOT363-6

2

R121
100K_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2014/03/19

2015/03/18

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDMI CONN.

A4WAL_Braswell-M/D_LA-C371P

Date:
A

4

RO0000003HM

6

<6>

19
18
17
16
15
14
13
12
11
10
9
8
7
6

5
4
3
2
1

ACON_HMRB4-AK120C
CONN@

2

4

3

HDMI connector

+1.8VALW

@

Q14A
DMN66D0LDW-7_SOT363-6

Intel Sugesstion

V1.0 modify

4
Q2514A

PJT138KA 2N SOT363-6
SB000016K00

5

4

4

GND

HDMI_DDCDATA

3

HDMI_DDCCLK

3

EN

RP18
470_8P4R_5%
7

VREF2

1

<6>

HDMI_DDCCLK

5
6
7
8

S

<6>
3

VREF1

RP17
470_8P4R_5%
5
6
7
8

1
200K_0402_5%

+1.8VALW
8

HDMI_C_TX1HDMI_C_TX1+
HDMI_C_TX2HDMI_C_TX2+

HDMI_GND

2
R2574

2

2

+HDMI_5V_OUT

4
3
2
1

2.2K_0804_8P4R_5%
HDMI_DDCDATA_L R2568 2
HDMI_DDCCLK_L R2567 2

@

R369 2

+1.8VALW

RP15
5
6

7
8

HDMI_DDCDATA
HDMI_DDCCLK
HDMI_SDATA
HDMI_SCLK

R368 2

HDMI_C_CLK+
C378
.1U_0402_16V7K

AP2330W-7_SC59-3

2

HDMI_C_CLK3

G

1

E

D

+5VS

D

B

C

D

Wednesday, March 04, 2015

Sheet
E

25

of

55

Rev
1.0