Tài liệu Arithmetic Circuits ppt

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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Digital Integrated
Digital Integrated
Circuits
Circuits
A Design Perspective
A Design Perspective
Arithmetic Circuits
Arithmetic Circuits
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
January, 2003
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
A Generic Digital Processor
A Generic Digital Processor
MEM ORY
DATAPATH
CONTROL
INPUT-OUTPUT
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© Digital Integrated Circuits

2nd
Arithmetic Circuits
Building Blocks for Digital Architectures
Building Blocks for Digital Architectures
Arithmetic unit
-
Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.)
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
An Intel Microprocessor
An Intel Microprocessor
9-1 Mux9-1 Mux
5-1 Mux2-1 Mux
ck1
CARRYGEN
SUMGEN
+ LU
1000um

b
s0
s1
g64
sum
sumb
LU : Logical
Unit
SUMSEL
a
to Cache
node1
REG
Itanium has 6 integer execution units like this
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Bit-Sliced Design
Bit-Sliced Design
Bit 3
Bit 2
Bit 1
Bit 0
Register
Adder
Shifter
Multiplexer
Control

Data-In
Data-Out
Tile identical processing elements
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Bit-Sliced Datapath
Bit-Sliced Datapath
Adder stage 1
Wiring
Adder stage 2
Wiring
Adder stage 3
B
i
t

s
l
i
c
e

0
B
i
t

s
l
i
c
e

2
B
i
t

s
l
i
c
e

1
B
i
t

s
l
i
c
e

6
3

Sum Select
Shifter
Multiplexers
L
o
o
p
b
a
c
k

B
u
s
From register files / Cache / Bypass
To register files / Cache
L
o
o
p
b
a
c
k

B
u
s
L

o
o
p
b
a
c
k

B
u
s
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Itanium Integer Datapath
Itanium Integer Datapath
Fetzer, Orton, ISSCC’02
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Adders
Adders
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© Digital Integrated Circuits
2nd

Arithmetic Circuits
Full-Adder
Full-Adder
A B
Cout
Sum
Cin
Full
adder
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
The Binary Adder
The Binary Adder
S A B C
i
⊕ ⊕
=
A= BC
i
ABC
i
ABC
i
ABC
i
+ + +
C

o
AB BC
i
AC
i
+ +=
A B
Cout
Sum
Cin
Full
adder
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Express Sum and Carry as a function of P, G, D
Express Sum and Carry as a function of P, G, D
Define 3 new variable which ONLY depend on A, B
Generate (G) = AB
Propagate (P) = A
⊕
B
Delete = A B
Can also derive expressions for
S
and
C
o

based on
D and P

Propagate (P) = A
+
B
Note that we will be sometimes using an alternate definition for
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
The Ripple-Carry Adder
The Ripple-Carry Adder
Worst case delay linear with the number of bits
Goal: Make the fastest possible carry path circuit
FA FA FA FA
A
0
B
0
S
0
A
1
B
1
S
1
A

2
B
2
S
2
A
3
B
3
S
3
C
i,0
C
o,0
(= C
i,1
)
C
o,1
C
o,2
t
d
= O(N)
t
adder
= (N-1)t
carry
+ t

sum
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Complimentary Static CMOS Full Adder
Complimentary Static CMOS Full Adder
28 Transistors
A B
B
A
C
i
C
i
A
X
V
DD
V
DD
A B
C
i
BA
B
V
DD
A

B
C
i
C
i
A
B
A C
i
B
C
o
V
DD
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Inversion Property
Inversion Property
A B
S
C
o
C
i
FA
A B
S

C
o
C
i
FA
S A B C
i
, ,( )
S A B C
i
, ,( )
=
C
o
A B C
i
, ,( )
C
o
A B C
i
, ,( )
=
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Minimize Critical Path by Reducing Inverting Stages
Minimize Critical Path by Reducing Inverting Stages

Exploit Inversion Property
A
3
FA FA FA
Even cell Odd cell
FA
A
0
B
0
S
0
A
1
B
1
S
1
A
2
B
2
S
2
B
3
S
3
C
i,0

C
o,0
C
o,1
C
o,3
C
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
A Better Structure: The Mirror Adder
A Better Structure: The Mirror Adder
V
DD
C
i
A
B
BA
B
A
A
B
Kill
Generate
"1"-Propagate
"0"-Propagate
V

DD
C
i
A B
C
i
C
i
B
A
C
i
A
B
B
A
V
DD
S
C
o
24 transistors
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Mirror Adder
Mirror Adder
Stick Diagram

C
i
A B
V
DD
GND
B
C
o
A C
i
C
o
C
i
A B
S
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
The Mirror Adder
The Mirror Adder
•
The NMOS and PMOS chains are completely symmetrical.
A maximum of two series transistors can be observed in the carry-
generation circuitry.
•
When laying out the cell, the most critical issue is the

minimization of the capacitance at node C
o
. The reduction of the
diffusion capacitances is particularly important.
•
The capacitance at node C
o
is composed of four diffusion
capacitances, two internal gate capacitances, and six gate
capacitances in the connecting adder cell .
•
The transistors connected to C
i
are placed closest to the output.
•
Only the transistors in the carry stage have to be optimized for
optimal speed. All transistors in the sum stage can be minimal
size.
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Transmission Gate Full Adder
Transmission Gate Full Adder
A
B
P
C
i

V
DD
A
A
A
V
DD
C
i
A
P
A
B
V
DD
V
DD
C
i
C
i
C
o
S
C
i
P
P
P
P

P
Sum Generation
Carry Generation
Setup
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Manchester Carry Chain
Manchester Carry Chain
C
o
C
i
G
i
D
i
P
i
P
i
V
DD
C
o
C
i
G

i
P
i
V
DD
φ
φ
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Manchester Carry Chain
Manchester Carry Chain
G
2
φ
C
3
G
3
C
i,0
P
0
G
1
V
DD
φ

G
0
P
1
P
2
P
3
C
3
C
2
C
1
C
0
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Manchester Carry Chain
Manchester Carry Chain
P
i + 1
G
i + 1
φ
C
i

Inverter/Sum Row
Propagate/Generate Row
P
i
G
i
φ
C
i - 1
C
i + 1
V
DD
GND
Stick Diagram
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Carry-Bypass Adder
Carry-Bypass Adder
FA FA FA FA
P
0
G
1
P
0
G

1
P
2
G
2
P
3
G
3
C
o,3
C
o,2
C
o,1
C
o,0
C
i,0
FA FA FA FA
P
0
G
1
P
0
G
1
P
2

G
2
P
3
G
3
C
o,2
C
o,1
C
o,0
C
i,0
C
o,3
Multiplexer
BP=P
o
P
1
P
2
P
3
Idea: If (P0 and P1 and P2 and P3 = 1)
then C
o3
= C
0

, else “kill” or “generate”.
Also called
Carry-Skip
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Carry-Bypass Adder (cont.)
Carry-Bypass Adder (cont.)
Carry
propagation
Setup
Bit 0–3
Sum
M bits
t
setup
t
sum
Carry
propagation
Setup
Bit 4–7
Sum
t
bypass
Carry
propagation
Setup

Bit 8–11
Sum
Carry
propagation
Setup
Bit 12–15
Sum
t
adder
= t
setup
+ M
tcarry
+ (N/M-1)t
bypass
+ (M-1)t
carry
+ t
sum
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© Digital Integrated Circuits
2nd
Arithmetic Circuits
Carry Ripple versus Carry Bypass
Carry Ripple versus Carry Bypass
N
t
p
ripple adder

bypass adder
4..8