Tài liệu Microprocessor System Design pdf

University of Technology 1
Microprocessor System Design
BÙI QUỐC BẢO
()
University of Technology 2
Outline
•
Address decoding
•
Chip select
•
Memory configurations
University of Technology 3
MEMORY INTERFACE
When Memory is selected?
MEMORY
D7 - D0
A19 - A0
RD
WR
Simplified
Drawing of
8088 Minimum
Mode
D7 - D0
A19 - A0
MEMR
MEMW
cs
University of Technology 4
Minimum Mode

MEMORY
D7 - D0
A19 - A0
RD
WR
Simplified
Drawing of
8088 Minimum
Mode
D7 - D0
A19 - A0
MEMR
MEMW
CS
2
20
bytes or 1MB
University of Technology 5
What are the memory locations of a
1MB (2
20
bytes) Memory?
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111

5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
00000 0000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
Example: 34FD0

0011 0100 11111 1101 0000
University of Technology 6
Interfacing a 1MB Memory to the 8088 Microprocessor
2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
:
:
45

98
27
39
42
88
07
F4
8A
:
:
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
:
:
:
:
:
:

:
:
A19
A0
:
D7
D0
:
RD
WR
A19
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000

0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
CS
University of Technology 7
Instead of Interfacing 1MB, what will happen if
you interface a 512KB Memory?
University of Technology 8
What are the memory locations of a
512KB (2
19
bytes) Memory?
A18 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432

AAAA
1198
1000
AAAA
7654
AAAA
3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
University of Technology 9
Interfacing a 512KB Memory to the 8088 Microprocessor
A18
A0
:
D7
D0
:
MEMR
MEMWXXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000

0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
2300000
00001 95
:
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36

:
:
:
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
A19
What do we do with A19?
University of Technology 10
What if you want to read physical address A0023?
A18
A0
:
D7
D0
:
MEMR
MEMWXXXX
BP
ES
DS

SS
CX
BX
AX
XXXX
XXXX
XXXX
A000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
2300000
00001 95
:
:
20020
20021
20022
20023
7FFFD
7FFFE

7FFFF
29
12
7D
13
19
25
36
:
:
:
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
A19
University of Technology 11
What if you want to read physical
address A0023?
A19 to
A0
(HEX)

AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
A0023 1010 0000 0000 0010 0011
A19 is not connected to the memory so
even if the 8088 microprocessor
outputs a logic “1”, the memory
cannot “see” this.
University of Technology 12
What if you want to read physical
address 20023?
A18 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432

AAAA
1198
1000
AAAA
7654
AAAA
3210
20023 0010 0000 0000 0010 0011
For memory it is the same as previous
one.
University of Technology 13
Interfacing two 512KB Memory to the 8088 Microprocessor
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX

XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19
2300000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19

25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
9700000
00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98

12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
University of Technology 14
Interfacing two 512KB Memory to the 8088 Microprocessor
•
Problem: đụng độ bus (bus conflict). Hai RAM sẽ xuất
dữ liệu cùng lúc khi VXL thực hiện lệnh đọc bộ nhớ
•
Solution: dùng A19 làm bộ phân xử bus (bus arbiter),
trong trường hợp này có thể gọi là bộ giải mã địa chỉ
(address decoder).
•
Khi A19 = 0, bộ nhớ thấp hơn được cho phép, bộ nhớ
cao bị cấm. Tương tự khi A19 = 1.
University of Technology 15
Interfacing two 512KB Memory to the 8088 Microprocessor
A18
A0
:

D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19

2300000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
9700000

00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
University of Technology 16
What are the memory locations of two

consecutive 512KB (2
19
bytes) Memory?
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
University of Technology 17
A18
A0
:
D7
D0
:

MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19
2300000
00001 95
:

20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
9700000
00001 D4
:
20020

20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
Interfacing two 512KB Memory to the 8088 Microprocessor
When the µP outputs
an address between
80000 to FFFFF,
this memory is

selected
When the µP outputs
an address between
00000 to 7FFFF,
this memory is
selected
University of Technology 18
Interfacing two 512KB Memory to the 8088 Microprocessor
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023

3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19
2300000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:

:
A18
A0
:
D7
D0
:
RD
WR
CS
9700000
00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:

A18
A0
:
D7
D0
:
RD
WR
CS
University of Technology 19
Interfacing two 512KB Memory to the 8088 Microprocessor
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX

2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19
2300000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25

36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
9700000
00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12

:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
A18
A0
:
D7
D0
:
RD
WR
A19
University of Technology 20
A18
A0
:
D7
D0
:
MEMR
MEMW

XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19
2300000
00001 95
:
20020
20021

20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
9700000
00001 D4
:
20020
20021
20022

20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
What if we remove the lower memory?
University of Technology 21
What if we remove the lower memory?
A18
A0
:
D7

D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19
2300000

00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
When the µP outputs
an address between

80000 to FFFFF,
this memory is
selected
When the µP outputs
an address between
00000 to 7FFFF, no
memory chip is
selected
!
University of Technology 22
Full and Partial Decoding
•
Full Decoding
–
When all of the “useful” address lines are connected the
memory/device to perform selection
•
Partial Decoding
–
When some of the “useful” address lines are connected
the memory/device to perform selection
–
Using this type of decoding results into roll-over
addresses
University of Technology 23
Full Decoding
A18
A0
:
D7

D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19
2300000

00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
University of Technology 24
Full Decoding

A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
A19 should be a logic “1” for the
memory chip to be enabled
University of Technology 25
Full Decoding
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111

5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
Therefore if the microprocessor
outputs an address between 00000 to
7FFFF, whose A19 is a logic “0”, the
memory chip will not be selected