Advanced Computer Architecture - Lecture 5: Instruction set principles (Cont''d)

CS 704
Advanced Computer Architecture

Lecture 5
Instruction Set Principles
(Encoding instructions and MIPS Instruction format)

Prof. Dr. M. Ashraf Chughtai
MAC/VU-Advanced Computer ArchitectureLecture 5 - Instruction Set Principles .. Cont'd

1


Today’s Topics
Recap Lecture 4
Instruction Set Encoding
MIPS Instruction Set
Summary

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Architecture
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Lecture
5 - Instruction Set Principles


Recap: Lecture 4
Three pillars of Computer Architecture
Hardware, Software and Instruction Set
Instruction Set
Interface between hardware and software

Taxonomy of Instruction Set:
Stack, Accumulator and General Purpose Register
Types and Size of Operands:
Types: Integer, FP and Character
Size: Half word, word, double word
Classification of operations
Arithmetic, data transfer, control and support
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5 - Instruction Set Principles


Recap

… Cont’d

Operand Addressing Modes
Immediate, register, direct (absolute) and
Indirect
Classification of Indirect Addressing
Register, indexed, relative (i.e. with
displacement) and
memory
Special Addressing Modes
Auto-increment, auto-decrement and scaled
Control Instruction Addressing modes
Branch, jump and procedure call/return
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Architecture
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Lecture
5 - Instruction Set Principles


Instruction set Encoding
Essential elements of computer instructions
1. Type of the operation to be performed
– This information is encoded in the “operation
code”, or the op-code, field of the machine
language instruction
– Examples: add, mov etc.

2. Place to find the source operand (s)
Possible locations are: CPU registers, memory
cells, I/O locations, part of the instruction itself
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5 - Instruction Set Principles


Computer Instructions Encoding
3. Place to store the results
Possible locations are:
CPU registers, memory cells and I/O locations

4. Place to find the next instruction from

– Address of the next instruction in sequence
(this is the default case)
– Address of the instruction at the branch target
location
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Architecture
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5 - Instruction Set Principles


Instruction Word Types
Variable Length
-

Operation is specified in one field, Op-code
Can support any number of operands
Each address specifier determines the addressing
mode and length of the specifier for the operand
Generally, it generates the smallest code
representation as unused fields need not be included
Typical Examples: VAX, Intel 80x86
Operation and
Address
number of
Specifier # 1
operands

Address
field # 1

Address
Specifier #n

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5 - Instruction Set Principles

Address
Field # n


Variable length Encoding .. Cont’d
Operation and
Address
number of
Specifier # 1
operands

Address
field # 1

Address
Specifier #n

Address
Field # n

-

The decision regarding the length depends upon the
range of addressing modes and degree of
independence between op-code and mode
-

For example: immediate addressing requires one or
two address field whereas indexed addressing requires
3 or 4 fields
The length of Intel 80x86 varies between 1 byte and 17
byte and is generally smaller than RICS architecture
which uses fixed length format

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5 - Instruction Set Principles


Fixed Length Format
-

Always has same number of operands
Addressing modes (if option exist) is specified
in Op-code
It generally generates the largest code size
Fields may be used for different purposes, if
necessary

Typical Examples: Alpha, MIPS, PowerPC, SPARC
Operation
code

Address
field # 1

Address
field # 2

Address
field # 3

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Architecture
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5 - Instruction Set Principles


Third Alternative: Hybrid Length
Multiple formats are specified by the op-code
One or two fields are added to specify addressing
mode
Similarly, one or two fields specify operand address
It generally generates the optimum code size
Typical Examples: IBM 360/370, MIPS16, TI-TMS320c54x
Operation
code

Address
specifier

Address
field

Operation
code

Address
Specifier # 1

Address
Specifier # 2

Address
field

Operation
code

Address
specifier

Address
field # 1

Address
field # 2

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Lecture
5 - Instruction Set Principles


Hybrid Length Taxonomy
Based on number of Address Fields
4-address instructions
Specifies the two source operands, the destination operand and
the address of the next instruction
op code

destination

source 1

source 2

next address

3-address instructions
Specifies addresses for both operands as well as the result
op code

destination

source 1

source 2

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5 - Instruction Set Principles


Hybrid Length Taxonomy .. Cont’d
2-address instructions
- Overwrites one operand with the result
- One field serves two purposes
op code

destination
source 1

source 2

1-address instructions
dedicated CPU register, accumulator, to hold one operand and the
result – the address of other operand is specified
op code

source 2

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Lecture
5 - Instruction Set Principles


Hybrid Length Taxonomy .. Cont’d
0-address instructions
- Uses a stack to hold both operands and
the result
- Operations are performed between the
value on the top of the stack (TOS) and
the second value on the stack (SOS) and
the result is stored on the TOS
op code

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Example
Evaluate the expression: F = (B + C)*D – E
using 0- address through 3-address format
0-Address
PUSH B
PUSH C
ADD
PUSH D

MUL
PUSH E
SUB
POP F
Number of
Instructions:

8

1-Address
LDA B
ADD C
MUL D
SUB E
STA F

5

2-Address
LOAD F, B
ADD F, C
MUL F, D
SUB F, E

4

3-Address
ADD F, B, C
MUL F, F, D
SUB F, F, E

3

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5 - Instruction Set Principles


Another example: 

Using different instruction formats, write pseudo­code to evaluate the following 
expression:  Z = 4(A+B) – 16(C+58) : Your code should not change the source operands

3­Address
ADD
MUL
ADD
MUL
SUB

x, A, B
y, x, 4
r, C, 58
s, r, 16
Z, y, s

2­Address
LOAD

MUL
LOAD
ADD
MUL
SUB
STORE

y, B
y, 4
s, C
s, 58
s, 16
y, s
Z, y

1­Address
; order changed to
reduce code size

LDA
ADDA
MULA
STA
LDA
ADDA
MULA
SUBA
STA

C

58
16
S
A
B
4
s
Z

0­Address
PUSH
PUSH
ADD
PUSH
MUL
PUSH
PUSH
ADD
PUSH
MUL
SUB
POP

C
58
16
A
B
4

Z

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Comparison of instruction formats
Assume that
A single byte is used for the op code
The size of the memory address space is 16 Mbytes
A single addressable memory unit is a byte
Size of operands is 24 bits
Data bus size is 8 bits
Use the following two parameters and compare the
five instruction formats (O-4 address) mentioned
earlier
- Code size: Its effect on the storage requirements
- Number of memory accesses: It’s effect on execution time
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4-address instruction
op code

destination

source 1

source 2

next address

1 byte

3 bytes

3 bytes

3 bytes

3 bytes

Code size = 1+3+3+3+3 = 13 bytes
# of bytes accessed from memory
13 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total =
22 bytes
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5 - Instruction Set Principles


3-address instruction
op code

destination

source 1

source 2

1 byte

3 bytes

3 bytes

3 bytes

Code size = 1+3+3+3 = 10 bytes
# of bytes accessed from memory
10 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total =
19 bytes
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Lecture
5 - Instruction Set Principles


2-address instruction
op code

destination
source 1

source 2

1 byte

3 bytes

3 bytes

Code size = 1+3+3 = 7 bytes
# of bytes accessed from memory
7 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total =
16 bytes
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1-address instruction
op code

source 2

1 byte

3 bytes

Code size = 1+3= 4 bytes
# of bytes accessed from memory
4 bytes for instruction fetch +
3 bytes for source operand fetch +
0 bytes for storing destination operand
Total =
7 bytes
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5 - Instruction Set Principles


0-address instruction
op code

1 byte

Code size = 1 bytes
# of bytes accessed from memory
1 bytes for instruction fetch +
6 bytes for source operand fetch +
3 bytes for storing destination operand
Total = 10 bytes
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Result Summary
A single byte is used for the op code, 16 MB memory address
space, single addressable memory unit: byte, 24 bits
operands is 24 bits and 8-bit data bus

Instruction Format 

Code size  Number of memory bytes 

4­address instruction 

13 

22 

3­address instruction 

10 

19 

2­address instruction 

7 

16 

1­address instruction 

4 

7 

0­address instruction 

1 

10 

 
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5 - Instruction Set Principles

RISC and MIPS ISA
RISC and MIPS is a fixed length, 64-bit
LOAD/STORE Architecture
Contains 32 GPR each of 32-bit
Supports:
- 3-address, reg-reg arithmetic instruction
- displacement instructions with address offset
12-16 bits
- immediate data 8-bit and 16-bit and
- register indirect
- data size 8-, 16-, 32- and 64-bit integer
- 64-bit IEEE 754 floating point
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RISC and MIPS ISA

…Cont’d

Supports … cont’d
Instructions:
- Data Transfer:

load, store,
register-register move
- Simple Arithmetic: add, subtract, and shift

- Compare:
equal, not-equal, less
- Branch:
PC-relative, jump and
call/return
Designed for pipelining efficiency
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5 - Instruction Set Principles


MIPS Instruction Word format
Recap: MIPS types and size of operands

Types of an Operand
- Integer
- Single-precision floating point
- Character
Size of Operand
- Character
- Half word
- Single precision FP or Word
- Double precision FP or
double word

8-bit
16-bit
32-bit

64-bit

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5 - Instruction Set Principles