Advanced Computer Architecture - Lecture 33: Memory hierarchy design

CS 704
Advanced Computer Architecture

Lecture 33
Memory Hierarchy Design
(Virtual Memory System)

Prof. Dr. M. Ashraf Chughtai


Today’s Topics
Recap: Main memory and Virtual memory Design
Virtual Memory Address Translation
Virtual Memory Performance
Protection of multiple processes
sharing memory
Summary

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Recap: Memory Hierarchy
Main memory organization
Organized using banks of memory arrays
Dual Inline Memory Modules - DIMMs
Fast page mode

Synchronous
Double Data Rate DRAMs

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Recap: Main Memory Performance
Fast page mode
Synchronous DRAM (SDRAM)
Double Data Rate (DDR) DRAM
latency and bandwidth

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Recap: Main Memory Performance
concern of caches
bandwidth
Inputs/outputs and multiprocessors
Wider Main Memory

Simple Interleaved Memory
Independent Memory Banks

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Recap: Virtual Memory
Multiple processes
Dedicate a full address space
Virtual Memory

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Recap: Virtual Memory … Cont’d

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Recap: Virtual Memory … Cont’d
Fix-sized fragment
Variable-sized fragment
Contiguous pages in virtual memory
Physically available on the main memory

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Recap: Virtual Memory .. Cont’d
Protection and Relocation
Protection
Relocation

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Recap: Cache verses Virtual memory
Page fault or address fault
– CPU produces virtual address
– Mapping of a virtual address
–

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Recap: Cache verses Virtual memory …. Cont’d
– Replacement
– The size of processor address
– Secondary storage

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Recap: Cache verses Virtual memory …. Cont’d
– The page replacement strategies

– FIFO – First –in-First Out
– LRU – Least recently Used
– Approximation to LRU
• Bit
• Resets the reference bit
• Page with a reference bit

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Recap: Cache verses Virtual memory …. Cont’d
– VM Write strategies may be:
– Write Back
– Write Through

Write through is impossible because:
• Too long access to disk
• The write buffer
• The I/O system

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Recap: Virtual Memory operation

–
–
–
–

The CPU generates the Virtual Address
Lookup table
Location of the page or segment
Virtual addresses to physical addresses

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Recap:

Virtual Memory operation .. Cont’d

– page fault
 The OS has full control over placement
 OS exception handler is invoked

 current process suspends the data is to the
main memory by the OS
 The contents of the page table are updated

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VM Address Translation Concept
Assume that Virtual Address space V
comprises a set of N pages
V = {0, 1, …, N–1}
And, Physical Address space P comprises a
set of M pages
P = {0, 1, …, M–1}
where M < N

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VM Address Translation Concept

Assuming n-bit virtual address, m-bit
physical address and p-bit page offset, the
virtual and physical address limits and the
page size can be expressed as
– Virtual address limit

=

N

=

2n

– Physical address limit

=

M

=

2m

– page size (bytes)

=

PS =

2p

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VM Address Translation Concept
page offset
page number

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VM Address Translation Concept
n–1

p p–1
virtual page number

0
virtual address

page offset

address translation
mechanism
m–1
p p–1
physical page number
page offset

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0
physical address

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Page Table
Virtual Page
Number

Memory resident page table
(physical page or disk address)

Physical Memory

Valid
1

1
0
1
1
1
0
1
0
1

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Disk Storage (swap file or
regular file system file)

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Page Table Operation: 3 steps
1: Translation
2: Computing Physical Address

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Address Translation via Page Table
page table base register
VPN acts
as
table index

if valid=0
then page
not in memory

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virtual address
n–1
p p–1
virtual page number (VPN)
page offset

0

Page entry Table
valid access physical page number (PPN)

m–1
p p–1
physical page number (PPN)
page offset

0

physical address
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Page Table Operation
3: Checking Protection

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Simple Memory System Example
Addressing
– 14-bit virtual addresses
– 12-bit physical address
– Page size = 64 bytes
13

12

11

10

9

8

7

6

5

4

VPN

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10

2

1

0

VPO
(Virtual Page Offset)

(Virtual Page Number)
11

3

9

8

7

6

5

4

3

2

1

PPN

PPO

(Physical Page Number)

(Physical Page Offset)

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0

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Simple Memory System Page
Table

– Only show first 16 entries
VPN

PPN

Valid

VPN

PPN

Valid

00

28

1

08

13

1

01

–

0

09

17

1

02

33

1

0A

09

1

03

02

1

0B

–

0

04

–

0

0C

–

0

05

16

1

0D

2D

1

06

–

0

0E

11

1

07

–

0

0F

0D

1

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