Advanced Computer Architecture - Lecture 39: Input/Output systems

CS 704
Advanced Computer Architecture

Lecture 39
Input Output Systems
(Bus Structures Connecting I/O Devices)

Prof. Dr. M. Ashraf Chughtai
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Today’s Topics
Recap:
I/O interconnect Trends
Bus-based Interconnect
Bus Standards

Conclusion

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Recap: I/O System
Last time we noticed that the overall
performance of a computer is measured by its
throughput, which is very much influenced by
the systems external to the processor
The effect of neglecting the I/Os on the overall
performance of a computer system can best be
visualized by Amdahl's Law which identifies
that: system speed-up limited by the slowest
part!
– We noticed that an I/O system comprises

storage I/Os and Communication I/Os
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Recap:

I/O Systems

The Storage I/Os consist of Secondary and
Tertiary Storage Devices; and
The communication I/O consists of I/O Bus system
which interconnect the microprocessor and

memory with the I/O devices

The development in processing effected the
storage industry and motivated to develop:
– the smaller, cheaper, more reliable and lower
power embedded storages for ubiquitous
computing; and …..
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Recap:

I/O Systems

– high capacity, hierarchically managed
storages as data utilities
We noticed that diversity, capacity, latency and
bandwidth are the most important parameters
of I/O performance measurement
I/O system works on the principle of producerserver model, which comprises an area called
queue, wherein the tasks accumulate while waiting
to be serviced
The metrics of disk I/O performance are:
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Recap:

I/O Systems

– Response Time, which is the time to Queue +
Device Service time; and
– Throughput, which is the percent of the total
bandwidth

Example:
Comparing the performance of different
I/Os
Assume the following parameters, and compare
the time to read and write a 64Kbyte block to flash
memory and disk
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I/O Performance Measurement: Example

─ Flash memory takes:
─ 65 ns to read 1 byte
─ 1.5 µsec. to write 1 byte and
─ 5 msec. to erase 4KB
─ Disk Storage has:
─ Average seek time = 4.0 msec.
─ Average rotational delay = 8.3 msec.
─ Transfer time = 4.2 MB/sec;
─ Controller overhead = 0.1 msec.

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I/O Performance Measurement: Example
─ Average read or write time for disk is same and
is calculated as:
=
Average seek time + Average rotational delay +
=

Transfer time + Controller overhead
4.0 ms+ 8.3 ms + 64KB/4.2 MB/sec + 0.1 ms

=

27.3 msec.

─ Read time for flash is the ratio of the flash

size to the read bandwidth:
= 64KB/1B/65ns = 4.3 ms
─ Flash is about 6 times faster than the disk for

reading 64KB
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I/O Performance Measurement: Example
─ Write time for flash is sum of the erase time and

the ratio of the flash size to the write bandwidth:
= (64KB/4KB/5ms) + (64KB/1B/1.5µs)
= 178.3 ms
The disk is about 6 times faster than the flash
for writing 64KB

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Interconnect Trends
The I/O interconnect is the glue that interfaces
computer system components
I/O interconnects are facilitated using High
speed hardware interfaces and logical
protocols
Based on the desired communication distance,
bandwidth, latency and reliability,
interconnects are classified as used:
Backplanes, channels, Networks
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Interconnect Trends .. Cont’d
Distance

Network

Channel

Backplane

>1000 m

10 - 100 m

1m

Bandwidth 10 - 100 Mb/s
Latency
Reliability

40 - 1000 Mb/s 320 - 1000+ Mb/s

high (>ms)

medium

low (<µs)

low
Extensive CRC

medium
Byte Parity

high
Byte Parity

message-based
narrow pathways

distributed
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memory-mapped
wide pathways
centralized
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Bus-Based Interconnect
Communication on different interconnects is
done via buses
Bus is a shared communication link between
subsystems

The advantages of using buses are:
– Low cost: a single set of wires is shared
multiple ways
– Versatility: Easy to add new devices &
peripherals may even be ported between
computers using common bus
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Bus-Based Interconnect
Disadvantage
– The major disadvantage of a bus is that it
creates a communication bottleneck,
possibly limiting the maximum I/O
throughput
– In server systems, where I/O is frequent,
design a bus-system capable of meeting
the demand of the processor is a real
challenge
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Bus-Based Interconnect
Bus speed is limited by physical factors,
such as:
– the bus length
– the bus loading, i.e., number of devices
connected to a bus
these physical limits prevent arbitrary bus
speedup, which make the bus design
difficult
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Bus-Based Interconnect
Buses are classified into Two generic types as:
– I/O busses: are lengthy, facilitate to connect
many types of devices, offer wide range in
the data bandwidth, and follow a bus
standard

(I/O bus is sometimes called a channel)
– CPU–memory buses: high speed, matched to
the memory system to maximize memory –
CPU bandwidth, single device (sometimes
called a backplane)

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Bus Transactions
Bus transactions are usually defined with

reference to the memory, i.e., what they do with
memory – memory read or memory write
Bus transaction includes two parts: Sending
the address and Receiving the data
Read Transaction:
Address is first sent down the bus to the
memory together with asserting the read
signal; and ….
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Bus Transactions
The memory responds by sending the
data and de-asserting the wait signal
Write Transaction:
– Address and data are sent down the bus

to the memory together with asserting the
write signal
– The memory stores the data and de-

asserting the wait signal
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Bus Transition Protocols
Bus transition or bus Communication
Protocols specify the sequence of events and
timing requirements in transferring information
Synchronous Bus Transfers: follows a
sequence of operations relative to a common
clock
Asynchronous Bus Transfers is not clocked
and uses control lines (req., ack.) which
provide handshaking among the devices
having bus transition
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Synchronous Bus Protocols
Clock
Address
Data
Read
Wait

begin read

The address transmitted in the 1st clock, using
control lines to indicate the type of request; the
read begins when NOT READ is asserted
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Synchronous Bus Protocols
Clock
Address
Data

Read

Read complete

Wait
begin read

The data are not ready until the wait signal is
reasserted
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Asynchronous Handshake
The asynchronous bus is not clocked, rather it is
self timed
Hand shaking protocols are used between the bus
sender and receiver
Write Transaction
Address

Master Asserts Address

Data

Master Asserts Data

Next Address

Read
Req.

4 Cycle Handshake

Ack.
t0
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t1

t2

t3

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t4

t5
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Asynchronous Handshake
t0 : Master has obtained control and asserts
address, direction, data; Waits a
specified amount of time for slaves to
decode target
t1: Master asserts request line
t2: Slave asserts ack, indicating data
received
t3: Master releases req
t4: Slave releases ack
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Read Transaction
Address

Master Asserts Address

Next Address

Data
Read
Req
Ack

4 Cycle Handshake

t0
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t1

t2

t3

t4

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t5
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Read Transaction
t0 : Master has obtained control and asserts
address, direction, data; Waits a
specified amount of time for slaves to
decode target\
t1: Master asserts request line
t2: Slave asserts ack, indicating ready to
transmit data
t3: Master releases req, data received
t4: Slave releases ack
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Bus Arbitration Protocols
Having understood the bus transactions, the
most important is to understand how is a bus
reserved by a device that wishes to
communicates when multiple devices need the
bus access?
This is accomplished by introducing one or

more bus masters into the system
A Bus Master has ability to control the bus
requests and initiate a bus transaction
Bus Slave is module activated by the master for
transaction
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