Advanced Computer Architecture - Lecture 45: Putting it all together

CS 704
Advanced Computer Architecture

Lecture 45
Putting It All Together
(Review: Lecture 1 - 43)

Prof. Dr. M. Ashraf Chughtai


Today’s Topics
 Module 1: Introduction
 Module 2: Instruction Set Architecture
 Module 3: Computer hardware design
 Module 4: Instruction Level Parallelism –Dynamic
 Module 5: Instruction Level Parallelism – Static
 Module 6: Memory Hierarchy system
 Module 7: Multiprocessing
 Module 8: I/O Systems
 Module 9: Networks and Clusters
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Module 1:
Introduction and Quantitative Principles
We started this course distinguishing the

computer organization and computer
architecture
Architecture refers to those attributes of a
computer visible to the programmer or
compiler writer; e.g.,
instruction set, memory addressing
techniques, I/O mechanisms etc.
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Module 1:
Introduction
Organization refers to how the features of a
computer are implemented; e.g.,
control signals are generated using the
principles of FSM or microprogramming
The architecture of the members of a
processor family are same whereas
organization of same architecture may differ
between different members of the family
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Module 1: Introduction ….
Computer Development
We also introduced the computers
developments with academic and commercial
perspectives
Academically, modern computer
developments have their infancy in 1944-49,
when John von Neumann introduced the
concept of stored-program computer, referred
to as Electronic Discrete Variable Automatic
Computer – EDVAC
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Module 1: Introduction ….
Computer Development
Commercially, the first machine was built by
Eckert-Mauchly Computer Corporation in 1949
In 1971, Intel introduced first cheep
microprocessor 4004 and then 80 x 86 series
In 1998, more than 350 million microprocessors
with different instruction set architectures were

in use; this number has risen to more than a
billion in 2006
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Module 1: Introduction ….
Computer Generations
Technological developments, from vacuum
tubes to VLSI circuits, dynamic memory and
network technology gave birth to four different
generations of computers






This course has viewed the Computer
Architecture from four perspectives
Processor Design
Memory Hierarchy
Input/output and storages
Multiprocessor and Network interconnection
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Module 1: Quantitative Principles
The key to the quantitative analysis in
determining the effectiveness of the entire
computing system is the computer hardware
and software performance
In this respect , we discussed:
 Price-performance design
 CPU performance metrics
 CPU benchmark suites

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Module 1: Price-Performance Design
The issue of cost-performance is complex one
At one extreme, high-performance computers
designer may not give importance to the cost
in achieving the performance goal.
At the other end, low-cost designer may

sacrifice performance to some extent.
The price-performance design lies between
these extremes where the designer balances
cost and hence price verses performance.
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Module1: CPU Benchmark Suites
In order to compare the performance of two
machines, a user can simply compare the
execution time of the same workload running
on both the machines.
In practice users want to know, without
running their own programs, that how well the
machine will perform on their workload.
This is accomplished by evaluating the
machine using a set of benchmarks – the
programs specifically chosen to measure the
performance.
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Module1: CPU Benchmark Suites
1.
2.

3.
4.
5.

Five levels of programs are used as benchmarks:
Real Applications – scientific programs evaluate
the performance of a machine
Modified Applications – the real applications with
certain blocks modified to focus desired aspects
of application,
Kernels – the small key pieces extracted from the
real program
Toy benchmarks – small codes normally used as
beginning programming assignments.
Synthetic benchmarks – the small section of
Artificially created program
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Module1: Quantitative Principles of
Performance Measurement
Quantitatively the performance of a system can
be enhanced by speedup of a fraction of
system based on the concept of the common
case first
Amdahl’s Law is the basis of the measure of
the performance enhancement
which defines the Speedup due to enhancement
E that accelerates a fraction F of the task as:
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Module 1: Amdahl's Law
Ex Time without Enhancement

Speedup (E) =
Ex Time with Enhancement

Performance with Enhancement

=
Performance without Enhancement
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Module 2:
Instruction Set Architecture
The three pillars of computer architecture are:
 hardware,
 instruction set
 software

Hardware facilitates to run the software and
instruction set is the interface between the
hardware and software
– While talking about the Instruction set

architecture the focus of our discussion has
been:
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Module 2:

Instruction Set Architecture





ISA Taxonomy
Types of operands
Types of operations
Memory Addressing modes

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Module 2: Taxonomy of Instruction Set
The taxonomy of Instruction set was defined
as:
– Stack Architecture:
– Accumulator Architecture
– General Purpose Register Architecture
 Register – memory
 Register – Register (load/store)
 Memory – Memory Architecture (Obsolete)
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Module 2: Types of Operands and
Operations
Operands Types:
Integer, FP and Character
Operand Size
Half word, word, double word
Classification of operations
Arithmetic, data transfer, control
and support operations
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Module 2: Types of Operands addressing
modes
Operand Addressing Modes
Immediate, register, direct (absolute) and
Indirect

Classification of Indirect Addressing

Register, indexed, relative (i.e. with
displacement) and memory

Special Addressing Modes
Auto-increment, auto-decrement and scaled

Control Instruction Addressing modes
Branch, jump and procedure call/return
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Module 3: Computer Hardware design
Basic building blocks of a computer
Sub-systems of CPU: Datapath and Control
Processor design steps
Processor design parameters
Hardware design process
Timing signals
Uni-bus, 2-bus and 3-bus structures
3-bus based single cycles data path
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Sub-systems of Central Processing Unit
At a “higher level” a CPU can be viewed as consisting of
two sub-systems

– Datapath:
the path that facilitates the
transfer of information from
one part (register/memory/ IO)
to the other part of the system

- Control:
the hardware that generates
signals to control the
sequence of steps and direct
the flow of information
through the datapath
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Data
Path
CONTROL
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Module 3: Datapath Implementations
The datapath is the arithmetic organ of the
Von- Neumann’s stored-program
organization
Typically, the datapath may be implemented
as:
- Unibus structure
- 2-bus structure
- 3-bus structure
Based on the concepts of single cycle,
multiple cycle and pipelined architecture
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Module 3: Datapath Implementation
It consists of registers, internal buses,
arithmetic units and shifters
Each register in the register file has:
- a load control line that enables data load to
register
- a set of tri-state buffers between its output and
the bus
- a read control line that enables its buffer and
place the register on the bus
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Module 3: Single/Multiple Cycle Approach
In the Single Cycle implementation, the cycle
time is set to accommodate the longest
instruction, the Load instruction.
In the Multiple Cycles implementation, the
cycle time is set to accomplish longest step,
the memory read/write
Consequently, the cycle time for the Single
Cycle implementation can be five times longer
than the multiple cycle implementation.
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Module 3: Pipelined Datapath
Pipelining is a fundamental concept
Where an instructions is completed in multiple
steps using distinct resources
It utilizes capabilities of the Datapath by

Starting next instruction while working on the
current one
The pipelined datapath may encounter three
types of hazards
Structural, Data and Control
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Module 3: Pipeline Hazards
Structural hazards occur when same
resource is accessed by more than one
instructions; e.g.,
One memory port or one register write port
It can be removed by using either multiple
resources or inserting stall
Stall degrades the pipeline performance
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