CMOS VLSI Design - Lecture 5: DC & Transient Response doc

Lecture 5:
DC &
Transient
Response
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 2
Outline
 Pass Transistors
 DC Response
 Logic Levels and Noise Margins
 Transient Response
 RC Delay Models
 Delay Estimation
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 3
Pass Transistors
 We have assumed source is grounded
 What if source > 0?
– e.g. pass transistor passing V
DD
 V
g
= V
DD
– If V
s
> V
DD
-V

t
, V
gs
< V
t
– Hence transistor would turn itself off
 nMOS pass transistors pull no higher than V
DD
-V
tn
– Called a degraded “1”
– Approach degraded value slowly (low I
ds
)
 pMOS pass transistors pull no lower than V
tp
 Transmission gates are needed to pass both 0 and 1
V
DD
V
DD
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 4
Pass Transistor Ckts
V
DD
V
DD
V

s
= V
DD
-V
tn
V
SS
V
s
= |V
tp
|
V
DD
V
DD
-V
tn
V
DD
-V
tn
V
DD
-V
tn
V
DD
V
DD

V
DD
V
DD
V
DD
V
DD
-V
tn
V
DD
-2V
tn
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 5
DC Response
 DC Response: V
out
vs. V
in
for a gate
 Ex: Inverter
– When V
in
= 0 -> V
out
= V
DD

– When V
in
= V
DD
-> V
out
= 0
– In between, V
out
depends on
transistor size and current
– By KCL, must settle such that
I
dsn
= |I
dsp
|
– We could solve equations
– But graphical solution gives more insight
I
dsn
I
dsp
V
out
V
DD
V
in
CMOS VLSI DesignCMOS VLSI Design

4th Ed.
5: DC and Transient Response 6
Transistor Operation
 Current depends on region of transistor behavior
 For what V
in
and V
out
are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 7
nMOS Operation
Cutoff Linear Saturated
V
gsn
< V
tn
V
in
< V
tn
V
gsn
> V
tn
V

in
> V
tn
V
dsn
< V
gsn
– V
tn
V
out
< V
in
- V
tn
V
gsn
> V
tn
V
in
> V
tn
V
dsn
> V
gsn
– V
tn
V

out
> V
in
- V
tn
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsn
= V
in
V
dsn
= V
out
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 8
pMOS Operation
Cutoff Linear Saturated
V
gsp

> V
tp
V
in
> V
DD
+ V
tp
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
> V
gsp
– V
tp
V
out
> V
in
- V
tp

V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
< V
gsp
– V
tp
V
out
< V
in
- V
tp
I
dsn
I
dsp
V
out
V
DD

V
in
V
gsp
= V
in
- V
DD
V
dsp
= V
out
- V
DD
V
tp
< 0
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 9
I-V Characteristics
 Make pMOS is wider than nMOS such that β
n
= β
p
V
gsn5
V
gsn4
V

gsn3
V
gsn2
V
gsn1
V
gsp5
V
gsp4
V
gsp3
V
gsp2
V
gsp1
V
DD
-V
DD
V
dsn
-V
dsp
-I
dsp
I
dsn
0
CMOS VLSI DesignCMOS VLSI Design
4th Ed.

5: DC and Transient Response 10
Current vs. V
out
, V
in
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|

V
out
V
DD
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 11
Load Line Analysis
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn

, |I
dsp
|
V
out
V
DD
 For a given V
in
:
– Plot I
dsn
, I
dsp
vs. V
out
– V
out
must be where |currents| are equal in
I
dsn
I
dsp
V
out
V
DD
V
in
CMOS VLSI DesignCMOS VLSI Design

4th Ed.
5: DC and Transient Response 12
Load Line Analysis
 V
in
= 0
V
in0
V
in0
I
dsn
, |I
dsp
|
V
out
V
DD
V
in1
V
in1
I
dsn
, |I
dsp
|
V
out

V
DD
V
in2
V
in2
I
dsn
, |I
dsp
|
V
out
V
DD
V
in3
V
in3
I
dsn
, |I
dsp
|
V
out
V
DD
V
in4

V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
V
in5
I
dsn
, |I
dsp
|
V
out
V
DD
V
in5
V
in4
V
in3
V
in2

V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
V
out
V
DD
 V
in
= 00.2V
DD
0.4V
DD
0.6V
DD
0.8V
DD
V
DD
CMOS VLSI DesignCMOS VLSI Design
4th Ed.

5: DC and Transient Response 13
DC Transfer Curve
 Transcribe points onto V
in
vs. V
out
plot
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
V
out
V

DD
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
V
in0
V
in1
V
in2
V
in3

V
in4
V
in5
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 14
Operating Regions
 Revisit transistor operating regions
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp

Region nMOS pMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
V
out
V
DD
V
in
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 15
Beta Ratio
 If β
p
/ β
n
≠ 1, switching point will move from V
DD
/2
 Called skewed gate
 Other gates: collapse into equivalent inverter
V
out
0
V
in

V
DD
V
DD
0.5
1
2
10
p
n
β
β
=
0.1
p
n
β
β
=
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 16
Noise Margins
 How much noise can a gate input see before it does
not recognize the input?
Indeterminate
Region
NM
L
NM

H
Input CharacteristicsOutput Characteristics
V
OH
V
DD
V
OL
GND
V
IH
V
IL
Logical High
Input Range
Logical Low
Input Range
Logical High
Output Range
Logical Low
Output Range
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 17
V
DD
V
in
V
out

V
OH
V
DD
V
OL
V
IL
V
IH
V
tn
Unity Gain Points
Slope = -1
V
DD
-
|V
tp
|
β
p
/β
n
> 1
V
in
V
out
0

Logic Levels
 To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic
V
DD
V
in
V
out
V
DD
β
p
/β
n
> 1
V
in
V
out
0
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 18
Transient Response
 DC analysis tells us V
out
if V
in
is constant

 Transient analysis tells us V
out
(t) if V
in
(t) changes
– Requires solving differential equations
 Input is usually considered to be a step or ramp
– From 0 to V
DD
or vice versa
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 19
Inverter Step Response
 Ex: find step response of inverter driving load cap
0
0
()
()
()
(
(
)
)
DD
DD
loa
d
ou
i

d
t
o
n
ut sn
V
V
ut t V
tt
Vt
V
d
dt C
t
It
= −
=
= −
<
( )
0
2
2
0
2
)
)
(
()
(

DD DD t
DD
out
out
out out
Dt
n
t
ds
D
I V
tt
VV VV
VV VVV
t
Vt
Vt
β
β

≤


= − >−



−− < −





V
out
(t)
V
in
(t)
t
0
t
V
in
(t)
V
out
(t)
C
load
I
dsn
(t)
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 20
Delay Definitions
 t
pdr
: rising propagation delay
– From input to rising output

crossing V
DD
/2
 t
pdf
: falling propagation delay
– From input to falling output
crossing V
DD
/2
 t
pd
: average propagation delay
– t
pd
= (t
pdr
+ t
pdf
)/2
 t
r
: rise time
– From output crossing 0.2
V
DD
to 0.8 V
DD
 t
f

: fall time
– From output crossing 0.8
V
DD
to 0.2 V
DD
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 21
Delay Definitions
 t
cdr
: rising contamination delay
– From input to rising output crossing V
DD
/2
 t
cdf
: falling contamination delay
– From input to falling output crossing V
DD
/2
 t
cd
: average contamination delay
– t
pd
= (t
cdr
+ t

cdf
)/2
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 22
Simulated Inverter Delay
 Solving differential equations by hand is too hard
 SPICE simulator solves the equations numerically
– Uses more accurate I-V models too!
 But simulations take time to write, may hide insight
(V)
0.0
0.5
1.0
1.5
2.0
t(s)
0.0 200p 400p 600p 800p 1n
t
pdf
= 66ps t
pdr
= 83ps
V
in
V
out
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 23

Delay Estimation
 We would like to be able to easily estimate delay
– Not as accurate as simulation
– But easier to ask “What if?”
 The step response usually looks like a 1
st
order RC
response with a decaying exponential.
 Use RC delay models to estimate delay
– C = total capacitance on output node
– Use effective resistance R
– So that t
pd
= RC
 Characterize transistors by finding their effective R
– Depends on average current as gate switches
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 24
Effective Resistance
 Shockley models have limited value
– Not accurate enough for modern transistors
– Too complicated for much hand analysis
 Simplification: treat transistor as resistor
– Replace I
ds
(V
ds
, V
gs

) with effective resistance R
• I
ds
= V
ds
/R
– R averaged across switching of digital gate
 Too inaccurate to predict current at any given time
– But good enough to predict RC delay
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
5: DC and Transient Response 25
RC Delay Model
 Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
 Capacitance proportional to width
 Resistance inversely proportional to width
k
g
s
d
g
s
d
kC
kC
kC
R/k

k
g
s
d
g
s
d
kC
kC
kC
2R/k