ASP v8 0 midrange family periphral

© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 1201ASP v8.0 January 2007
201ASP
Mid-Range Family Peripheral
Configuration and Assembly
Programming
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 2201ASP
Objectives
z At the end of this class you will:
– Understand the basic PICmicro peripherals
and their associated registers
– Have “HANDS ON” experience initializing
Mid-Range peripherals
– Be able to implement peripherals not
covered here
– Understand interrupts and polling
– Write your own application code from
“scratch”
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 3201ASP
To get the most from this Class
z Ideally you should be familiar with the
following:
– Assembler programming
– Basic Mid-Range family Instruction set
– Data and Program memory organization
– MPLAB Integrated Development Environment
– Microchip ICD2 debugger
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 4201ASP
201ASP Agenda
z Brief review of Mid-Range Architecture,
Instruction Set and Tools
z Interrupts on the Mid-Range PICmicro

– Interrupts Lab
z Peripheral discussion:
– Input/Output Ports
– Timers
z Timer0
z Timer1
– Timer1 Lab
z Timer2
– Timer2 Lab
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 5201ASP
201ASP Agenda (cont.)
z Capture / Compare / PWM Module (CCP)
– PWM and Output Compare Labs
z Analog Comparator
z Analog to Digital Converters (ADC)
– ADC Lab
z Addressable Universal Asynchronous &
Synchronous Receiver & Transmitter (AUSART)
z I
2
C with the Master Synchronous Serial Port
– I
2
C Based Temp Sensor Lab
z Wrap-Up and additional questions
© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 6201ASP v8.0 January 2007
Mid-Range Family Basic
Architecture and
Development Tools
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 7201ASP

Mid-Range PIC Block Diagram
ADC
TIMER0
MUX
ALU
AUSART
MSSP
PERIPHERALS
WORKING
REGISTER
STATUS REGISTER
Pages of
Program
Memory
Banks of Data Memory
INSTRUCTION REGISTER
8-bit value from instruction
14-bits
PROGRAM COUNTER
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 8201ASP
Program Memory
z Maximum 8K words
– (8K x 14 bits/word)/1 byte
= 14Kbytes of memory
z Reset Vector at 0000h
– Program Counter (PC) will
go to this address on
reset
z Interrupt Vector at 0004h
– Program Counter (PC) will

go to this address upon
any Interrupt
Reset Vector
Interrupt Vector
Page 0
Page 1
Page 2
Page 3
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
17FFh
1800h
1FFFh
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 9201ASP
Program Counter (PC) and Stack
z 13-bit PC
– PCLÆ ALU result (8-bits) or
OPCODE(11-bits)
– PCHÆ Paging bits
z Updated from PCLATH
z Specifies page in program
memory
z 8 Level Deep Stack
– Stores the contents of the PC
z PUSHES

– CALL/Interrupt
z POPS
– RETURN, RETFIE,RETLW
PCLATH
PCH<12:8> PCL
Stack Level 1
Stack Level 8
Program Memory
PC<12:0>
CALL, RETURN,
RETFIE, RETLW
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 10201ASP
Data Memory Map
128
Bytes
Shared
Shared
Shared
Shared
Shared
Shared
Bank 0 Bank1 Bank2 Bank3
000h
01Fh
020h
07Fh
080h
09Fh
0A0h
0FFh

100h
110h
17Fh
180h
190h
1FFh
0EFh 16Fh
1EFh
10Fh 18Fh
Special
Function
Registers
Registers
SFR
SFR
General
Purpose
Purpose
Registers
Registers
General
General
Purpose
Purpose
Registers
Registers
Special
Function
Function
Registers

Registers
General
General
Purpose
Registers
Registers
General
Purpose
Purpose
Registers
Registers
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 11201ASP
Special Function Registers (SFRs)
06hPORTB
PORTC
07h
PORTD
08h
PORTE
09h
PCLATH
0Ah
INTCON
0Bh
PIR1
0Ch
PIR2
0Dh
86hTRISB
TRISC

87h
TRISD
88h
TRISE
89h
PCLATH
8Ah
INTCON
8Bh
PIE1
8Ch
PIE2
8Dh
Bank0 Bank1
z Register File Concept
z Accessed like any
other register
z Some registers carry
across all banks
(PCLATH, INTCON, etc.)
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 12201ASP
Status Register
z Contains:
– Arithmetic status of the
ALU
– The RESET status
– Bank select bits for data
memory
RP1 RP0
RP1 RP00 0

0 1
1 0
1 1
BANK0
BANK1
BANK2
BANK3
IRP RP1 RP0 TO PD Z DC C
Indirect Register Bank Select bit:
(used for indirect addressing)
1 = Bank 2,3
0 = Bank 0,1
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 13201ASP
PIC16 Instruction Set
z 35 single word instructions
z All are single cycle except for program branches
Byte Oriented Operations
Byte Oriented Operations
Bit Oriented Operations
Bit Oriented Operations
addwf f,d
addwf f,d
andwf f,d
andwf f,d
clrf f
clrf f
clrw -
clrw -
comf f,d
comf f,d

decf f,d
decf f,d
decfsz f,d
decfsz f,d
incf f,d
incf f,d
incfsz f,d
incfsz f,d
iorwf f,d
iorwf f,d
movf f,d
movf f,d
movwf f
movwf f
nop -
nop -
rlf f,d
rlf f,d
rrf f,d
rrf f,d
subwf f,d
subwf f,d
swapf f,d
swapf f,d
xorwf f,d
xorwf f,d
Add W and f
Add W and f
AND W with f
AND W with f

Clear f
Clear f
Clear W
Clear W
Complement f
Complement f
Decrement f
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if 0
Increment f
Increment f
Increment f, Skip if 0
Increment f, Skip if 0
Inclusive OR W with f
Inclusive OR W with f
Move f
Move f
Move W to f
Move W to f
No Operation
No Operation
Rotate Left f through Carry
Rotate Left f through Carry
Rotate Right f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract W from f
Swap nibbles in f
Swap nibbles in f

Exclusive OR W with f
Exclusive OR W with f
bcf f,b
bcf f,b
bsf f,b
bsf f,b
btfsc f,b
btfsc f,b
btfss f,b
btfss f,b
Bit Clear f
Bit Clear f
Bit Set f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Test f, Skip if Set
Literal and Control Operations
Literal and Control Operations
addlw k
addlw k
andlw k
andlw k
call k
call k
clrwdt -
clrwdt -
goto k
goto k

iorlw k
iorlw k
movlw k
movlw k
retfie -
retfie -
retlw k
retlw k
return -
return -
sleep -
sleep -
sublw k
sublw k
xorlw k
xorlw k
Add literal and W
Add literal and W
AND literal with W
AND literal with W
Call subroutine
Call subroutine
Clear Watchdog Timer
Clear Watchdog Timer
Go to address
Go to address
Inclusive OR literal with W
Inclusive OR literal with W
Move literal to W
Move literal to W

Return from interrupt
Return from interrupt
Return with literal in W
Return with literal in W
Return from Subroutine
Return from Subroutine
Go into standby mode
Go into standby mode
Subtract W from literal
Subtract W from literal
Exclusive OR literal with W
Exclusive OR literal with W
© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 14201ASP v8.0 January 2007
PICmicro Development
Tools
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 15201ASP
MPLAB
®
IDE
z
z
MPLAB
MPLAB
®
®
IDE (Integrated Development
IDE (Integrated Development
Environment)
Environment)
z

z
Integrates different Microchip and third
Integrates different Microchip and third
party tools
party tools
–
–
Code Editor
Code Editor
–
–
Cross Compilers
Cross Compilers
–
–
Assemblers
Assemblers
–
–
Simulators, In
Simulators, In
-
-
Circuit Debuggers, Emulators
Circuit Debuggers, Emulators
–
–
Programmers
Programmers
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 16201ASP

MPLAB
®
IDE
z
z
MPLAB
MPLAB
®
®
IDE (
IDE (
I
I
ntegrated
ntegrated
D
D
evelopment
evelopment
E
E
nvironment)
nvironment)
z
z
Integrates different Microchip and third
Integrates different Microchip and third
party tools
party tools
–

–
Code Editor
Code Editor
–
–
Cross Compilers
Cross Compilers
–
–
Assemblers
Assemblers
–
–
Simulators, In
Simulators, In
-
-
Circuit Debuggers, Emulators
Circuit Debuggers, Emulators
–
–
Programmers
Programmers
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 17201ASP
ICD 2 (In Circuit Debugger)
z
z
MPLAB
MPLAB
®

ICD 2 is a low cost, real
ICD 2 is a low cost, real
-
-
time
time
debugger and programmer.
debugger and programmer.
–
–
Reading/Writing memory space and
Reading/Writing memory space and
EEDATA areas of the PIC
EEDATA areas of the PIC
–
–
Programs configuration bits
Programs configuration bits
–
–
Real time debugging
Real time debugging
–
–
Erase of program memory
Erase of program memory
space with verification
space with verification
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 18201ASP
18, 28 and 40-

pin DIP sockets
9V to 5V
regulator
ICD
Connecto
r
RS232
Connector
Push button
Switches
PICDEM® 2 Plus Board
Analog Pot
LEDs
16 x 2 LCD
Module
Piezo
Buzzer
I2C Based
Temp Sensor
© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 19201ASP v8.0 January 2007
Interrupts
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 20201ASP
z Often we would like the processor to
perform a task if a specific event occurs
z Two methods to check if this event has
occurred:
– Polling:
z Continuously check for event at various points in
the code
– Interrupts:

z “INTERRUPTS” the Main program and starts an
Interrupt Service Routine when an event occurs
Polling and Interrupts
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 21201ASP
Polling
bsf PORTA,1 ;Set bit 1 of
;PORTA
btfss INTCON,TMR0IF ;Check Timer0
;interrupt flag
;in “INTCON”
;register and
;skip the next
;instruction if
;it is set
goto $-1 ;Go to
;previous
;instruction
bcf PORTA,1 ;Clear bit 0 of
;PORTA
RA<1> = 1
RA<1> = 1
TMR0IF = 1
??
TMR0IF = 1
??
RA<1> = 0
RA<1> = 0
YES
NO
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 22201ASP

Reset code 000h
goto Start
;=========================
int_vector code 004h
retfie ;return from
;interrupt
;=========================
main_prog code
Start ;start label for main
code
end
Interrupts
Main
program
execution
Main
program
execution
no interrupt
Execute ISR at
address 004h
Execute ISR at
address 004h
interrupt flag
set
retfie
instruction
Interrupt Service
Routine (ISR)
Main program

code
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 23201ASP
Enabling Interrupts
z Processor must be told that interrupts
will be used
– A number of registers with interrupt enable
bits do this:
z Interrupt Control (INTCON)
z Peripheral Interrupt Enable 1 (PIE1)
z Peripheral Interrupt Enable 2 (PIE2)
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 24201ASP
Interrupt Logic
INTE
INTF
RBIE
RBIF
TMR2IE
TMR2IF
ADIE
ADIF
PEIE
GIE
Interrupt
Other peripherals
TMR0IE
TMR0IF
© 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 25201ASP
GIE
INTCON Register
(Core Interrupts)

PEIE TMR0IE INTE RBIE TMR0IF
INTF RBIF
Flags will set
even if interrupts
aren’t enabled!
Global Interrupt EnableGIE
Peripheral Interrupt EnablePEIE
Timer0 Interrupt EnableTMRIE
External Interrupt EnableINTE
PORTB change Interrupt EnableRBIE
DescriptionEnable Bits
Timer0 Overflow Interrupt FlagTMR0IF
RB0/INT External Interrupt FlagINTF
PORTB Change Interrupt FlagRBIF
DescriptionFlag Bits
Must be set to use
any Interrupts
Must be set to use
any Peripheral
Interrupts