arithmetic and logic in computer systems

Arithmetic
and
Logic
in
Computer
Systems
This Page Intentionally Left Blank
Arithmetic
and
Logic in
Computer Systems
Mi
Lu
Texas
A&M
University
WILEY-
INTERSCIENCE
A JOHN
WILEY
&
SONS,
INC., PUBLICATION
Copyright
0
2004 by John Wiley
&
Sons, Inc. All rights reserved.
Published by John Wiley
&

Sons,
Inc., Hoboken, New Jersey.
Published simultaneously in Canada.
No
part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or
by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as
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108
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11 1
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I,
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Wiley
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however, may not be available in electronic format.
Library
of
Congress Cataloging-in-Publication Data
is
available.
ISBN

0-471-46945-9
Printed in the United States of America.
I0987654321
To
the memory of my mother, Shu Sheng Fan.
To
my father, Chong
Pu
Lu,
my
husband, Jiming Yin, and my son, Luke Yin.
This Page Intentionally Left Blank
Preface
List of Figures
List
of
Tables
About the Author
1
Computer Number Systems
Contents
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Conventional Radix Number System
Conversion

of
Radix Numbers
Representation
of
Signed Numbers
1.3.1 Sign-Magnitude
1.3.2 Diminished Radix Complement
1.3.3 Radix Complement
Signed-Digit Number System
Floating-point Number Representation
1.5.1 Normalization
1.5.2 Bias
Residue Number System
Logarithmic Number System
References
Problems
xiii
xv
xix
xxi
1
2
4
7
8
8
8
11
15
15

16
22
23
24
26
vii
viii
CONTENTS
2 Addition and Subtraction
2.1 Single-Bit Adders
2.1.1 Logical Devices
2.1.2 Single-Bit Half-Adder and Full-Adders
2.2 Negation
2.2.1 Negation in One’s Complement System
2.2.2 Negation in Two’s Complement System
2.3 Subtraction through Addition
2.4 Overjflow
2.5 Ripple Carry Adders
2.5.1 Two’s Complement Addition
2.5.2 One’s Complement Addition
2.5.3 Sign-Magnitude Addition
References
Problems
3
High-speed Adder
3.1 Conditional-Sum Addition
3.2 Carry-Completion Sensing Addition
3.3 Carry-Lookahead Addition (CLA)
3.3.1 Carry-Lookahead Adder
3.3.2 Block Carry Lookahead Adder

3.4 Carry-Save Adders (CSA)
3.5 Bit-Partitioned Multiple Addition
References
Problems
4 Sequential Multiplication
4. 1 Add-and-shifl Approach
4.2 Indirect Multiplication Schemes
4.2. 1 Unsigned Number Multiplication
4.2.2 Sign-Magnitude Number Multiplication
4.2.3 One’s Complement Number Multiplication
4.2.4 Two’s Complement Number Multiplication
Robertson
’s
Signed Number Multiplication
4.4. 1
4.4.2
Overlapped Multiple Bit Scanning
4.3
4.4
Recoding Technique
Non-overlapped Multiple Bit Scanning
29
29
29
32
35
36
38
40
43

44
44
46
48
50
52
53
53
56
61
61
62
66
71
73
74
77
78
81
81
81
81
85
87
89
89
90
CONTENTS
ix
4.4.3

Booth’s Algorithm
4.4.4
Canonical Multiplier Recoding
References
Problems
5
Parallel Multiplication
5.1
Wallace Trees
5.2
Unsigned Array Multiplier
5.3
Two’s Complement Array Multiplier
5.3.1
5.3.2
Pezaris Two’s Complement Multipliers
Modular Structure
of
Large Multiplier
5.4.1
Modular Structure
5.4.2
Additive Multiply Modules
5.4.3
Programmable Multiply Modules
References
Problems
Baugh-
Wooley
Two

s
Complement Multiplier
5.4
6 Sequential Division
6.1
Subtract-and-Shifl Approach
6.2
Binary Restoring Division
6.3
Binary Non-Restoring Division
6.4
High-Radix Division
6.4.1
High-Radix Non-Restoring Division
6.4.2
SRT Division
6.4.3
Modified SRT Division
6.4.4
Robertson’s High-Radix Division
6.5.1
Convergence Division Methodologies
6.5.2
Divider Implementing Convergence Division
6.5
Convergence Division
Algorithm
6.6
Division by Divisor Reciprocation
References

Problems
7
Fast Array Dividers
7.1
Restoring Cellular Array Divider
7.2
Non-Restoring Cellular Array Divider
93
95
99
100
103
103
105
108
111
117
120
120
123
125
130
132
135
135
138
141
144
144
146

147
147
150
152
155
157
162
164
167
167
171
X
CONTENTS
7.3
Carry-Lookahead Cellular Array Divider
References
Problems
8
Floating Point Operations
8.1
Floating Point AdditiodSubtraction
8.2
Floating Point Multiplication
8.3
Floating Point Division
8.4
Rounding
8.5
Extra Bits
References

Problems
9
Residue Number Operations
9.1
9.2
RNS Addition, Subtraction and Multiplication
Number Comparison and Overflow Detection
9.2.1
Unsigned Number Comparison
9.2.2
Overflow Detection
9.2.3
9.2.4
9.3.1
Unsigned Number Division
9.3.2
Signed Number Division
9.3.3
Multiplicative Division Algorithm
References
Problems
Signed Numbers and Their Properties
Multiplicative Inverse and the Parity Table
9.3
Division Algorithm
10
Operations through Logarithms
10. 1
Multiplication and Addition in Logarithmic Systems
10.2

Addition and Subtraction in Logarithmic Systems
10.3
Realizing the Approximation
References
Problems
I1
Signed-Digit Number Operations
11.1
Characteristics
of
SD Numbers
11.2
Totally Parallel AdditiodSubtraction
11.3
Required and Allowed Values
173
180
181
183
183
184
188
189
191
194
196
199
199
200
200

202
202
203
206
206
209
21 2
216
21 8
221
221
222
225
232
233
235
235
236
237
11.4
Multiplication and Division
References
Problems
Index
CONTENTS
Xi
239
243
244
245

This Page Intentionally Left Blank
Preface
This book describes the fundamental principles of computer arithmetic. Algorithms
for performing operations like addition, subtraction, multiplication and division in
digital computer systems are presented. The goal is to explain the concepts behind
the algorithms rather than to address any direct applications. Alternative methods are
examined and various possibilities considered. With
the
rapid growth of
VLSI
tech-
nology, some currently unattractive algorithms may be implemented with remarkable
performance in the future.
This book can be used as a text of an introductory course for graduate students
or senior undergraduate students
in
electrical engineering, and computer and mathe-
matical sciences. It can also be used as a reference book for practicing engineers and
computer scientists involved in the design, application and development of computer
arithmetic units. For the number systems covered in Sections
1.4, 1.6
and
1.7,
some
exercise problems are listed in Chapters
9,
10
and
11
for in-depth study.

I
have been teaching a computer arithmetic course for fifteen years and have
supervised Doctorate and Masters research projects in this area.
As
a preliminary
version of the book, my lecture notes have received positive and constructive feedback
over the years. An effort has been made to keep fundamental material self-contained
and instructive rather than just referring readers to articles spread throughout the
literature. The theories in the book have been carefully derived and the reasoning
addressed as completely as possible.
In
addition to
"it
is
so,"
pointed to the readers
is "why
it
is
so."
The notation in different discussions is unified and
the
descriptions
are given logically and with clarity. The whole presentation of the text is designed
to be smooth and coherent rather than a collection of broken pieces, with leaps from
Xiii
xiv
PREFACE
one subject to another.
I

gratefully thank my father, Chong Pu Lu, and my husband,
Jiming Yin, for their encouragement and support during the writing
of
this book.
I
also wish to acknowledge the contribution made by my graduate student, C.
T.
Chiang,
for
his assistance in graphical typesetting.
College
Station,
Texas
MI
Lu
1.1
1.2
1.3
1.4
2.
I
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
List

of
Figures
Floating-point Representation
Range
of
the Numbers
Precision
of
Floating-Point Numbers
Double Precision Floating-point Representation
AOI Function
Decoder and Multiplexer
Single-Bit Half-Adder
Design
of
Full-Adder
Single-Bit Subtrator
Negation in One’s Complement System
Negation in
Two’s
Complement System
Subtraction through Addition
One-Bit Adder/Subtractor
18
19
19
20
30
31
32

34
36
37
39
41
42
2.
I0
Two’s
Complement AdditiodSubtraction
45
2.11
One’s Complement AdditionlSubtraction
47
xv
XVi
LIST OF FIGURES
2.12 Block Diagram
of
Sign-Magnitude AdditiodSubtraction 49
2.13 Sign-Magnitude AdditiodSubtraction
50
3.1 Conditional-Sum Addition 55
3.2 Conditional-Sum Adder 57
3.3 Generation and Transmission
of
Carries 58
3.4 Construction
of
Carry-Completion Sensing Adder 59

3.5 Carry-Lookahead Adder 63
3.6 Block Carry-Lookahead Adder
65
3.7 Carry-Save Adder 67
3.8 Carry-Save Adder Tree 69
3.9 Two Types
of
Parallelization in Multi-Operand Addition 70
3.10 Bit-Partitioned Multiple Addition 72
3.11 Carry-Completion Sensing Adder 75
3.12 Carry-Save Adder 75
4.1 Hardware
for
Sequential Multiplication 79
3.13 Bit-Partitional Adder 76
4.2 Register Occupation
80
4.3 Unsigned Number Multiplication 82
4.4 Sign -Magn itude Number Multiplication 83
4.5 One’s Complement Number Multiplication 84
4.6 Two’s Complement Number Multiplication
86
4.7 Negative Multiplicand Times Positive Multiplier 87
4.8 Negative Multiplicand Times Negative Multiplier 88
4.9 Multiple Bit Scanning 90
4.10 String Property 91
4.11 Two-Bit Scan vs. Overlapped Three-Bit Scan 92
4.12 Example
of
Booth’s Multiplication 94

4.13 Scan Pattern in 32-bit Multiplication
97
LIST
OF
FIGURES
XVii
4.14 Adding the Bit-Pairs Parallelly Scanned with a CSA Tree 98
5.1
Wallace Tree 104
5.2 5-by-5 Multiplication 106
5.3 5x4 Array Multiplier Perfomzing 5-by-5 Multiplication 108
5.4
5.5
Distribution
of
Negative Weight
5.6
5.7
5.8 Baugh-Wooley Array with
m=n=5
5.9
5.10 5-by-5 Pezaris Array Multiplier
5.11 The Adjustment
5.12 5-by-5 Bi-Section Array Multiplier
5.13 5-by-5 Tri-section Array Multiplier
5.14 Alignment
of
the Sub-products
5.15 8-by-8 Multiplication via 4-by-4 Multipliers
5.16 Modular Structure

of
Array Multipliers
5.1
7
4-by-2 Additive Multiply Module
5.18
8-by-8 Multiplication via 4-by-2 Multipliers
Different Types
of
Full
Adders
Baugh- Wooley Array Multiplier Perfomzing 6-by-4
Two’s Complement Multiplication
Baugh- Wooley Multiplication
for
10
x
(-3)
Distribution
of
the Negative Weight
111
114
115
115
116
117
118
118
119

120
121
121
122
123
124
5.19
5.20
5.21
5.22
6.1
6.2
6.3
6.4
Modular Structure Applying Additive Multiply Modules 125
Combine Small AMMs into a Large One
127
Summands
of
Preparation in Programmable AMM 128
AMM
8
x
8
Applying AMM
4
x
4
129
Pencil-and-Paper Division 136

Long Division
Form
137
Example
of
Long Division 138
Example
of
Restoring Procedure 139
XViii
LET
OF
FIGURES
6.5 Hardware
for
Restoring Division 140
6.6 Division Performed by Non-Restoring/Restoring
Algorithms I43
6.7 Flow Chart
for
Wilson-Ledley
s
Division Algorithm 148
6.8 Numerical Example
for
Wilson-Ledley
's
Division
Algorithm 149
6.9 Robertson Diagrams 151

6.
I0
Stepwise Approximation
of
the Reciprocal
of
Divisor 160
7.1 4-by-4 Restoring Array Divider I68
7.2 5-by-5 Non-Restoring Array Divider 172
7.3 Carry-Lookahead Array Divider
for
4-bit Division
(Carry-Lookahead Mechanism is Shown in the Second
Row Only)
I75
7.4 Example
of
Carry-Lookahead Array Division I78
7.5 Wires Can Take Up Signifcant Space 179
8.1 Data Flow
of
Floating Point AdditionlSubtraction I85
8.2 Data Flow
of
Floating Point Multiplication 187
8.3 Data Flow
of
Floating Point Division I89
8.4 Example
of

Rounding in Subtraction 194
9.1 Flowchart
of
the Unsigned Number Division Algorithm 210
9.2 Example
of
Signed Number Division 21
1
9.3 Example
of
Conversion to Mixed-Radix Representation 21 4
10.1 Linear Approximation
of
logs
(1
+
x)
224
10.2 Mechanism
for
Multiplication (Division) in Binary
Logarithms 225
10.3 Logarithmic Curve and Four-Straight-Line
Approximation 22
7
10.4 Error
of
the Four-Straight-Line Approximation 228
10.5 Correction Register 229
10.6 Realization

of
the Correction 230
11
.I
Totally-Parallel Adder in Signed-Digit System 237
1.1
1.2
1.3
2.1
2.2
2.3
2.4
2.5
3.1
4.1
5.1
6.1
8.1
9.1
List
of
Tables
Numbers Represented by 4 bits in DifSerent Number
Finding Signed Digits
14
21
30
32
33
Systems

12
Resewed Representation in IEEE Standard
Delay Time and Area
of
Logic Gates
Logic Function
of
a Half-Adder
Logic Function
of
a Full-Adder
Single-Bit Subtractor
35
Negation in One’s Complement System
36
Maximum Inputs
of
CSA Trees
71
Recoding the Triplets
92
Combination and Delay
of
k-input Wallace Tree
105
2-Input 4-Output ROM to Store
p0(s).
158
Round to Nearest Even
I91

201
xix
Parity Table
for
Modulus Set
(3,5,7}
xx
LIST
OF
TABLES
9.2 Mixed-Radix Digits 21 3
10.1 Required
$s.
229
10.2 Mean-Square Error
and
CoefJicients
for
Logarithm
Approximation 231
10.3 Logarithm Equations
11.1
Example
for
SD
Multiplication
11.2 Example
for
SD
Division

232
241
242
About the Author
Mi
Lu
received the M.S. and Ph.D. degrees in electrical engineering from Rice Uni-
versity, Houston, in 1984 and 1987, respectively. She joined the Department of
Electrical Engineering at Texas A&M University in 1987, where she is currently
a professor. Lu’s research interests include computer arithmetic, parallel comput-
ing, computer architectures, VLSI algorithms and computer networks, and she has
published more than 100 technical papers in these areas. In addition, Professor
Lu
has served as associate editor of the
Journal of Computing and Information
and the
Information Sciences Journal,
and was conference chairman of the Fifth, Sixth and
Seventh International Conferences on Computer Science and Informatics. She served
on the panel of the National Science Foundation and the panel of the IEEE Workshop
on Imprecise and Approximate Computation, as well as many conference program
committees. Professor
Lu
is also the chairman of
60
research advisory committees
for Ph.D. and Masters students, is a registered professional engineer, and is a senior
member of the Institute of Electrical and Electronics Engineers. She is recognized
in
Who’s Who in the World

(2001, 2003),
Who‘s Who in America
(2002-2003)
and
Who’s Who of American Women
(2002-2003).
xxi
This Page Intentionally Left Blank
1
Computer Number Systems
As the arithmetic applications grow rapidly, it is important for computer engineers
to be well informed
of
the essentials
of
computer number systems and arithmetic
processes.
With the remarkable progress in the very large scale integration
(VLSI)
circuit
technology, many complex circuits unthinkable yesterday become components eas-
ily realizable today. Algorithms that seemed impossible to implement now have
attractive implementation possibilities for the future. This means that not only the
conventional computer arithmetic methods, but also the unconventional ones are worth
investigation in new designs.
Numbers play an important role in computer systems. Numbers are the basis and
object
of
computer operations. The main task
of

computers is computing, which deals
with numbers all the time.
Humans have been familiar with numbers for thousands of years, whereas repre-
senting numbers in computer systems is a new issue. A computer can provide only
finite digits for a number representation (fixed word length), though a real number
may be composed of infinite digits.
Because of the tradeoffs between word length and hardware size, and between
propagation delay and accuracy, various types of number representation have been
proposed and adopted. In this book, we introduce the Conventional Radix Number
System and Signed-Digit Number System, both belonging to the Fixed-Point Num-
1
2
COMPUTER
NUMBER SYSTEMS
ber System, as well as the Floating-point Number System. Two additional number
systems, the Residue Number System and Logarithmic Number System, will also be
described.
1.1
CONVENTIONAL RADIX NUMBER SYSTEM
A conventional radix number
N
can be represented by a string of
n
digits such as
(4-ldn-2
*.
d1d0)r
with
r
being the radix.

di,
0
5
i
5
n
-
1,
is a digit and
di
E
{0,1,

,r
-
l}.
Note that
the
position of
di
matters, such as
27
is a different number from
72.
Such
a number system is referred to as a
positional weighted
system. Actually,
N
=

dn-l
.
wn-1
+
dn-2
.
wn-2
+
.
*.
+
do
.
WO
i=O
with
wi
being the weight of position
i.
If
r
is fixed, as in thefixed-radix number
system in our further discussion,
wi
=
r'.
Hence,
(1.1)
N
=

dn-l
.
rn-'
+
dn-2
.
rn-'
+
.
+
do
.
ro
n-1
=
xdi.ri.
(1.2)
i=O
If
r
is not fixed, the number becomes a mixed-radix number. For example, to rep-
resent time
T
we have
T
=
[hour
:
minute
:

second]
or
T
=
[(h)r:!,
(m),.~,
(s),~]
where
r:!
=
24;
r1
=
60; ro
=
60.
To
include the fraction into a fixed radix number
N,
let
"."
be a radix point with
the integer part on the left of it and fraction part on the right of it. There are
n
digits
in the integer and
lc
digits in the fraction, such as
(dn-l
.

*.
d0.d-1
.
.
.
d-k)r.
Then
n-1
i=-k
For example, in the decimal number system,
r
=
10,
and
di
E:
{0,1,
N
=
(69.3)10
=
=
=
69.3.
dl
.rl
+do .ro +d-l. r-'
6
x
10'

+
9
x
10'
+
3
x
10-1