15Cr gv2 6050a2548301 mb a01 pv 20121207
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8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
3
2
1
THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC
CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT
WRITTEN PERMISSION,INVENTEC CORPORATION, 2012 ALL RIGHT RESERVED.
HSF Property:ROHS or Halogen-Free
F
F
1310A2548301 (SAMSUNG) R5061 CHANGE TO 6013A0107901 (45.3K OHM)
1310A2548302 (MICRON)
R5061 CHANGE TO 6013A0017501 (30.1K OHM)
E
E
15CR-GV2-PV-1207
D
D
2012.12.07
C
C
B
B
A
A
EE
DRAWER
DESIGN
CHECK
DATE
POWER
INVENTEC
DATE
Abel
Alan
Alan
TITLE
MODEL,PROJECT,FUNCTION
RESPONSIBLE
2012/5/02
DB
X01
SIZE=
FILE NAME:
P/N
21-OCT-2002
DATE
CHANGE NO.
REV
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
3
Main Board
VER:
SIZE
C
CODE
CS
DOC.NUMBER
2
REV
1310A2548303
SHEET
XXX
1
1
of
A01
69
07dc0c0702112402d1001dc1f80075b9
8
7
6
5
4
3
2
1
Index
D
C
B
D
1 COVER
2 INDEX
3 BLOCK DIAGRAM
4 POWER PROCEDURE
5 SELECTOR
6 CHARGER
7 P3V3_P5V0
8 PVDDQ
9 P1V0S_VCCP
10 P1V8S
11 P1V5S
12 PVSA
13 PVCORE1
14 PVCORE2
15 POWER TO EE PORT & EMI PART
16 P5V0S & P3V3S
17 CPU1
18 CPU2_EDP & FDI & DMI & PCIE_GPU
19 CPU3
20 CPU4
21 CPU5
22 CPU6
23 THERMAL & FAN
24 DDR3-1
25 DDR3-2
51 GPU-2
52 GPU-3
53 GPU-4
54 GPU-5
55 VRAM DDR3
56 VRAM DDR3
57 PVCORE_DGPU
58 P1V5S_DGPU
59 DGPU LOAD SWITCH
60 AUB_BLANK
61 AUB_USB30-1
62 AUB_USB30-2
63 LAN RLT8161GSH-CG
64 TRANSFORMER & RJ45
65 JACK
66 DAUGHTER BOARD
67 ESD BOARD
68 POWER SEQUENCE
69 POWER SEQUENCE2 (DEEP S3)
26 PCH1 RTC,HDA,SPI,LPC.SATA
27 PCH2 CLK,SMBUS,PCI-E
28 PCH3 DMI,FDI,SPM
29 PCH4 LVDS,CRT
30 PCH5 PCI,USB
31 PCH6 GPIO,CPU/MISC
32 PCH7 POWER
33 PCH8 POWER
34 PCH9 GND
35 EC IT8527
36 KB CONN & LED
37 40 PIN LCM&TOUCH SCREEN
38 HDMI
39 SATA HDD & ODD
40 USB3.0 CONN
41 CARD READER
42 WLAN
43 G-SENSOR
44 AUDIO-1
45 AUDIO-2
46 AUDIO-3
47 FINGER PRINT
48 MB TO DB CONN & SCREW
49 N14P-GV2
50 GPU-1
C
B
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
INDEX
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
2
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
8
7
VRAM
6
5
NV 14P-GV2
P55~56
4
3
DDR3
DDR3
IVY BRIDGE
PEG
2
1
DDR3L SO-DIMM
1333/1600
MAX 8GB
P24~25
(SOCKET RPGA 989)
37.5MM X 37.5MM
P50~59
HDMI
P17~P22
FDI
P38
DMI
D
D
32.768KHz
LCM/EDPP37
CARD READER
PANTHER
POINT
PCIE
REALTEK_RTS5239
USB
25MHz
WEBCAM
PORT10
RTL 8151
RJ-45
P63
WLAN + BT
C
USB
HM77
PCIE
GIGA LAN
P64
USB
PORT0
USB CONN
P40
SATA
MSATA
HDA
P26~P34
LPC
USB
PORT2
USB CONN
P39
P47
C
USB
25MM X 25MM
SATA HDD
PORT6
P40
MINI CARD
P42
PORT7
PORT1
USB CONN
USB 3.0
989 PIN
PCIE
FINGER PRINT & TOUCH SCREEN
P37
USB 2.0
P41
25MHz
USB
PORT3
USB CONN
P62
P61
SPI ROM
P39
8MB
P26
SUBWOOFER
B
TI_TPA3111D1
P45
REAR SPEAKER
IDT92HD91
SPI ROM
ITE IT8527
AUDIO CODEC
ACCELEROMETER
ST_HP3DC2TR_LGA_16P
512KB
P44
TI_TPA2012D2RTJR
B
KBC
P35
P35
P43
P46
FRONT SPEAKER
IDT CODEC
A
THERMAL
NUVO_NCT7717U_SOT23
P44
DMIC
P44
COMBOM JACK
TI_TPA6130A2RTJR
KEYBOARD
MAIN BATT
TOUCHPAD
P36
P6
P48
P45
SYSTEM CHARGER
DC/DC SYSTEM POWER
P23
P5
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
3
69
of
1
X01
A
07dc0c0702112402d1001dc1f80075b9
8
D
7
AC
PVADPTR
DC
PVPACK
6
VADPBL
MOS
5
4
3
2
1
MOS
MOS
VRP5V0A
CHARGER
BQ24728
5.7815A
P5V0DS
PAD
PAD
PVBAT
MOS
5V / 3.3V
MOS
TPS51123RGER
MOS
MOS
VRPVCCSA_IN
0.001A
P5V0A
C
PAD
0.1546A
P3V3DS
MOS
MOS
PAD
1.35V
TPS51216RUKR
PAD
1.05V
TPS51219RTER
VRPVDDQ
PAD
VRP1V05S_VCCP
9.48A
P1V35
PAD
0.3A
P3V3A
7.444A
P3V3S
VCORE
TPS51650RSLR
PAD
AXG
CSD97374CQ4M
TI_TPS51211DSCR
6A
PVSA
D
0.647A
P1V5S
P1V5S
AP2132BMP
1.8V
RT8068AZQW
VRP1V8S
PAD
1.242A
P1V8S
C
4.0072A
P3VSS_DGPU
MOS
P1V35S_CPUDDR
PAD
MOS
PAD
PAD
MOS
8.5A
P1V05S_CPU
B
VRPVSA
1.991A
P5V0S
PAD
VRP3V3A
VCCSA
TPS51461RGER
6.751A
P1V05S_PCH
3.71A
P1V0S_DGPU
B
53A
PVCORE
33A
PVAXG
2.9A
P1V5S_DGPU
A
A
35A
VCORE_DGPU
TPS51219RTER
EN_DGPU
VRPVCORE_DGPU
PAD
PVCORE_DGPU
DGPU_PG
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
POWER PROCEDURE
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
4
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
7
3
L6035, L6036 BOM CHANGE TO 6014B0225501
PV-1207
1
2
3
4
5
6
7
8
9
10
2
1
1
4
5
6
7
8
9
10
ACES_59012_0100N_003_10P
R6048
1K_1%_2
1
3
PN:6012B0422401
SI-1017
D
2
2
OUT
C6048
2
P3V3AL
1
2
ADP_ID
35
1
2
1SS355VMTE_17
2
1
1
1
0.0015UF_50V_2
3
D6045
CHG_LED# IN
AC_LED#
IN
JACK6015
R6047
12K_1%_2
2
1
P3V3AL
3
1
C6036
35
35
D6035
SEM_SM24_SOT23_3P_DY
C
2
HCB2012KF_121T30_120R_3A
1
2
2
1
2
D
L6036
4
HCB2012KF_121T30_120R_3A
C6037
1000PF_50V_2
1
C6038
2
CSC0402_DY
1
2
5
C6035
1000PF_50V_2
PVADPTR
L6035
2
1
6
CSC0402_DY
8
C
PVPACK
35
35
6
6
BATT_DAT
BATT_CLK
1
BI
BI
1
1
LITEON_L13ESD5V0CA2_SOD523_2P
D7506
2
2
1
C7502
100PF_50V_2
2
1
2
2
LITEON_L13ESD5V0CA2_SOD523_2P
1
D7505
1
C7501
100PF_50V_2
2
1
1
R6051
100_5%_2
B
LITEON_L13ESD5V0CA2_SOD523_2P
D7504
2
2
1
2
C7500
100PF_50V_2
1
2
R6050
2.2K_5%_2
R6052
2.2K_5%_2
2
1
D7504,D7505,D7506 SI Change to 6011B0132401
CN6050
1
2
3
4
5
6
7
8
2
1
2
R6053
1
100_5%_2
2
R6057
100_5%_2
P3V3AL
1
B
2
3
4
5
6
G
7
G
G1
G2
8
TAI_TWUN_PMPCR3_08MNBK2ZZ4H2_8P
2
1
1
1
1
P3V3AL
D7502
BAV99
2
1
R6058
100K_5%_2
3
2
D7501
BAV99
3
2
A
D7500
BAV99
2
3
C6050
0.1UF_25V_2
PN:6012B0487701
A
OUT
BATT_IN#
35
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
5
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
8
7
6
5
4
3
2
1
PVBAT
PVADPTR
VADPBL
D
S
D
G
8
7
6
5
NMOS_4D3S
Q6011
2
4
R6000
0.01_1%_6
BI
BATT_CLK
BI
1
2
BATT_DAT
5
R6023
100K_1%_2
5
35
C6047
CSC0402_DY
2
1
ACDET>3.15V = AC_OVP
1
1
C6001
10UF_25V_5
2
B
A
2
R6025
SHORT_0402_5
VRPVPACK_CSN
2
R6020
SHORT_0402_5
1
2
OUT
BATDRV
INVENTEC
6
R6043
4.3K_5%_2
TITLE
MODEL,PROJECT,FUNCTION
Block
A3
CHANGE by
7
07dc0c0702112402d1001dc1f80075b9
6
1
2
1
C6024
CSC0402_DY
2
1
C6021
0.1UF_25V_2
C6023
0.1UF_16V_2
SIZE
8
D6019
B0530W_7
1
2
2
C6011
10UF_25V_5
1
2
1
C6010
10UF_25V_5
2
4
2
20_1%_5
R6027
2
2
1
1
1
3
VRPVPACK_CSP
1
1
ACDET>2.4V = AC_OK TO CHARGE
1
35
VRPVPACK_LG
2
ACDET>1.8V = ADP_PRES HI
DB2J31300L
P3V3DS
R6046
36.5K_1%_2
ACDET>0.6V = SMBUS OK
1
D6016
2
R6001
0.01_1%_6
1
PAD6015
2
6 7
IN
VRP5V0A_VIN
2
1
C6030
CSC0402_DY
VRPVADPTR_CSN
1
C6046
100PF_50V_2
2
1
1
2
R6049
47K_1%_2
A
2
2
S
OUT
1
C6015
0.047UF_16V_2
G
I_ADP
2
R6015
2.2_5%_2
NMOS_4D3S
15
14
13
12
11
35
1
D
1
REGN
1
Q6001
1
BTST
1SS355VMTE_17
L6000
ETQP3W4R7WFN
VRPVPACK_PH
LQ3E080BNFU7TB
2
HIDRV
ILIM
PVPACK
1
VRPVPACK_HG
C6025
1UF_10V_2
2
1
1
2
1
R6024
10K_5%_2
SCL
ADP_PRES OUT
20
19
18
17
16
PHASE
LODRV
GND
SRP
SRN
BATDRV
2
R6021
300K_1%_2
SDA
VCC
2
16
PVBAT_CHG
S
IOUT
D6018
2
U6000
ACDET
21
D
6
7
8
9
10
C6027
0.047UF_25V_3
TML
G
ACN
ACP
CMSRC
ACDRV
ACPRES
PVADPTR
NMOS_4D3S
1
2
3
4
5
TI_BQ24738RGRR_QFN_20P
Q6000
VRPVADPTR_CSP
C6029
1UF_25V_3
1
2
2
1
R6018
4.3K_5%_2
2
1
R6028
4.3K_5%_2
IN
LQ3E080BNFU7TB
P3V3AL
C
C6012
CSC0805_DY
1
2
C6028
0.1UF_16V_2
1
1
C
2
NMOS_4D3S
RQ3E080BNFU7TB
C6000
10UF_25V_5
G
1
3
8
7
6
5
R7600
RSC_0603_DY
D
2
ACDRV OUT
S
C7600
CSC0402_DY
1
2
3
4
2
6
PVBAT
RQ3E080BNFU7TB
2
1
POWERPAD_2_0610
1
2
R6017
RSC_0402_DY
IN
C6032
0.01UF_50V_2
B
7
Q6012
1
2
3
4
2
P1V5S
6
PVADPTR
PVPACK
BATDRV
OUT
5
6
7
8
2
1
C6031
2200PF_50V_2
C6019
0.1UF_25V_2
2
1
C6020
0.047UF_25V_2
2
1
2
VRP5V0A_VIN
3
PN: 6011B0142501
SI-1022
4
3
2
1
2
1
D
D6099
BAV70W
5
6
7
8
1
NMOS_4D3S
AON6414AL
2
G
8
7
6
5
R6033
2_5%_6
IN
D
C6033
1UF_25V_3
ACDRV
S
1
Q6010
1
2
3
4
4
3
2
1
OUT
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
6
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
8
7
6
5
4
3
2
1
PVBAT
1
PAD6160
POWERPAD_2_0610
2
2
2
PAD6110
POWERPAD_2_0610
2
1
1
1
PVBAT
16 VRPVBAT_3V
IN
VRPVBAT_5V
IN
D
D
VRP5V0A_VIN
1
VBST2
VBST1
DRVH2
DRVH1
17
16
18
VRP5V0A_HG
VRP5V0A_PH
15
VRP5V0A_LG
2
VO=((6.8K/10K)+1)*2
1
1
2
16.5K_1%_2
1
+
2
150UF_6.3V
C6150
VRP5V0A
IN
VRP5V0A_CLK
2
7
13
EN_5V
D6150
DIODES_BAV99
2
1
IN
1
7
B
2
1
C6120
2
1UF_6.3V_2
C6121
1UF_6.3V_2
2
1
7
C6156
0.1UF_16V_2
EN_3V
C
SI-1003
OUT
IN
2
2
POWERPAD1X1M
B
7
1
1
R6150
2
1
2
1
2
TMD
P5V0AL
PAD6105
10.5K_1%_2
2
POWERPAD1X1M
13
1
VO=((15.4K/10K)+1)*2
R6151
1
2
VREG5
2
1
20
19
EN1
R6160
1
PAD6103
VCLK
VRP5V0A_LDO
R6110
2
P3V3AL
EN2
21
1
G
5V_PG
OUT
1
POWERPAD_2_0610
2
VREG3
CS1
2
R7615
RSC_0603_DY
PGOOD
3
VFB1
2
6
7
VFB2
1
CS2
14
2
1
49.9K_1%_2
AON7752
4
5
C6161
10UF_25V_5
2
4
3
2
1
8
7
6
5
D
Q6101
S
R7610
RSC_0603_DY
15
1
2
3
4
1
2
C7610
CSC0402_DY
1
2
1
R6100
6.8K_1%_2
2
1
S
1
VO1
58
PAD6150
ETQP3W4R7WFN
1
2
3
4
2
DRVL1
D
1
SW1
DRVL2
57
OCP=8AMP
Q6151
+
SW2
14
P5V0DS
G
150UF_6.3V
11
13
7
OUT
L6150
AON7752
C6100
VRP3V3A_LG
2
1
2
8
7
6
5
2
2
9
10
8
VRP3V3A_LDO
1
ETQP3W3R3WFN
VRP3V3A_HG
VRP3V3A_PH
46.4K_1%_2
1
1
POWERPAD_2_0610
R6101
10K_1%_2
2
L6100
C6160
10UF_25V_5
5
6
7
8
1
1
2
3
4
12
9
VRP5V0A
C7615
CSC0402_DY
G
1UF_25V_3
1
C6122
2
NMOS_4D3S
AON7410
D
Q6100
1
10UF_25V_5
C6111
2
1
2
8
7
6
5
2.2_5%_3
VIN
8
OUT
SHORT_0402_5
S
S
U6100
TI_TPS51225CRUKR_QFN_20P
2
VR_VDD5
R6161 2
1
Q6150
2
1
C6165
0.1UF_16V_2
D
PAD6100
C
2
R6165
G
1
P3V3DS
R6115
2.2_5%_3
NMOS_4D3S
OCP=7AMP
C6115
0.1UF_16V_2
AON7410
CSC0805_DY
C6110
OUT
OUT
7
6
OUT
VRP3V3A
VRP5V0A_PH
OUT
EN_3V
1
R6987 2
IN
SHORT_0402_5
7
OUT
EN_5V
1
VRP5V0A_CLK
15
7
C6158
0.1UF_16V_2
C6157
0.1UF_16V_2
2
IN
13
P15V0A
D6151
DIODES_BAV99
R6988 2
A
1 1
A
EN_3A5A
2
7
SHORT_0402_5
2
C6159
1UF_25V_3
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
7
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
8
7
6
5
4
3
2
1
P1V35
PVBAT
PAD6200
1
2
VR_VDD5
7
IN
1
4
2
GND
2
3
4
2
4
OUT
VRPVDDQ
C
SI-1005
P0V675M_VREF
19
MODE
VTTGND
18
TRIP
VTTREF
5
B
1
OUT
C6221
0.22UF_6.3V_2
2
C6220
TI_TPS51216RUKR_QFN_20P
2
1
21
10UF_6.3V_3
2
R6202
1
86.6K_1%_2
TML
R6203
100K_5%_2
2
1
1
0.1UF_16V_2
C6218
2
1
0.01UF_50V_2
C6217
2
2
R6201
1
52.3K_1%_2
B
7
1
2
3
VTTSNS
1
2
VTT
Q6201
9
VLDOIN
1
2
3
4
VDDQSNS
S
REFIN
20
G
8
10
PGOOD
D
16.5K_1%_2
1
11
PGND
AON7752
VREF
1
3
PAD6220
POWERPAD1X1M
1
2
1
2
2
VRPVDDQ_LG
8
7
6
5
6
1
PAN_ETQP3W1R0WFN_4P
VRPVDDQ_PH
S5
DRVL
2
2
L6200
VRPVDDQ_HG
R6200
1
2
4
3
2
1
13
OCP=10AMP
2
R7620
C7620
CSC0402_DY RSC_0603_DY
16
SW
1
C6211
5
6
7
8
1
C6216
2.2UF_6.3V_3
2
1
IN
DRVH
C6215
0.1UF_16V_2
Q6200
EN_VRPVDDQ
S3
2
S
17
14
1
D
IN
15
G
EN_VRPVTT
VBST
NMOS_4D3S
C
V5IN
AON7410
R6215
2.2_5%_3
U6200
12
10UF_25V_5_DY
VRPVBAT_VDDQ
P0V675S
1
9
VRPVDDQ
D
+
13
IN
560UF_2.5V
14
1
1
C6200
57
2
58
PAD6210
POWERPAD_2_0610
D
2
POWERPAD_2_0610
C6210
10UF_25V_5
1
2
VRPVDDQ_PG 15
VOUT=REFIN=1.8*(52.3K/(16.5K+52.3K))
MODE=100KOHM:TRACKING DISCHARGE
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
8
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
8
7
6
5
4
3
2
1
P1V05S_CPU
PAD6300
2
2
1
1
IN
VRP1V05S_VCCP
POWERPAD_2_0610
D
D
15
EN_VCCIO
IN
1
1
2
2
13
BST
VRP1V05S_VCCP_HG
3
GSNS
DL
10
VRP1V05S_VCCP_LG
4
VSNS
V5
9
1
1
L6300
1
2
3
4
CYN_PCMC063T_R68MN_4P
1
+
13
VRP1V05S_VCCP
330UF_2V_9MR_PANA_-35%
C6300
9
OUT
2
1
2
4
3
2
1
1
2
1
7
8
2
5
6
7
8
TRIP
5
6
2
R6302
1
80.6K_1%_2
C6319
0.01UF_50V_2
14
S
VOUT=2*11.3/(10+11.3)=1.06V
7 8 13
57 58
D
IN
1
G
B
OCP=20AMP
Q6301
2
FDMS0310AS
VR_VDD5
TI_TPS51219RTER_QFN_16P
C6316
2.2UF_6.3V_3
0_5%_2_DY
GND
IN
C6312
14
EN
VRP1V05S_VCCP_PH
11
2
15
MODE
12
DH
2
1
16
SW
REFIN
2
17
PWPD
PGOOD
VREF
2
PGND
IN
VCC_SENSE_VCCIO
2
COMP
1
C6320
0.01UF_50V_2
2
2
10K_1%_2
R6306
1
2
R6308
11.3K_1%_2
1
VSS_SENSE_VCCIO
1
S
IN
C
1
2
3
4
21
G
1
R6307
VCCIO_SEL
D
U6300
NMOS_4D3S
C6318
0.22UF_6.3V_2
2
1
C6315
0.1UF_16V_2
1
2
Q6300
R6315
2.2_5%_3
2
FDMC8884
1
8
7
6
5
C
C6311
10UF_25V_5
VRPVBAT_P1V05S_CPU
OUT
C6310
10UF_25V_5
VCCIO_PG
C7630
R7630
CSC0402_DY RSC_0603_DY
15
PAD6310
POWERPAD_2_0610
MODE=100KOHM/300KHZ
10UF_25V_5_DY
2
1
R6303
100K_5%_2
PVBAT
B
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
9
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
8
7
6
5
4
3
2
1
D
D
P5V0DS
PAD6980
1
1
2
2
POWERPAD_2_0610
U6970
P1V8S
LX
NC
PGOOD
FB
EN
1
2
3
4
5
PAD6970
L6970
2
ELL5PR1R2N
VRP1V8S_PH 1
OUT P1V8S_PG
IN
EN_P1V8S
2
RICHTEK_RT8068AZQW_WDFN_10P
1
2
B
1
2
2
POWERPAD_2_0610
22UF_6.3V_5
LX
SVIN
CSC0402_DY
C6970
2
1
LX
PVIN
1
PVIN
10K_1%_2 20.5K_1%_2
C6974
2
1
TML
R6970
11
10
9
8
7
6
1
1
C6972
2
0.1UF_16V_2
P5V0DS
VRP1V8S
C
R6971
1
C6975
2
C
10UF_6.3V_3
OCP=4.5AMP
OUT
B
VOUT=((20.5K/10K)+1)*0.6
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
10
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
8
7
6
5
4
3
2
1
D
D
P1V5S
P1V8S
U6350
NC
R6351
2
1
VCTRL
BCD_AP2132BMP_2_5TRG1_PSOP_8P
C
10UF_6.3V_3
VOUT
C6350
VIN
9
8
7
6
5
2
ADJ
1
GND
EN
9.31K_1%_2
IN
TML
PG
10K_1%_2
1
EN_P1V5S
10UF_6.3V_3
2
C6360
1
C6352
2
1UF_6.3V_2
15
1
2
3
4
OUT
R6350
P1V5S_PG
2
C
1
P5V0S
VOUT=(1+(9.31K/10K))X0.8V
B
B
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
11
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
8
7
6
5
4
3
2
1
PVSA
P5V0DS
PAD6500
PAD6510
1
D
1
2
2
OUT
2
VRPVCCSA_IN
2
1
1
IN
VRPVSA
12
POWERPAD_2_0610
POWERPAD1X1M
1
C6522
0.01UF_50V_2
2
1
R6520
5.11K_1%_2
2
1
2
C6521
0.22UF_6.3V_2
2
1
C6520
3300PF_50V_2
D
IN
C
VCCSA_SENSE
C
2
R6521
RSC_0402_DY
OCP=7AMP
GND
VREF
COMP
SLEW
VOUT
MODE
1
2
3
4
5
6
1
SW
PGND
SW
PGND
BST
2
3
4
2
4
OUT
VRPVSA
12
CYN_PCMB063T_R33MS_4P
1
2
C6515
0.1UF_16V_2
C6500
C6501
C6502
C6503
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5
22UF_6.3V_5_DY
18
17
16
15
14
13
2
TI_TPS51462RGER_QFN_24P
1
PGND
SW
1
2
U6500
1
3
1
VIN
L6500
VRPVSA_PH
7
8
9
10
11
12
2
SW
1
SW
VIN
1
VIN
V5DRV
V5FILT
PGOOD
VID1
VID0
EN
C6510
22UF_6.3V_5
2
1
TML
2
25
24
23
22
21
20
19
IN
C6511
0.1UF_16V_2
2
1
VRPVCCSA_IN
B
B
R6502
VRPVCCSA_IN
1
IN
2
15
IN
EN_PVCCSA
IN
VCCSA_VID0
21
IN
VCCSA_VID1
21
SHORT_0402_5
R6524
R6522
10K_5%_2
2
1
C6524
1UF_6.3V_2
2
1
C6523
1UF_6.3V_2
2
1
1
2
SHORT_0402_5
R6525
R6523
10K_5%_2
2
1
1
A
2
SHORT_0402_5
A
OUT PVCCSA_PG
15
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
12
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
3
PVBAT
IN
2.2_5%_3
OUT
PVCORE_PG
17
CPGOOD
IN
VR_SVID_CLK
18
VCLK
OUT
VR_SVID_ALERT#
19
ALERT#
BI
VR_SVID_DATA 20
VDIO
1
7
07dc0c0702112402d1001dc1f80075b9
6
1
C6615
CSC0805_DY
2
1
2
1
1
+
2
1
2
1
R6608
100K_5%_NTC
2
R6609
28.7K_1%_2
PVCORE
B
IN
13
OUT
14
C6603
470UF_2V
1
+
3
1
2
2
+
1
C6602
470UF_2V
1
4
2
L6620
PAN_ETQP4LR36ZFC_4P
R7662
RSC_0603_DY
5
6
7
8
C7662
CSC0402_DY
2
OUT
OUT
2
3
1
1
A
R6730
100K_5%_2
IN
VRP1V05S_VCCP
R6729
100K_5%_NTC
20
13
IN
20
13
BI
1
C6635
2
1
VR_SVID_CLK
0.1UF_16V_2
C6727
0.1UF_16V_2_DY
R6633
130_1%_2
13
2
IN
1
2
1
VREF_CPU
2
R6632
54.9_1%_2
1
2
R6728
15.4K_1%_2
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block
VR_SVID_DATA
SIZE
A3
CHANGE by
8
C6614
CSC0805_DY
2
1
R6607
17.8K_1%_2
2
IN
GSKIP#
2
IN
14
R6638
IN
13
2 R6720 1
SHORT_0402_5
1
GPU_CSP2 2
R6722 0_5%_2_DY
1
GPU_CSN2 2
R6726 0_5%_2_DY
1
OUT
R6724
SHORT_0402_5
1
GPU_CSN1 2
1
2
1
SHORT_0402_5
R6630
2
VR_ON
2
R6610
162K_1%_2
RSC_0402_DY
R6725
SHORT_0402_5
R6718
4.99K_1%_2
VREF_CPU
2
2
R6631
0_5%_2_DY
A
2
GPU_CSP1
1
EN_PVCORE
1
2
4
3
2
1
1
5
6
7
8
PVBAT
14
R6723
0_5%_2_DY
C6726
47PF_50V_2
1
1
2
3
36
CPWM3
0.1UF_16V_2
2
R6616
10K_5%_3
R6731
2
1
C6625
0.033UF_16V_2
4
3
2
1
1
2
IN
1
CPU_CSP2
14
VREF_CPU
OUT
S
IN
R6721
1
2
SHORT_0402_5
CPU_CSN2
2
G
R6716
0_5%_2_DY
13
OUT
R6719
0_5%_2_DY
1
2
1
OUT
13
2
35
GPWM2
1
D
2
IN
13
C6624
2
Q6621
IN
P3V3DS
R6715
SHORT_0402_5
GFX_VCC_SENSE 1
2
C
58
4
3
2
1
34
GPWM1
57
2
33
14
S
25
13
FDMS0306AS
21
IN
9
D
R6714
0_5%_2_DY
15
8
G
1
2
L6610
PAN_ETQP4LR36ZFC_4P
C7661
CSC0402_DY
NMOS_4D3S
2
2
GPWM2
1
7
FDMS7692
37 1
CPWM3
38
VBAT
GSKIP#
CDH2
GF_IMAX
GPWM1
GPGOOD
24
GTHERM
1
2.2_5%_3
23
GCSP2
1
1
GCSN2
R6712
39
GCSP1
75K_5%_2
40
GCSN1
2
CSW2
CBST2
R6606
PVAXG_PG
PVCORE
R7661
RSC_0603_DY
PVBAT_CPU
VR_HOT#
R6713
SHORT_0402_5
GFX_VSS_SENSE
41
SLEW
GVFB
IN
CDL2
IN
22
GCOMP
21
42
0.1UF_16V_2
21
GGFB
B
R6629
20K_1%_2
OUT
CPU_PROCHOT#
PGND
OCP=65AMP
4
2
Q6620
15
OUT
32
17
31
35
43
TI_TPS51650RSLR_QFN_48P
30
13
29
20
44
C6613
CSC0805_DY
1
1
2
2
VR_VDD5
28
20
CDL1
V5DRV
U6600
27
C6633
2.2UF_6.3V_3
15
13
26
2
2
1
R6628
0_5%_2_DY
1
R6711
499K_1%
2
28
20
C6612
10UF_25V_5
2
1
2
3
1
1
2
1
R6604
28.7K_1%_2
+
1
45
2
C6601
470UF_2V
46
CSW1
1
R6603
100K_5%_NTC
3
CBST1
VR_ON
2
R6602
17.8K_1%_2
2
V3R3
16
2
C6600
470UF_2V
15
VR_ON
D
S
C6622
2
1
1
G
13
1
3
7
8
9
13
14
57
58
13
IN
CPU_CSP1
5
6
7
8
1
2
V5_CPU
OUT
1
47
C6611
10UF_25V_5
2
48
C6630
4.7UF_10V_3
1
2
1
2
3
4
IN
IN
CPU_CSN2
CPU_CSN1
5
6
IN
V5
CDH1
13
5
6
7
8
1
2
1
2
C6631
0.1UF_16V_2_DY
R6618
100K_5%_NTC
13
13
13
13
IN
CPU_CSP2
7
CPU_CSP3
CPU_CSN3
C6629
2.2UF_10V_3
IN
IN
20
20
IN
8
CPU_CSP1
49
IN
D
GND
2
R6617
10_5%_3
CPU_CSN1
R6605
162K_1%_2
Q6611
C6634
2.2UF_6.3V_3
1
R6601
C
IN
VR_VDD5
V5_CPU
OUT
IN
OUT
13
OUT
C6623
0.033UF_16V_2
13
FDMS0306AS
COCP-R
CTHERM
CF-IMAX
2
13
CCSP1
CCSN1
CCSN2
CCSP2
VREF
CCSP3
GOCP-R
14
CCSN3
IN
13
CCOMP
13
CVFB
CGFB
P3V3DS
VREF_CPU
IN
VREF_CPU
9
OUT
10
13
11 VCCSENSE
0
1
0
DNP
8.25K_1%_2
R6619
15.4K_1%_2
VREF_CPU
1
2
13
S
DNP
R6723
SHORT_0402_5
2
R6625
PVBAT_CPU
D
R6719
2
PVBAT_CPU
Q6610
0
1
G
0
DNP
R6636
NMOS_4D3S
DNP
R6716
1
2
SHORT_0402_5
FDMS7692
R6714
1
12 VSSSENSE
30K DNP
1
200K DNP
R6712
2
R6711
R6635
2
C6632
47PF_50V_2
R6626
4.7K_1%_2
56K DNP
1
VREF_CPU
IN
R6627
75K_1%_2
R6627
13
1
D
2+0
3.3K DNP
2
2+1
P3V3DS
SI 1005
1
1
R6623
24K_1%_2
1
2
SI 1005
R6626
1
PAD6610
2
R6621
90.9K_1%_2
1
2
2
POWERPAD_2_0610
2
1
2
1
C6610
10UF_25V_5
VREF_CPU
IN
4
R6622
39K_1%_2
1
2
+
13
5
R6620
43K_1%_2
1
2
15UF_25V
6
C6699
7
4
3
2
1
8
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
13
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
8
7
6
5
4
3
2
1
D
D
13
GPU_CSN1
OUT
1
2
C6723
3300PF_50V_2
13
OUT
GPU_CSP1
1
2
C6722
0.015UF_10V_2
C
1
PVBAT
PVAXG
1
2
4
1
2
L6710
PAN_ETQP4LR24AFM_4P
R7671
4.7_5%_3
9
TI_CSD97374CQ4M_SON_8P
2
1 2
PN: 6019B0999601-001
PV-1121
B
1
OCP=39AMP
4
2
PVBAT_AXG
14
OUT
B
2
C7671
470PF_50V_2
PAD6710
POWERPAD_2_0610
1
3
2
3
1
2
2
R6704
28.7K_1%_2
C6711
10UF_25V_5
VSW
1
2
PVBAT_AXG
1
2
R6703
100K_5%_NTC
1
VIN
4
5
2
R6702
17.8K_1%_2
C6710
10UF_25V_5
3 1UF_6.3V_2
VDD
1
2
BOOT_RPGND
2
22UF_6.3V_5_DY
BOOT
6
1
22UF_6.3V_5_DY
C6703
2
1
IN
C6721
7
57
22UF_6.3V_5
C6702
2
1
14
1
13
1
2
SKIP#
9
C6700
1
0.1UF_16V_2
PWM
7 8
58
IN
22UF_6.3V_5
C6701
2
1
2
2.2_5%_3
8
GPWM1
C6720
IN
R6705
162K_1%_2
VR_VDD5
U6710
1
13
R6701
1
GSKIP#
IN
PGND
13
C
2
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
Diagram
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
14
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
8
7
6
5
4
3
2
1
31
D
16
IN
CORE_PWEN#1
G
S
35
1
R7018
EN_P1V0_VCCP => 1.05V
35
21
15
IN
R7023
CORE_PWEN
1
EN_VCCIO
2
10K_5%_2
C7013
2
Q7003
2
R7022
22_5%_2
2
P0V675S
D
10K_5%_2
P3V3S
9
OUT
8
1
2
D
100_5%_2
1
0.01uF_50V_2
12
C7013 CLOSE U6300
SSM3K7002BFU
R7019
VRPVDDQ_PG
IN
R7020
PVCCSA_PG
IN
1
ALL_PWGD_IN
2
35
OUT
2
100_5%_2
35
21
15
IN
R7025
CORE_PWEN
1
EN_P1V8S
2
C7012
10
OUT
2
10K_5%_2
2
C7015
1
1000PF_50V_2
1
0.01uF_50V_2
R7017
35
21
15
IN
CORE_PWEN
1
R7024
2 EN_P1V5S
9
IN
VCCIO_PG
C
C7007
2
R7016 2
SHORT_0402_5
EN_PVCCSA
1
11
OUT
100K_5%_2
2
C
C7015CLOSE U6970
10K_5%_2
1
P3V3S
OUT
12
1
OCP=12AMP
CSC0402_DY
OCP=8AMP
P1V05S_PCH
C7007 CLOSE U6351
P1V05S_CPU
PAD7000
2
35
IN
CPU_PWEN
1
R7021 2
EN_PVCORE
13
OUT
2
1
1
POWERPAD_2_0610
SHORT_0402_5
1
CORE_PWEN
1
2
EN_VRPVTT OUT
8
C7019
2
1
35
IN
ALWAYS_PW_EN 2
R7027
1
1K_5%_2
PVCORE_PG
13
OUT
PVAXG_PG
2
IN
DGPU_PG
R7008
1
DGPU_PWROK OUT
2
31
B
35
SHORT_0402_5
1
R7041
2K_5%_2
EN_3A5A
OUT
P3V3AL
7
7
IN
5V_PG
R7044
1
2
100K_5%_2_DY
SI-1016
SI-1017
1
C7018 CLOSE TO U6100
R7043
RSMRST#
2
28
OUT
35
0_5%_2
SI-1012
SI-1017
C7008
1000PF_50V_2_DY
A
2
OUT
57
2
2
1
R7042
2K_5%_2
P3V3DS
13
R7010
1
C7017 CLOSE TO U6200
C7019 CLOSE TO U6200
28
8
CSC0402_DY
0.1uF_16V_2
A
OUT
C7017
2
100K_5%_2
EN_VRPVDDQ
1
B
IN
R7026
1
2
100K_5%_2
1
15
RESUME_PWEN
2
21
IN
0.1UF_25V_2
35
35
1
DIODE-BAT54-TAP-PHP
R7029
P3V3S
C7016 CLOSE U6600
200K_5%_2
2 R7028 1
C7018
NC
3
noise cap
1
10K_5%_2
2
2
C7016
0.1uF_16V_2_DY
D7000
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
POWER TO EE PORT & EMI PART
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
15
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
6
5
4
3
2
1
P3V3S
P3V3DS
2.665A
2200pF_50V_2
C7026
1
4
G
3
1
R7036 2
C
Q7019
P5V0DS
D
G
S
SHORT_0402_5
1
1
2
3
4
G
C7642
2
S
S
C7024
2
D
1
Q7017
PMN35EN
SSM3K7002BFU_DY
NMOS_4D3S
1
0.1uF_16V_2
2
S
2
D
D
P5V0A
C7025
2
R7035
1
D
S
1
R7037
32
P1V35S_CPUDDR
5.647A
8
7
6
5
P5V0DS
2
2
SI-0925
Q7012
3
NMOS_4D1S
R7005 2
Q7013
G
R7034 2
1
P3V3A
SHORT_0402_5
SSM3K7002BFU
4
SHORT_0402_5
1
2
5
6
D
G
1M_5%_2
1
R7045
2
1
PMN35EN
1
2
3
SSM3K7002BFU
S
NMOS_4D1S
RSC_0603_DY
G
P1V35
1
D
PMN35EN
3
4
G
2
S
D
P3V3A_5A_PWEN#1
IN
10uF_6.3V_3
Q7011
1
3 2
35
3.135A
P3V3S
C
Q7018
P5V0S
NMOS_4D1S
R7031
10K_5%_2
1
P5V0DS
1
2
5
6
22_5%_5
10uF_6.3V_3
2
2
2
SSM3K7002BFU
Q7016
1
2
5
6
P15V0A_RC_A
1
1
C7021
S
G
SI-0925
R7004 2
1
P15V0A
P3V3AL
SHORT_0402_5
2200pF_50V_2
3
CORE_PWEN# 1
D
Q7006
IN
3
PMN35EN
P15V0A_RC_S
15
G
NMOS_4D1S
D
35
S
4
D
1
2
10K_5%_2_DY
P3V3A
P3V3DS
Q7004
C7022
2
R7046
1M_5%_2
R7030
SI-0925
PV-1130
1
2
5
6
C7020
P15V0A
1
P3V3AL
10uF_6.3V_3
7
10uF_6.3V_3
8
D
B
32
32
R7038
RSC_0603_DY
G
P3V3A
C7645
2
1
B
0.1uF_16V_2
Q7020
D
Q7014
SSM3K7002BFU_DY
1
G
S
2
S
1
RSC_0603_DY
P5V0A
1
C7023
R7006 2
2
1
1
SHORT_0402_5
R7032
1
PN: 6015B0134801
P5V0S
10uF_6.3V_3
RQ3E100BNFU7TB
SSM3K7002BFU_DY
2
P3V3S
C7648
2
1
0.1uF_16V_2
P1V35S_CPUDDR
C7654
2
2
1
PVBAT_CHG
IN
6
VRPVBAT_3V
IN
7
0.1UF_25V_2
R7033
220_5%_2_DY
C7655
1
1
2
0.1UF_25V_2
3
A
A
C7651
1
USBPWR_EN
Q7015
G
S
1
35
IN
D
2
40
48
0.1uF_16V_2
SSM3K7002BFU_DY
C7657
2
2
1
VRPVBAT_5V
IN
7
0.1UF_25V_2
INVENTEC
TITLE
SI-1005 EMI
MODEL,PROJECT,FUNCTION
SI-1005 EMI
P5V0S
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
& P3V3S
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
16
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
8
7
6
5
4
3
2
1
CHIEF RIVER CPU
LOCATION 4500~4699
VER.001_20120807
D
1
R4539
2.2K_5%_2
R4536
1
H_SNB_IVB#
2
1K_5%_2
C26
TP4502
TP24
PROC_SELECT#
1 AN34
CLOCKS
NV_CLE
CN4500
MISC
OUT
2
R4535
2
31
1K_5%_2_DY
1
P1V8S
A28
A27
BCLK
BCLK#
SKTOCC#
DPLL_REF_CLK
H_PECI
AN33
R4540
CPU_PROCHOT#
1
H_PROCHOT#_R AL32
2
31
OUT
1
R4528
SM_RCOMP[2]
1
28
BI
H_PM_SYNC
31
IN
H_CPUPWRGD
42
17
IN
PM_DRAM_PWRGD_CPU
R4537
1
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
TCK
TMS
TRST#
TDI
TDO
DBR#
PM_DRAM_PWRGD_CPU_R V8
2
35
30
BUF_PLT_RST#
IN
1
BUF_PLT_RST#_CPU
2
BPM#[3]
RESET#
1
R4530
RSC_0402_DY
BPM#[5]
BPM#[6]
BPM#[7]
OUT
OUT
17
17
AL35XDP_DBRESET#
OUT
17
P3V3S
P1V35
1
1K_1%_2
R4543
2
17
17
R4546
2
3
Q4504
IN
IN
R4712
17
RSC_0402_DY
17
CHECK
2
CPU_DRAMRST#
17
G
BSS138LT1
17
25
17
2
1
24
17
D
PCH_DDR_RST
R4551 1
2
1K_5%_2
IN
IN
IN
IN
XDP_TDO
R4552 1
XDP_TMS
R4553 1
2 51_5%_2
2 51_5%_2
XDP_TDI_R
R4554 1
2 51_5%_2
XDP_PREQ#
R4555 1
2 51_5%_2_DY
IN
IN
XDP_TRST#
R4556 1
XDP_TCLK
R4557 1
2 51_5%_2
2 51_5%_2
A
11
21
DIMM_DRAMRST# OUT
1K_5%_2
S
35
XDP_DBRESET#
2
1
C4544
2
D
G
OUT
IN
P1V05S_CPU
1
100pF_50V_2_DY
2
3
S
2
Q4503
AR28XDP_TDI_R
AP26XDP_TDO
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
2
1
R4501
2
3
D
1
10K_5%_2
2
R4526
1
1K_1%_2
PM_DRAM_PWRGD_CPU
SSM3K7002BFU
17
17
17
17
17
Q4505
G
C
AR26XDP_TCLK
AR27XDP_TMS
AP30XDP_TRST#
CSC0402_DY
EMI
1
TP24
TP24
OUT
OUT
OUT
OUT
C4506
200_5%_2
P3V3A
1
1
B
11
2
P1V35S_CPUDDR
750_1%_2
R4542
2
B
TP4504
TP4505
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
BPM#[2]
AR33
BPM#[4]
R4527
2 140_1%_2
2 25.5_1%_2
2 200_1%_2
SM_DRAMPWROK
BPM#[0]
R4538
1.5K_1%_1/16W
CSC0402_DY
2
1
R4544
4.99K_1%_2
2
C4703
INVENTEC
EMI
2
CSC0402_DY
2
1
C4699
11
2
RSC_0402_DY
0.047uF_16V_2
S
C4704
R4711
SSM3K7002BFU
6015B0110701-001
R4558 1
R4559 1
R4560 1
AP29
AP27XDP_PREQ#
PRDY#
PREQ#
BPM#[1]
1
EMI
THERMTRIP#
130_1%_2
PM_DRAM_PWRGD
17
OUT
1
2
1
2 2
1
R4529
C4505
CSC0402_DY RSC_0402_DY
EMI
IN
2 C4502
2
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
AK1
A5
A4
SM_RCOMP[0]
10K_5%_2
28
27
27
R4541
C
A
IN
IN
P1V05S_CPU
2 1K_5%_2
2 1K_5%_2
RSC_0402_DY CSC0402_DY
PROCHOT#
AN32
R4500
D
CLK_DP_P
CLK_DP_N
R4523
SM_RCOMP[1]
PM_THRMTRIP#
LVDS DISABLE OPTION
2 1K_5%_2_DY
2 1K_5%_2_DY
1
1
1
1
27
27
IN
IN
CPU_DRAMRST#
R8
SM_DRAMRST#
JTAG & BPM
C4697
2
PECI
R4525
CLK_DP_PCH_DP
CLK_DP_PCH_DN
56_5%_2
47pF_50V_2
IN
CATERR#
MISC
DDR3
OUT
THERMAL
35
1 AL33
PWR MANAGEMENT
1
62_5%_2
R4531
2
13
1
35
TP4503
TP24
R4524
A16
A15
DPLL_REF_CLK#
P1V05S_CPU
CLK_DMI_PCH_DP
CLK_DMI_PCH_DN
TITLE
MODEL,PROJECT,FUNCTION
CPU -
EMI
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
1
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
17
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
5
4
3
2
CN4500
P3V3A
P1V05S_CPU
PEG_ICOMPI
18
30
18
30
18
30
30
18
30
18
30
18
30
30
30
18
18
18
2
BOARD_ID0
R4822 1
BOARD_ID1
R4827 1
R4825 1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
BOARD_ID6
2
10K_5%_2_DY
10K_5%_2_DY
2
10K_5%_2_DY
2
10K_5%_2
2
10K_5%_2_DY
R4826 1
R4828 1
2 10K_5%_2
2
10K_5%_2
R4829 1
R4844 1
2
10K_5%_2
2
10K_5%_2
28
28
28
28
0:R4844
1:R4828
0:R4844
1:R4816
0:R4844
1:R4825
UMA
0
0
0
0
1
DIS(DUAL)
0
0
0
0
DIS(SINGAL)
1
0
0
0
0:R4844
1:R4827
0:R4844
1:R4822
0
0
1
0
1
1
0
1
P1V05S_CPU
DMI_RX0_DP
DMI_RX1_DP
DMI_RX2_DP
DMI_RX3_DP
G22
D22
F20
C21
FDI_TX0_DN
FDI_TX1_DN
FDI_TX2_DN
FDI_TX3_DN
FDI_TX4_DN
FDI_TX5_DN
FDI_TX6_DN
FDI_TX7_DN
A21
H19
E19
F18
B21
C20
D18
E17
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
FDI_TX0_DP
FDI_TX1_DP
FDI_TX2_DP
FDI_TX3_DP
FDI_TX4_DP
FDI_TX5_DP
FDI_TX6_DP
FDI_TX7_DP
A22
G19
E20
G18
B20
C19
D19
F17
28
28
IN
IN
FDI_FSYNC0
FDI_FSYNC1
J18
J17
28
IN
FDI_INT
H20
IN
IN
FDI_LSYNC0
FDI_LSYNC1
J19
H17
28
28
P1V05S_CPU
1
G21
E22
F21
D21
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
28
28
28
28
28
28
28
28
ID6 ID5 ID4 ID3 ID2 ID1 ID0
0:R4829
1:R4823
DMI_RX0_DN
DMI_RX1_DN
DMI_RX2_DN
DMI_RX3_DN
OUT
OUT
OUT
OUT
28
28
28
28
28
28
28
28
C
0:R4844
1:R4818
OUT
OUT
OUT
OUT
DMI_RX[1]
PEG_RX#[2]
PEG_RX#[3]
DMI_RX[2]
PEG_RX#[4]
DMI_RX[3]
PEG_RX#[5]
PEG_RX#[6]
28
28
28
28
2 10K_5%_2_DY
R4818 1
BOARD_ID6
10K_5%_2
DMI_RX[0]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
FDI0_FSYNC
FDI1_FSYNC
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
FDI_INT
PEG_TX#[9]
FDI0_LSYNC
PEG_TX#[10]
FDI1_LSYNC
PEG_TX#[11]
PEG_TX#[12]
R4900
1
10K_5%_2
OUT
3
IN
PEG_TX#[14]
eDP_COMPIO
PEG_TX#[15]
PEG_TX[0]
eDP_HDP#
IN
IN
NB_EDP_AUX_DP
NB_EDP_AUX_DN
C15
D15
37
37
IN
IN
IN
IN
NB_EDP_TX0_DP
NB_EDP_TX1_DP
NB_EDP_TX2_DP
NB_EDP_TX3_DP
C17
F16
C16
G15
eDP_AUX
eDP_AUX#
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
D
37
37
G
IN
37
S
Q4900
EDP_TRAN_HPD
1
1
SSM3K7002BFU_DY
PN: 6015B0110701_DY
Rc
2
1ST : 6015B0110701
2ND : 6015B0142901
R4901
37
37
2
100K_5%_2_DY
NB_EDP_TX0_DN
NB_EDP_TX1_DN
NB_EDP_TX2_DN
NB_EDP_TX3_DN
IN
IN
IN
IN
PEG_TX[6]
PEG_TX[7]
eDP_TX[0]
eDP_TX[1]
PEG_TX[8]
eDP_TX[2]
PEG_TX[9]
eDP_TX[3]
PEG_TX[10]
PEG_TX[11]
C18
E16
D16
F15
eDP_TX#[0]
PEG_TX[12]
eDP_TX#[1]
PEG_TX[13]
eDP_TX#[2]
PEG_TX[14]
eDP_TX#[3]
PEG_TX[15]
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
PEG_RX0_C_DP
PEG_RX1_C_DP
PEG_RX2_C_DP
PEG_RX3_C_DP
PEG_RX4_C_DP
PEG_RX5_C_DP
PEG_RX6_C_DP
PEG_RX7_C_DP
IN
IN
IN
IN
IN
IN
IN
IN
50
50
50
50
50
50
50
50
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
PEG_TX0_DN
PEG_TX1_DN
PEG_TX2_DN
PEG_TX3_DN
PEG_TX4_DN
PEG_TX5_DN
PEG_TX6_DN
PEG_TX7_DN
C4516
C4521
C4523
C4526
C4528
C4531
C4533
C4536
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
0.22UF_16V_2
0.22UF_16V_2
0.22UF_16V_2
0.22UF_16V_2
0.22UF_16V_2
0.22UF_16V_2
0.22UF_16V_2
0.22UF_16V_2
PEG_TX0_C_DN
PEG_TX1_C_DN
PEG_TX2_C_DN
PEG_TX3_C_DN
PEG_TX4_C_DN
PEG_TX5_C_DN
PEG_TX6_C_DN
PEG_TX7_C_DN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
50
50
50
50
50
50
50
50
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_TX0_DP
PEG_TX1_DP
PEG_TX2_DP
PEG_TX3_DP
PEG_TX4_DP
PEG_TX5_DP
PEG_TX6_DP
PEG_TX7_DP
C4538
C4541
C4543
C4546
C4548
C4551
C4553
C4554
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
0.22UF_16V_2
0.22UF_16V_2
0.22UF_16V_2
0.22UF_16V_2
0.22UF_16V_2
0.22UF_16V_2
0.22UF_16V_2
0.22UF_16V_2
PEG_TX0_C_DP
PEG_TX1_C_DP
PEG_TX2_C_DP
PEG_TX3_C_DP
PEG_TX4_C_DP
PEG_TX5_C_DP
PEG_TX6_C_DP
PEG_TX7_C_DP
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
50
50
50
50
50
50
50
50
P1V05S_CPU
P3V3S
P1V05S_CPU
C7639
1
D
PVCORE
C
B
2
P3V3S
0.1uF_16V_2
C7640
1
2
1
R4765
UMA
DGPU_PRSNT#
2
10K_5%_2_DY
0.1uF_16V_2
C7641
1
2
1
R4766
IN
18
27
IN
18
27
DIS
DGPU_PRSNT#
2
10K_5%_2
0.1uF_16V_2
CPU SOCKET, PN: 6026B0154901
FOR EMI
P3V3S
50
50
50
50
50
50
50
50
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
A
P1V05S_PCH
IN
IN
IN
IN
IN
IN
IN
IN
eDP_ICOMPO
PEG_TX[1]
MOUNT FOR EDP PANEL
Qa
NB_EDP_HPD#
A18
A17
B16
eDP
18
NB_EDP_HPD#
PEG_TX#[13]
CPU_EDP_COMPIO
2
24.9_1%_2
Co-Layot for eDP:
MOUNT RC, QA
2
B
R4502
P3V3S
PEG_RX0_C_DN
PEG_RX1_C_DN
PEG_RX2_C_DN
PEG_RX3_C_DN
PEG_RX4_C_DN
PEG_RX5_C_DN
PEG_RX6_C_DN
PEG_RX7_C_DN
1
R4823 1
2
IN
IN
IN
IN
P1V5S_DGPU
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
1
BOARD_ID5
BOARD_ID3
OUT
OUT
OUT
OUT
OUT
OUT
OUT
18
2 10K_5%_2_DY
BOARD_ID4
R4819 1
R4824 1
BOARD_ID2
28
28
28
28
10K_5%_2
PEG_RX#[1]
C7603
0.1uF_16V_2
30
2 10K_5%_2_DY
PEG_RX#[0]
C7605
0.1uF_16V_2
18
2
R4821 1
R4820 1
DMI_RX#[3]
2
30
R4817 1
BOARD_ID1
DMI_RX#[2]
1
18
BOARD_ID0
DMI_RX#[1]
2
30
OUT
OUT
OUT
OUT
OUT
OUT
OUT
B28
B26
A24
B23
FOR EMI
2
24.9_1%_2
2
18
DMI_TX0_DP
DMI_TX1_DP
DMI_TX2_DP
DMI_TX3_DP
PEG_RCOMPO
1
2
18
30
IN
IN
IN
IN
DMI_RX#[0]
DMI
30
2
B27
B25
A25
B24
PCI EXPRESS* - GRAPHICS
D
GPIO59
OUT
DMI_TX0_DN
DMI_TX1_DN
DMI_TX2_DN
DMI_TX3_DN
Intel(R) FDI
30
28
28
28
28
10K_5%_2
R4503
CPU_PEG_ICOMPI
J22
J21
H22
PEG_ICOMPO
R4816 1
1
C7606
0.1uF_16V_2
6
1
7
C7604
0.1uF_16V_2
8
SI-1005 EMI
A
AGND_AUDIO
PVBAT
PVBAT
PVPACK
P3V3S
P5V0DS
P3V3S
P5V0S
P1V35
P5V0DS
SCREW330_600_1P
S5003
1
S5002
1
SCREW330_600_1P
S5001
1
SCREW330_600_1P
S5000
1
SCREW330_600_1P
1
C7623
0.1uF_16V_2
2
1
C7624
0.1uF_16V_2
2
1
C7626
0.1uF_16V_2
2
1
C7627
0.1uF_16V_2
2
1
C7628
0.1uF_16V_2
2
C7629
0.1uF_16V_2
1
2
C7631
0.1uF_16V_2
1
2
1
C7632
0.1uF_16V_2
2
1
C7607
0.1uF_16V_2
2
1
C7608
0.1uF_16V_2
2
1
C7609
0.1uF_16V_2
2
1
C7611
0.1uF_16V_2
2
1
C7612
0.1uF_16V_2
2
1
C7621
0.1UF_25V_2
2
1
C7622
0.1UF_25V_2
2
1
C7613
0.1UF_25V_2
2
1
C7614
0.1UF_25V_2
2
C7616
0.1UF_25V_2
1
C7601
0.1UF_25V_2
2
1
2
1
C7602
0.1UF_25V_2
2
C7617
0.1UF_25V_2
1
C7618
0.1UF_25V_2
2
1
2
1
2
C7619
0.1UF_25V_2
FOR DGPU SCREW
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CPU -
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
2
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
18
69
of
1
X01
07dc0c0702112402d1001dc1f80075b9
8
7
6
5
4
3
CN4500
2
CN4500
SB_CLK[0]
C
B
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
C5
D5
D3
D2
D6
C6
C2
C3
F10
F8
G10
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N10
N8
N7
M10
M9
N9
M7
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
SA_DQ[0]
SA_CKE[0]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_CLK[1]
SA_CLK#[1]
SA_CKE[1]
RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]
RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]
SA_CS#[0]
SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]
SA_ODT[0]
SA_ODT[1]
RSVD_TP[9]
RSVD_TP[10]
SA_DQS#[0]
SA_DQ[38]
SA_DQS#[1]
SA_DQ[39]
SA_DQS#[2]
SA_DQ[40]
SA_DQS#[3]
SA_DQ[41]
SA_DQS#[4]
SA_DQ[42]
SA_DQS#[5]
SA_DQ[43]
SA_DQS#[6]
SA_DQ[44]
SA_DQS#[7]
A
AB3
AA3
W10
AK3 M_CS#0
AL3 M_CS#1
AG1
AH1
OUT
OUT
AH3 M_ODT0
AG3 M_ODT1
AG2
AH2
OUT
OUT
C4
M_A_DQS0_DN
G6 M_A_DQS1_DN
J3
M_A_DQS2_DN
M6 M_A_DQS3_DN
AL6 M_A_DQS4_DN
AM8 M_A_DQS5_DN
AR12 M_A_DQS6_DN
AM15 M_A_DQS7_DN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
24
24
24
24
24
24
24
24
24
24
24
24
SA_DQ[48]
SA_DQ[49]
SA_DQS[0]
SA_DQ[50]
SA_DQS[1]
SA_DQ[51]
SA_DQS[2]
SA_DQ[52]
SA_DQS[3]
SA_DQ[53]
SA_DQS[4]
SA_DQ[54]
SA_DQS[5]
SA_DQ[55]
SA_DQS[6]
SA_DQ[56]
SA_DQS[7]
D4
M_A_DQS0_DP
F6
M_A_DQS1_DP
K3
M_A_DQS2_DP
N6
M_A_DQS3_DP
AL5 M_A_DQS4_DP
AM9 M_A_DQS5_DP
AR11 M_A_DQS6_DP
AM14 M_A_DQS7_DP
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
24
24
24
24
24
24
24
24
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
M_B_DQ<0>
M_B_DQ<1>
M_B_DQ<2>
M_B_DQ<3>
M_B_DQ<4>
M_B_DQ<5>
M_B_DQ<6>
M_B_DQ<7>
M_B_DQ<8>
M_B_DQ<9>
M_B_DQ<10>
M_B_DQ<11>
M_B_DQ<12>
M_B_DQ<13>
M_B_DQ<14>
M_B_DQ<15>
M_B_DQ<16>
M_B_DQ<17>
M_B_DQ<18>
M_B_DQ<19>
M_B_DQ<20>
M_B_DQ<21>
M_B_DQ<22>
M_B_DQ<23>
M_B_DQ<24>
M_B_DQ<25>
M_B_DQ<26>
M_B_DQ<27>
M_B_DQ<28>
M_B_DQ<29>
M_B_DQ<30>
M_B_DQ<31>
M_B_DQ<32>
M_B_DQ<33>
M_B_DQ<34>
M_B_DQ<35>
M_B_DQ<36>
M_B_DQ<37>
M_B_DQ<38>
M_B_DQ<39>
M_B_DQ<40>
M_B_DQ<41>
M_B_DQ<42>
M_B_DQ<43>
M_B_DQ<44>
M_B_DQ<45>
M_B_DQ<46>
M_B_DQ<47>
M_B_DQ<48>
M_B_DQ<49>
M_B_DQ<50>
M_B_DQ<51>
M_B_DQ<52>
M_B_DQ<53>
M_B_DQ<54>
M_B_DQ<55>
M_B_DQ<56>
M_B_DQ<57>
M_B_DQ<58>
M_B_DQ<59>
M_B_DQ<60>
M_B_DQ<61>
M_B_DQ<62>
M_B_DQ<63>
C9
A7
D10
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K10
K9
J9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
SB_CLK#[0]
SB_CKE[0]
SB_DQ[0]
SA_MA[0]
SA_DQ[62]
SA_MA[1]
SA_DQ[63]
SA_MA[2]
SA_MA[6]
AE10
AF10
V6
SA_MA[7]
SA_BS[0]
SA_MA[8]
SA_BS[1]
SA_MA[9]
SA_BS[2]
AE8
AD9
AF9
SA_CAS#
SA_MA[13]
SA_RAS#
SA_MA[14]
SA_WE#
SA_MA[15]
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_A_A<0>
M_A_A<1>
M_A_A<2>
M_A_A<3>
M_A_A<4>
M_A_A<5>
M_A_A<6>
M_A_A<7>
M_A_A<8>
M_A_A<9>
M_A_A<10>
M_A_A<11>
M_A_A<12>
M_A_A<13>
M_A_A<14>
M_A_A<15>
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_CLK[1]
SB_CLK#[1]
SB_CKE[1]
RSVD_TP[12]
RSVD_TP[13]
AA9
AA7
R6
RSVD_TP[15]
RSVD_TP[16]
SB_CS#[0]
SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]
SB_ODT[0]
SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]
SB_DQ[37]
SB_DQS#[0]
SB_DQ[38]
SB_DQS#[1]
SB_DQ[39]
SB_DQS#[2]
SB_DQ[40]
SB_DQS#[3]
SB_DQ[41]
SB_DQS#[4]
SB_DQ[42]
SB_DQS#[5]
SB_DQ[43]
SB_DQS#[6]
SB_DQ[44]
SB_DQS#[7]
AA10
AB8
AB9
25
25
25
D
AD3
AE3
AD6
AE6
M_CS#2
M_CS#3
OUT
OUT
25
25
AE4
AD4
AD5
AE5
M_ODT2
M_ODT3
OUT
OUT
25
25
D7
F3
K6
N3
AN5
AP9
AK12
AP15
M_B_DQS0_DN
M_B_DQS1_DN
M_B_DQS2_DN
M_B_DQS3_DN
M_B_DQS4_DN
M_B_DQS5_DN
M_B_DQS6_DN
M_B_DQS7_DN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
25
25
25
25
25
25
25
25
C7
G3
J6
M3
AN6
AP8
AK11
AP14
M_B_DQS0_DP
M_B_DQS1_DP
M_B_DQS2_DP
M_B_DQS3_DP
M_B_DQS4_DP
M_B_DQS5_DP
M_B_DQS6_DP
M_B_DQS7_DP
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
25
25
25
25
25
25
25
25
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_B_A<0>
M_B_A<1>
M_B_A<2>
M_B_A<3>
M_B_A<4>
M_B_A<5>
M_B_A<6>
M_B_A<7>
M_B_A<8>
M_B_A<9>
M_B_A<10>
M_B_A<11>
M_B_A<12>
M_B_A<13>
M_B_A<14>
M_B_A<15>
C
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQS[0]
SB_DQ[50]
SB_DQS[1]
SB_DQ[51]
SB_DQS[2]
SB_DQ[52]
SB_DQS[3]
SB_DQ[53]
SB_DQS[4]
SB_DQ[54]
SB_DQS[5]
SB_DQ[55]
SB_DQS[6]
SB_DQ[56]
SB_DQS[7]
B
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_MA[0]
SB_DQ[62]
SB_MA[1]
SB_DQ[63]
SB_MA[2]
SB_BS[0]
SB_MA[7]
SB_BS[1]
SB_MA[8]
SB_BS[2]
SB_MA[9]
SB_MA[12]
M_B_CAS#
M_B_RAS#
M_B_WE#
OUT
OUT
OUT
SB_DQ[46]
SB_MA[11]
OUT
OUT
OUT
M_CLK_DDR3_DP
M_CLK_DDR3_DN
M_CKE3
SB_DQ[45]
SB_MA[10]
25
25
25
AE1
AD1
R10
AA1
AB1
T10
RSVD_TP[14]
SB_MA[6]
M_B_BS0
M_B_BS1
M_B_BS2
25
25
25
AB2
AA2
T9
RSVD_TP[11]
SB_MA[5]
OUT
OUT
OUT
OUT
OUT
OUT
SB_DQ[3]
SB_MA[4]
25
25
25
M_CLK_DDR2_DP
M_CLK_DDR2_DN
M_CKE2
SB_DQ[2]
SB_MA[3]
SA_DQ[61]
AE2
AD2
R9
SB_DQ[1]
SA_DQ[60]
SA_MA[12]
M_A_CAS#
M_A_RAS#
M_A_WE#
AB4
AA4
W9
SA_DQ[47]
SA_MA[11]
OUT
OUT
OUT
OUT
OUT
OUT
24
24
24
SA_DQ[46]
SA_MA[10]
24
24
24
AA5 M_CLK_DDR1_DP
AB5 M_CLK_DDR1_DN
V10 M_CKE1
SA_DQ[45]
SA_MA[5]
M_A_BS0
M_A_BS1
M_A_BS2
24
24
24
SA_DQ[3]
SA_MA[4]
OUT
OUT
OUT
OUT
OUT
OUT
SA_DQ[2]
SA_MA[3]
24
24
24
AB6 M_CLK_DDR0_DP
AA6 M_CLK_DDR0_DN
V9
M_CKE0
SA_DQ[1]
DDR SYSTEM MEMORY A
D
M_A_DQ<0>
M_A_DQ<1>
M_A_DQ<2>
M_A_DQ<3>
M_A_DQ<4>
M_A_DQ<5>
M_A_DQ<6>
M_A_DQ<7>
M_A_DQ<8>
M_A_DQ<9>
M_A_DQ<10>
M_A_DQ<11>
M_A_DQ<12>
M_A_DQ<13>
M_A_DQ<14>
M_A_DQ<15>
M_A_DQ<16>
M_A_DQ<17>
M_A_DQ<18>
M_A_DQ<19>
M_A_DQ<20>
M_A_DQ<21>
M_A_DQ<22>
M_A_DQ<23>
M_A_DQ<24>
M_A_DQ<25>
M_A_DQ<26>
M_A_DQ<27>
M_A_DQ<28>
M_A_DQ<29>
M_A_DQ<30>
M_A_DQ<31>
M_A_DQ<32>
M_A_DQ<33>
M_A_DQ<34>
M_A_DQ<35>
M_A_DQ<36>
M_A_DQ<37>
M_A_DQ<38>
M_A_DQ<39>
M_A_DQ<40>
M_A_DQ<41>
M_A_DQ<42>
M_A_DQ<43>
M_A_DQ<44>
M_A_DQ<45>
M_A_DQ<46>
M_A_DQ<47>
M_A_DQ<48>
M_A_DQ<49>
M_A_DQ<50>
M_A_DQ<51>
M_A_DQ<52>
M_A_DQ<53>
M_A_DQ<54>
M_A_DQ<55>
M_A_DQ<56>
M_A_DQ<57>
M_A_DQ<58>
M_A_DQ<59>
M_A_DQ<60>
M_A_DQ<61>
M_A_DQ<62>
M_A_DQ<63>
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
DDR SYSTEM MEMORY B
SA_CLK[0]
SA_CLK#[0]
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
1
SB_CAS#
SB_MA[13]
SB_RAS#
SB_MA[14]
SB_WE#
SB_MA[15]
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
A
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
INVENTEC
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
TITLE
MODEL,PROJECT,FUNCTION
CPU -
SIZE
A3
CHANGE by
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
XXX
3
DATE
21-OCT-2002
2
CODE
CS
3
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
19
69
of
1
X01
8
7
07dc0c0702112402d1001dc1f80075b9
6
5
4
3
2
1
F
F
PVCORE
VCC17
VCC18
VCC19
VCC20
VCC21
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCC22
VCCIO21
VCC23
VCCIO22
VCC24
VCCIO23
VCC25
VCCIO24
1
22UF_6.3V_5
2
C4572
1
2
C4571
1
2
1
2
C4556
1
2
C4550
1
2
C4545
1
2
C4540
1
2
1
2
C4530
1
2
1
22UF_6.3V_5
VCCIO14
VCC16
22UF_6.3V_5
VCCIO13
VCC15
22UF_6.3V_5
C4570
VCC14
22UF_6.3V_5
VCCIO12
22UF_6.3V_5
VCC13
22UF_6.3V_5
VCCIO11
22UF_6.3V_5
VCC12
22UF_6.3V_5
C4535
VCCIO10
PEG AND DDR
VCCIO9
VCC11
22UF_6.3V_5
VCCIO8
VCC10
C4518
VCCIO6
VCCIO7
VCC9
2
VCCIO5
VCC7
VCC8
22UF_6.3V_5
VCCIO4
VCC6
1
VCCIO3
VCC5
C4513
VCCIO2
VCC4
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
C4501
VCC3
VCCIO1
2
POWER
VCC2
E
VCC26
VCC37
VCCIO35
VCC38
VCCIO36
VCC39
VCCIO37
VCC40
VCCIO38
VCC41
VCCIO39
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
VCCIO40
J23
VCC27
VCCIO25
VCC28
VCCIO26
VCC29
VCCIO27
VCC30
VCCIO28
VCCIO29
VCC31
VCC32
VCCIO30
VCC33
VCCIO31
VCC34
VCCIO32
VCC35
VCCIO33
VCC36
VCCIO34
VCC42
VCC43
VCC44
D
VCC45
VCC46
VCC53
P1V05S_CPU
1
VCC52
2
VCC54
R4506
VCC55
VCC56
VCC57
VCC58
VCC60
VCC61
1
SVID
VCC59
VIDALERT#
VCC62
VIDSCLK
VCC63
VIDSOUT
AJ29 H_CPU_SVIDALRT#
AJ30 H_CPU_SVIDCLK
AJ28 H_CPU_SVIDDAT
R4512
VCC51
R4509
R4510
R4511
1
1
1
75_1%_2
VCC50
2
VCC49
130_1%_2
VCC47
VCC48
CORE SUPPLY
VR_SVID_ALERT#
VR_SVID_CLK
VR_SVID_DATA
2 43_5%_2
2 0_5%_2
2 0_5%_2
OUT
OUT
OUT
13
13
13
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
C
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
PVCORE
VCC80
VCC89
VCC90
VCC_SENSE
VSS_SENSE
AJ35
AJ34
VCC91
VCC93
VCCIO_SENSE
VCC94
VSS_SENSE_VCCIO
R4505
VCC92
B10
A10
2
VCC95
VCC96
VCCSENSE
VSSSENSE
R4507
VCC99
2
VCC100
13
13
OUT
OUT
9
9
P1V05S_CPU
VCC97
VCC98
OUT
OUT
10_1%_2
VCC88
2
VCC86
VCC87
1
VCC85
R4504
VCC84
1
1
VCC83
100_1%_2
VCC82
100_1%_2
VCC81
SENSE LINES
1
2
10uF_6.3V_5
10uF_6.3V_5
1
22UF_6.3V_5
C4539
1
2
1
2
C4534
B
22UF_6.3V_5
2
C
C4559
1
2
10uF_6.3V_5
D
C4552
1
2
10uF_6.3V_5
1
2
1
22UF_6.3V_5
C4560
10uF_6.3V_5
10uF_6.3V_5
C4547
C4529
1
2
1
2
C4524
22UF_6.3V_5
2
1
2
10uF_6.3V_5
C4564
C4542
1
2
10uF_6.3V_5
1
22UF_6.3V_5
C4565
10uF_6.3V_5
2
2
10uF_6.3V_5
1
1
1
2
C4566
C4503
C4508
C4519
C4514
2
22UF_6.3V_5
1
2
1
22UF_6.3V_5
C4509
C4504
22UF_6.3V_5
2
E
VCC1
22UF_6.3V_5
P1V05S_CPU
CN4500
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
10_1%_2
1
R4508
2
B
VCC_SENSE_VCCIO
VSS_SENSE_VCCIO
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
A
A
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CPU4
8
7
07dc0c0702112402d1001dc1f80075b9
CHANGE by
6
5
4
3
XXX
DATE
21-OCT-2002
2
SIZE
CODE
C
CS
DOC.NUMBER
REV
1310xxxxx-0-0
SHEET
20
1
X01
of
69
