MOSFET MODELING FOR VLSI SIMULATION Theory and Practice docx

MOSFET
MODELING
FOR
VLSI SIMULATION
Theory
and Practice
International Series on Advances in Solid State Electronics and Technology
Founding
Editor:
Chih-Tang Sah
(ASSET)
Published:
Modern Semiconductor Quantum Physics
by
Li Ming-Fu
Topics in Growth and Device Processing of
III-V
Semiconductors
by
Stephen John Pearton, Cammy R. Abernathy
&
Fan Ren
Ionizing Radiation Effects in MOS Oxides
by
Timothy
R.
Oldham
Forthcoming.
MOSFET Modeling for Circuit Analysis and Design
by

Carlos Galup-Montoro
&
Marcio Cherem Schneider
The Physics and Modeling
of
MOSFETS:
Surface-Potential Model HiSIM
by
Mitiko Miura-Mattausch, Hans Jurgen Mattausch
&
Tatsuya Ezaki
BSIM4: Theory and Engineering of MOSFET Modeling for
IC
Simulation
by
Weidong Liu
&
Chenming Hu
ASSET
MOSFET MODELING
FOR
VLSl
SIMULATION
Theory and
Practice
Narain Arora
Cadence
Design
Systems,
USA

1;
World
Scientific
NEW JERSEY
*
LONDON
-
SINGAPORE
*
BElJlNG SHANGHAI
*
HONG KONG
*
TAIPEI
*
CHENNAI
International series on Advances in solid state Electronics and Technology
Founding Editor: Chih-Tang sah
Published by
World Scientific Publishing Co. Re. Ltd.
5
Toh Tuck Link, Singapore 596224
USA
ofice:
27 Warren Street, Suite 401-402, Hackensack, NJ 07601
UK
ofice:
57 Shelton Street, Covent Garden, London WC2H 9HE
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A

catalogue record for this book is available
from
the British Library.
MOSFET MODELING FOR VLSI SIMULATION
Theory and Practice
International Series on Advances
in
Solid State Electronics and Technology
Copyright
0
2007 by World Scientific Publishing Co. Pte. Ltd.
All
rights reserved. This
book,
or parts there% my not be reproduced in any form or by any means,
electronic or mechanical, including photocopying, recording or any information storage and retrieval
system now known or to be invented, without written permission from the Publisher.
For photocopying of material in this volume, please pay a copying fee through the Copyright
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ISBN-13 978-981-256-862-5
ISBN-
10
98
1

-256-862-X
Disclaimer:
This book was prepared by the authors. Neither the Publisher nor its Series Editor
thereof, nor any of their employees, assumes any legal liability or responsibility for the accuracy,
completeness, or usefulness of any information. The contents, views, and opinions of the authors
expressed herein do not necessarily state or reflect those of the Publisher, its Series Editor, and their
employees.
Printed
in
Singapore
by
World Scientific Printers
(S)
Pte
Ltd
In
the loving memory
of
my parents
Hukamdevi and Guranditta Arora
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Foreword
The purpose of this compact modeling monograph series is to provide an archival
reference
on
each specific MOS transistor compact model as described by the originators or the
veterans of each compact model. The monograph idea came about when this editor was looking
into the literature to prepare for a keynote address, invited by the Founder of the Workshop on
Compact Modeling, Professor Xing Zhou of Nanyang Technology University, and his program
committee, to be presented at its

4Ih
Workshop on May 10, 2005. The topic was on the history of
MOS
transistor compact modeling, a subject this editor could not find a reference or book that
provided the descriptions of each of the dozen or more MOS transistor compact models, which
had been extensively developed for the first-generation computer-aided circuit design
applications during 1995-2005, such as the use of the Berkeley BSlM and SPICE. A second
purpose
is
to serve as textbooks for graduate students and reference books for practicing
engineers, to rapidly distribute the detailed design methodologies and underlying physics in
order to meet the ever faster advances in the design of silicon semiconductor
MOS
and bipolar-
junction-transistor integrated circuits, which contain hundreds or thousands of transistors per
circuit or circuit function.
I
am especially thankful
to
the authors of the four startup monograph
volumes who concurred with me and agreed
to
take up the chore to write their books in the very
short time of less than six months in order
to
be published in one year, which we try as a rapid
response
to
document the latest advances. It is also the objective of this monograph series to
provide timely updates via website exchanges between the readers and authors, for public

distribution, and for new editions when sufficient materials are accummulated by the authors.
We are especially indebted
to
Dr. Narain Arora who agreed to allow
us
to reprint his 1993
classic, first published by Springer-Verlag, Wien, New York, as the lead of these initial four
monographs. Dr. Arora’s book was the first textbook and also reference book on MOS transistor
modeling.
It
has since educated tens of thousands of practicing engineers and graduate
students on the developments of compact MOS transistor models and their device physics
bases, which have provided rapid computations of accurate MOS transistor characteristics. The
physics base makes Arora’s book timeless, for the underlying physics on how the transistor
works and how it should be modeled by equivalent circuits, does not change with time, only
details from adding more physical phenomena as the technology advances.
I
would like
to
thank all the WSPC editors and this monograph volume’s copy editor Mr.
Tjan Kwang Wei at Singapore, led by Dr. Yubing Zhai at New Jersey, for their and her timely
efforts, and Professor Kok-Khoo Phua, Founder and Chairman of WSPC, for his support, all of
which have made it possible to attain a less-than-one-year turn-around time to print each
monograph volume, in order to meet our intention of responding to the rapid advances of the
state of the art of computer-aided integrated circuit design.
Chih-Tang Sah
Gainesville, San Diego, Singapore, Beijing and Xiaman.
October
1,
2006

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Preface
Metal Oxide Semiconductor
(MOS)
transistors are the basic building block
of MOS integrated circuits
(IC).
Very Large Scale Integrated (VLSI) circuits
using
MOS
technology have emerged as the dominant technology in the
semiconductor industry. Over the past decade, the complexity of
MOS
IC's
has increased at an astonishing rate. This is realized mainly through the
reduction of MOS transistor dimensions in addition to the improvements
in processing. Today VLSI circuits with over
3
million transistors on a
chip, with effective or electrical channel lengths of
0.5
microns, are in volume
production. Designing such complex chips is virtually impossible without
simulation tools which help to predict circuit behavior before actual circuits
are fabricated. However, the utility
of
simulators as a tool for the design
and analysis of circuits depends
on
the adequacy of the device models used

in the simulator. This problem is further aggravated by the technology
trend towards smaller and smaller device dimensions which increases the
complexity of the models.
There is extensive literature available
on
modeling these short channel
devices. However, there is a lot of confusion too. Often it is not clear what
model to use and which model parameter values are important and how
to determine them. After working over
15
years in the field of semiconductor
device modeling,
I
have felt the need for a book which can
fill
the gap
between the theory and the practice
of
MOS transistor modeling. This
book is an attempt
in
that direction.
The book deals with the MOS Field Effect transistor (MOSFET) models
that are derived from basic semiconductor theory. Various models are
developed ranging from simple to more sophisticated models that take into
account
new physical
effects
observed in submicron devices used in today's
MOS VLSI technology. The assumptions used to arrive at the models are

emphasized
so
that the accuracy
of
the model
in
describing the device
characteristics are clearly understood. Due to the importance of designing
reliable circuits, device reliability models have also been covered. Under-
standing these models is essential when designing circuits for state of the
art
MOS
IC's.
X
Preface
Extracting the device model parameter values from device data is a very
important part of device modeling which is often ignored. In this book the
first detailed presentation of model parameter determination
for
MOS
models is given. Since the device parameters vary due to inherent processing
variations, how to arrive at worst case design parameters which ensure
maximum yield is covered in some detail.
Presentation
of
the material is such that even an undergraduate student
not well familiar with semiconductor device physics can understand the
intricacies of MOSFET modeling. Chapter
1
deals with the overview of

various aspects of device modeling for circuit simulators. Chapter
2
is a
brief but complete (for understanding MOSFET models) review
of
semiconductor device physics and
pn
junction theory. The MOS transistor
characteristics as applied
to
current MOS technologies are discussed in
Chapter
3.
The theory of MOS capacitors that is essential for the under-
standing of MOS models are covered in Chapter
4.
Different MOSFET
models, such as threshold voltage, DC (steady-state), AC and reliability
models are the topic of discussion in Chapters
5,
6,
7
and
8,
respectively.
Chapters
9
and
10
deal with data measurements and model parameter

extraction. The diode and MOSFET models implemented in Berkeley
SPICE, a defacto industry standard circuit simulator, are covered in
Chapter
11.
Finally, the statistical variation of model parameters due to
process variations are covered in Chapter
12.
It is my sincere hope that this book will serve as a technical source in the
area of MOSFET modeling for state of the art MOS technology for both
practicing device and circuit engineers and engineering students interested
in
the said area.
During the writing of this book
I
have received much help and
encouragement, directly or indirectly, from my colleagues. First I would
like to express my gratitude to the management of Digital Equipment
Corporation, namely Dr. Rich Hollingsworth (Corporate Consultant) and
Dr. Llanda Richardson (Consultant) for their encouragement and assistance
in writing this book. I am deeply indebted to Dr. F. Fox, Dr.
D.
Ramey,
and Mr.
K. Mistry for their excellent work in careful reading of many
of
the chapters in the first draft
of
the manuscript and giving their critical
comments. I am also indebted to Drs.
R.

Rios,
J.
Huang and Mr. K. Roal
for this invaluable help during completion of this work. I would like to
express my thanks to the large number of my colleagues, within and outside
my organization, who helped in preparing the manuscript in one way or
the other, namely Drs. A. Bose, D. Bell, B. Doyle,
J.
Faricelli, A. Enver,
K.
L.
Kodandpani,
L.
Richardson,
A.
R.
Shanker, Messers
L.
Bair,
N.
Khalil,
L.
Gruber, Prof.
S.
C. Jain (former Director
SPL),
Prof. D. Antoniadis
(MIT), Prof.
G.
Gildenblat (Penn. State), Prof.

D.
J.
Roulston
(UW),
Dr.
R.
Chadha (AT
&
T), and Dr. M. Sharma (Motorola). This acknowledgment
will not be complete without the name of Dr. Risal Singh, my old colleague
Preface
XI
and close friend, who in spite of his busy schedule, spent many many hours
to help me bring this book to the present form.
Finally,
I
would like to express my deep gratitude to my family. This book
would not have been possible without their support. The understanding
of
my wife Suprabha, and the cooperation of my
son
Surendra and daughter
Shilpa all were indispensable in making this book a reality.
April 11, 1992
Shrewsbury,
MA.
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Contents
List
of

Symbols
XIX
Acronyms
XXIV
1
Overview 1
1.1 Circuit Design with MOSFETs 3
1.2 MOSFET Modeling
5
1.3 Model Parameter Determination 9
1.4 Interconnect Modeling 10
1.5 Subjects Covered 11
References 11
2 Review
of
Basic Semiconductor and
pn
Junction Theory
15
2.1 Energy Band Model 15
2.2 Intrinsic Semiconductor 17
2.2.1 Fermi level
19
2.3 Extrinsic or Doped Semiconductor 21
2.3.1 Generation-Recombination 25
2.3.2 Quasi-Fermi Level 27
2.4.1 Carrier Mobility 28
2.4.2 Resistivity and Sheet Resistance 33
2.4.3 Transport Equations
36

2.4.4 Continuity Equation 37
2.4.5 Poisson’s Equation 38
2.5
pn
Junction at Equilibrium 39
2.5.1 Built-in Potential 42
2.5.2 Depletion Width 43
2.6.1 Limitation of the Diode Current Model 48
2.6.2 Bulk Resistance 51
2.6.3 Junction Breakdown Voltage 52
2.4 Electrical Conduction 28
2.6 Diode Current-Voltage Characteristics 46
XIV
Contents
2.7 Diode Dynamic Behavior 53
2.7.1 Junction Capacitance 53
2.7.2 Diffusion Capacitance 56
2.7.3 Small Signal Conductance 57
2.8 Real
pn
Junction 58
2.9 Diode Circuit Model 61
2.10 Temperature Dependent Diode Model Parameters
64
2.10.1 Temperature Dependence of
I,
2.10.2 Temperature Dependence of
4bi
2.10.3 Temperature Dependence of
Cjo

64
66
66
References 67
3
MOS
Transistor Structure and Operation 69
3.1 MOSFET Structure 69
3.2 MOSFET Characteristics 73
3.2.1 Punchthrough
8
1
3.2.2 MOSFET Capacitances 82
3.2.3 Small-Signal Behavior 84
3.2.4 Device Speed 86
3.3 MOSFET Scaling 87
3.4 Hot-Carrier Effects
90
3.5 VLSI Device Structures 93
3.5.1 Gate Material 93
3.5.2 Nonuniform Channel Doping 94
3.5.3 Source-Drain Structures 95
3.5.4 Device Isolation 98
3.5.5 CMOS Process 99
3.6 MOSFET Parasitic Elements 102
3.6.1 Source-Drain Resistance 102
3.6.2 Source/Drain Junction Capacitance 108
3.6.3 Gate Overlap Capacitances 109
3.7 MOSFET Length and Width Definitions 113
3.7.1 Effective or Electrical Channel Length 113

3.7.2 Effective or Electrical Channel Width 114
3.8 MOSFET Circuit Models 115
References 1 18
4 MOS Capacitor 121
4.1 MOS Capacitor with
No
Applied Voltage 121
4.1.1 Work Function 123
4.1.2 Oxide Charges 127
4.1.3 Flat Band Voltage 131
4.2.1 Accumulation 135
4.2 MOS Capacitor at Non-Zero Bias 133
Contents
xv
4.2.2 Depletion 135
4.2.3 Inversion 138
4.3.1 Low Frequency C-V Plot 153
4.3.2 High Frequency C-V Plot 154
4.3.3 Deep Depletion C-V Plot 155
4.4 Deviation from Ideal C-V Curves 156
4.5 Anomalous C-V Curve (Polysilicon Depletion Effect) 159
4.6 MOS Capacitor Applications 161
4.7 Nonuniformly Doped Substrate and Flat Band Voltage 162
4.3 Capacitance of MOS Structures 147
4.7.1 Temperature Dependence
of
Vfb
163
References 165
5

Threshold Voltage 167
5.1 MOSFET with Uniformly Doped Substrate 167
5.2 Nonuniformly Doped MOSFET 177
5.2.1 Enhancement Type Device 179
5.2.2 Depletion Type Device 190
5.3
Threshold Voltage Variations with Device Length and
Width 194
5.3.1 Short-Channel Effect 195
5.3.2 Narrow-Width Effect 205
5.3.3 Drain Induced Barrier Lowering (DIBL) Effect 210
5.3.4 Small-Geometry Effect 219
5.4 Temperature Dependence
of
the Threshold voltage 221
References 225
6 MOSFET DC Model 230
6.1 Drain Current Calculations 230
6.2 Pao-Sah Model 235
6.3 Charge-Sheet Model 238
6.4
Piece-Wise Drain Current Model for Enhancement
Devices 243
6.4.1 First Order Model 244
6.4.2 Bulk-Charge Model 251
6.4.3 Square-Root Approximation 253
6.4.4
6.4.5 Subthreshold Region Model 259
6.4.6 Limitations of the Model 267
Drain Current Equation with Square-Root

Approximation 257
6.5 Drain Current Model for Depletion Devices 270
6.6 Effective Mobility 276
6.6.1 Mobility Degradation Due to the Gate Voltage 277
6.6.2 Mobility Degradation Due to the Drain Voltage 284
XVI
Contents
6.7 Short-Geometry Models 287
6.7.1 Linear Region Model 289
6.7.2 Saturation Voltage 291
6.7.3 Saturation Region-Channel Length Modulation 295
6.7.4 Subthreshold Model 305
6.7.5 Continuous Model 307
6.8 Impact of Source-Drain Resistance
on
Drain Current 310
6.9 Temperature Dependence of the Drain Current 313
6.9.1 Temperature Dependence of Mobility 314
References
3
18
7 Dynamic Model 325
7.1 Intrinsic Charges and Capacitances 325
7.1.1 Meyer Model 328
7.1.2 Drawbacks of the Meyer Model 334
7.2 Charge-Based Capacitance Model 337
7.3 Long-Channel Charge Model 340
7.4 Short-Channel Charge Model 352
7.5 Limitations of the Quasi-Static Model 359
7.6 Small-Signal Model Parameters 360

7.3.1 Capacitances 347
7.4.1 Capacitances 356
References 364
8 Modeling Hot-Carrier Effects 366
8.1 Substrate Current Model 367
8.2 Gate Current Model 374
8.3 Correlation
of
Gate and Substrate Current 382
8.4 Mechanism
of
MOSFET Degradation 383
8.5 Measure of Degradation-Device Lifetime 388
8.6 Impact
of
Degradation
on
Circuit Performance 394
8.7 Temperature Dependence of Device Degradation 396
References 398
9 Data Acquisition and Model Parameter Measurements 402
9.1 Data Acquisition 403
9.1.1 Data for DC Models 410
9.1.2 Data for AC Models 414
9.1.3
MOS
Capacitor C-V Measurement 418
9.2 Gate-Oxide Capacitance Measurement 421
9.2.1 Optical Method-Ellipsometry 421
9.2.2 Electrical Method 422

9.3.1 Capacitance-Voltage Method 428
9.3.2 DC Method 436
9.3 Measurement of Doping Profile in Silicon 427
Contents
XVII
9.4 Measurement
of
Threshold Voltage 438
9.5 Determination
of
Body Factor
y
443
9.6 Flat Band Voltage 445
9.7 Drain Induced Barrier Lowering (DIBL) Parameter 445
9.8 Determination
of
Subthreshold Slope 447
9.9 Carrier Inversion Layer Mobility Measurement 448
9.9.1 Split-CV Method 452
9.10 Determination
of
Effective Channel Length and Width
9.10.1 Drain Current Methods
of
Determination
AL
458
9.10.2 Capacitance Method of Determining
AL

468
9.10.3 Methods
of
Determining
AW
470
9.1 1 Determination
of
Drain Saturation Voltage 472
9.12 Measurement
of
MOSFET Intrinsic Capacitances
457
477
9.12.1 On-Chip Methods 477
9.12.2 Off-Chip Methods 481
9.13 Measurement
of
Gate Overlap Capacitance
9.14 Measurement of MOSFET Source/Drain Diode Junction
484
Parameters 489
9.14.1 Diode Saturation or Reverse Current
I,
489
9.14.2 Junction Capacitance 493
References 494
10 Model Parameter Extraction Using Optimization Method
501
10.1 Model Parameter Extraction 501

10.2 Basics Definitions in Optimization 504
10.3 Optimization Methods 510
10.3.1 Constrained Optimization 515
10.3.2 Multiple Response Optimization 518
10.4 Some Remarks on Parameter Extraction Using Optimization
Technique 521
10.5 Confidence Limits on Estimated Model Parameter 522
10.5.1 Examples
of
Redundant Parameters 527
10.6 Parameter Extraction Using Optimizer 53 1
10.6.1 Drain Current Model Parameter Extraction 532
10.6.2 MOSFET AC Model Parameter Extraction 533
References 534
11
SPICE Diode and MOSFET Models and Their Parameters 536
11.1 Diode Model 536
11.2 MOSFET Level 1 Model 542
11.2.1 DC Model 542
11.2.2 Capacitance Model 543
11.3 MOSFET Level 2 Model 548
11.3.1 DC Model 548
11.3.2 Capacitance Model 552
XVIII
Contents
11.4 MOSFET Level 3 Model 554
11.4.1 DC Model 554
11.5 MOSFET Level 4 Model 556
11.5.1 DC Model
556

11.5.2 Capacitance Model 559
11.6 Comparison
of
the Four MOSFET Models 559
References 561
12 Statistical Modeling and Worst-case Design Parameters 563
12.1 Methods of Generating Worst Case Parameters 564
12.2 Model Parameter Sensitivity 566
12.3 Statistical Analysis with Parameter Correlation 569
12.4 Factor Analysis 572
12.2.1 Principal Factor Method 567
12.3.1 Principal Component Analysis 571
12.4.1 Factor Rotation 574
12.4.2 Regression Models 574
12.5 Optimization Method 575
References 578
Appendix A. Important Properties of Silicon, Silicon Dioxide and Silicon
Nitride at 300K 580
Appendix B. Some Important Physical Constants at 300
K
581
Appendix C. Unit Conversion Factors 581
Appendix
D.
Magnitude Prefixes
Appendix E. Methods
of
Calculating
4s
from the Implicit

Eq.
(6.23) or
(6.30)
Appendix F. Charge Based MOSFET Intrinsic Capacitances 583
Appendix
G.
Linear Regression 587
Appendix
H.
Basic Statistical and Probability Theory
Appendix I. List of Widely Used Statistical Package Programs 599
58
1
588
Subject Index
600
List
of
Symbols
The following is list of symbols used in the text. This list excludes those
symbols which are used locally in a particular chapter.
Symbol Description Unit
Ionization constants cm-I
Ionization constants V/cm
Depletion region capacitance per unit area
F/cm2
Flat band capacitance per unit area F/cm2
Capacitance per unit area of a
MOS
capacitor F/cm2

Gate-to-channel capacitance per unit area F/cm2
Gate to bulk capacitance per unit area F/cm2
Gate to source overlap capacitance per unit F/cm
length
Gate to drain overlap capacitance per unit length F/cm
Gate to bulk overlap capacitance per unit length F/cm
Intrinsic gate to source capacitance
F
Intrinsic gate to drain capacitance
F
Intrinsic gate to bulk capacitance
F
pn
junction depletion capacitance F/cm2
Gate oxide capacitance per unit area F/cm2
Total gate oxide capacitance
(C,,WL)
F
Space charge capacitance per unit area F/cm
Interface state density charges/cm2
Electron Diffusivity or diffusion constant cm’/s
Hole Diffusivity or diffusion constant cm’/s
Ionized acceptor energy level eV
Ionized donor energy level eV
Energy level for the lower edge
of
the conduction eV
band
xx
List

of
Symbols
Symbol Description
Unit
Energy level for the upper edge
of
the valance
band
Energy gap of semiconductor
Intrinsic energy level
Fermi-energy or Fermi level
in
(n or p-type) bulk
silicon
Fermi-energy level in n-type Silicon
Fermi-energy level in p-type Silicon
Electric field in the space-charge region
Vertical or normal electric field in the channel
Lateral electric field in the channel
Critical field for the carrier velocity saturation
Effective vertical field
Electric field in the oxide
Electron quasi-Fermi energy
Hole quasi-Fermi energy
Carrier generation rate
Diode small-signal conductance
MOSFET small signal output conductance
MOSFET small signal transconductance
MOSFET small signal substrate
transconductance

Current in a diode or drain current in a
MOSFET
Gate current in a MOSFET
Substrate current in a MOSFET
Leakage current in a diode or source current
in a MOSFET
Drain to source current
Electron current density
Hole current density
Junction leakage current
Boltzmann constant
Effective or electrical channel length
Mask or drawn channel length
Extrinsic Debye length
Length near the drain end due to channel
length modulation
Electron effective mass
Hole effective mass
Electron rest mass
eV
eV
eV
eV
eV
eV
V/cm
V Jcm
V/cm
V Jcm
V/cm

V Jcm
eV
eV
S-l
AN
A/V
AJV
A/V
A
A
A
A
A
A/cm2
A/cm2
A
JK
Pn
Pm
cm
cm
g
g
g
List
of
Symbols
XXI
Symbol Description
Impurity (accepter) concentration in p-type

silicon
Impurity (donor) concentration in n-type
silicon
Impurity concentration in
(n
or p-type) bulk
silicon
Ionized acceptor impurity concentration
Ionized donor impurity concentration
Free electrons concentration
Intrinsic carrier concentration
Electrons concentration in p-type silicon
Free holes concentration
Hole concentration in n-type silicon
Magnitude
of
Electronic Charge
Oxide charge density at the interface
Bulk
(depletion) charge per unit area
Mobile (inversion) charge per unit area
Gate charge per unit area
Charge per unit area induced in the silicon
Total inversion charge
Total gate charge
Total source charge
Total drain charge
Intrinsic channel resistance
Drain resistance
Source resistance

Sum of the source and drain resistance
Subthreshold slope
Absolute temperature
Gate oxide thickness
Gate voltage
Channel to bulk potential
Bulk
to source voltage
Drain to source voltage
Gate to source voltage
gate to bulk voltage
(
V,,
-
'b,)
gate to drain voltage
(V,,
-
Vds)
Drain saturation voltage
Flat-band voltage
Threshold voltage
Thermal voltage
(kT/q)
Unit
cm-
cm-3
cm-3
cm-
cm-3

cmP3
cm-3
cm-
cm-3
cm-3
C
charges/cm2
C/cm
C/cm2
C/cm2
C/cm2
C
C
C
C
R
R
n
R
V/decade
f
v
V
V
V
V
V
v
V
v

V
V
XXII
List
of
Symbols
Symbol Description
-
~
Unit
%b
V
Vsat
W
Wm
X
tch
X
j
xn
x€J
xd
xdm
CI
Po
Y
6
AL
AW
z

€0,
Esi
8
PO
Peff
Pn
PP
PS
Peff
XS
Qrn
'ms
'b
Psr
P
Substrate bias V
Carrier velocity cmjsec
Carrier saturation velocity cm/sec
Effective or electrical channel width Pm
Mask or drawn channel width
Pm
Distance from Si-SiO, interface into silicon cm
Inversion layer thickness cm
Junction depth cm
Depletion width on n-side
of
a pn junction cm
Depletion width on p-side
of
a

pn
junction cm
Bulk depletion width in
a
MOS
capacitor or cm
MOSFET
Maximum depletion width in
a
MOS
cm
capacitor or MOSFET
Body factor term
(1
+
6y)
-
v-'
V-
'
Device gain
=
poco,
W/L
Body factor
~~&jCo,
v1/2
Square-root approximation factor in the bulk
charge
Qb

term
Difference between drawn and electrical channel
pm
length
(L,
-
L)
Difference between drawn and electrical
Pm
channel width
(W,
-
L)
Carrier life-time sec
Dielectric permittivity of SiO, Fjcm
Dielectric permittivity of silicon F/cm
The mobility degradation factor resulting
from the vertical field
Low
field channel mobility cm2/V.s
Effective channel mobility cm2/V.s
Electron mobility cm2/V.
s
Hole mobility cm2/V.s
MOSFET surface mobility cm2/V.s
Effective mobility due to gate and drain field cm2/V.s
Electron affinity for silicon eV
Metal (gate) work function eV
Gate to substrate work function difference eV
Electron potential barrier height

at
Si-SiO, eV
interface
Surface roughness scattering cm2/V.s
Space charge density C/cm
V-'
List
of
Symbols
XXIII
Symbol
PS
il
4
Description
Sheet resistance
channel length modulation factor
Electrostatic potential with respect to
intrinsic
level
Ei
Surface potential with respect to intrinsic
level
Ei
Built-in potential
of
a
pn
junction
Fermi potential in

(n
or p-type) bulk silicon
Electron quasi-Fermi potential (imref)
Hole quasi-Fermi potential (imref)
Unit
Q/O
VP1
v
V
V
eV
v
v
Acronyms
Symbol Description
CHE Channel Hot Electron
CLM Channel Length Modulation
CMOS Complementary Metal Oxide Semiconductor
c-v
Device Capacitance-Voltage Characteristics
DIBL Drain Induced Barrier Lowering
GCA Gradual Channel Approximation
IGFET
LDD
Lightly Doped Drain
LOCOS Localized Oxidation of Silicon
MOSFET
nMOST n-channel MOSFET
pMOST p-channel
MOSFET

ZTC
Insulated Gate Field Effect Transistor
Metal Oxide Semiconductor Field-Effect Transistor
MOSFET SourceIDrain
Zero Temperature Coefficient
SID