High Level Synthesis: from Algorithm to Digital Circuit- P2 pdf

Contributors xi
Rom´an Hermida
Facultad de Inform´atica, Universidad Complutense de Madrid, c/Prof. Jos´eGarc´ıa
Santesmases s/n, 28040 Madrid, Spain,
Niraj K. Jha
Department of Electrical and Engineering, Princeton University, Princeton, NJ
08544, USA,
Wei Jiang
AutoESL Design Technolgoies, Inc., 12100 Wilshire Blvd, Los Angeles, CA
90025, USA,
Ryan Kastner
Department of Electrical and Computer Engineering, University of California,
Santa Barbara, CA 93106, USA,
Vinod Kathail
Synfora, Inc., 2465 Latham Street, Suite # 300, Mountain View, CA 94040, USA,

Hyukmin Kwon
Samsung Electronics Co., Suwon, Kyunggi Province, South Korea,

Eric Martin
European University of Brittany – UBS, Lab-STICC, BP 92116, 56321 Lorient
Cedex, France,
Jos´e Manuel Mend´ıas
Facultad de Inform´atica, Universidad Complutense de Madrid, c/Prof. Jos´eGarc´ıa
Santesmases s/n, 28040 Madrid, Spain,
Michael Meredith
VP Technical Marketing, Forte Design Systems, San Jose, CA 95112, USA,

Mar´ıa Carmen Molina
Facultad de Inform´atica, Universidad Complutense de Madrid, c/Prof. Jos´eGarc´ıa
Santesmases s/n, 28040 Madrid, Spain,

Rishiyur S. Nikhil
Bluespec, Inc., 14 Spring Street, Waltham, MA 02451, USA,
Fr´ed´eric P´etrot
INPG-TIMA/SLS, 46 Avenue F´elix Viallet, 38031 Grenoble Cedex, France,

Patrice Quinton
ENS de Cachan, antenne de Bretagne, Campus de Ker Lann, 35 170 Bruz Cedex,
France,
xii Contributors
Sanjay Rajopadhye
Department of Computer Science, Colorado State University, 601 S. Howes St.
USC Bldg., Fort Collins, CO 80523-1873, USA,
Tanguy Risset
CITI – INSA Lyon, 20 avenue Albert Einstein, 69621, Villeurbanne, France,

Rafael Ruiz-Sautua
Facultad de Inform´atica, Universidad Complutense de Madrid, c/Prof. Jos´eGarc´ıa
Santesmases s/n, 28040 Madrid, Spain,
Benjamin Carrion Schafer
EDA R&D Center, Central Research Laboratories, NEC Corp., Kawasaki, Japan,

Eric Senn
European University of Brittany – UBS, Lab-STICC, BP 92116, 56321 Lorient
Cedex, France,
Li Shang
Department of Electrical and Computer Engineering, Queen’s University, Kingston,
ON, Canada K7L 3N6,
Pascal Urard
STMicroelectronics, Crolles, France,
Kazutoshi Wakabayashi

EDA R&D Center, Central Research Laboratories, NEC Corp., Kawasaki, Japan,

Gang Wang
Technology Innovation Architect, Intuit, Inc., 7535 Torrey Santa Fe Road,
San Diego, CA 92129, USA, Gang

Changqi Yang
AutoESL Design Technolgoies, Inc., 12100 Wilshire Blvd, Los Angeles, CA
90025, USA,
Joonhwan Yi
Samsung Electronics Co., Suwon, Kyunggi Province, South Korea,
,
Zhiru Zhang
AutoESL Design Technolgoies, Inc., 12100 Wilshire Blvd, Los Angeles, CA
90025, USA,
List of Web sites
Chapter 2
related to system level design, synthesis and verification. Our recent projects include
the SPARK parallelizing synthesis framework, SATYA verification framework. Ear-
lier work from the laboratory formed the technical basis for the SystemC initiative.
/>Chapter 3
Catapult Synthesis product information page
The home page for Catapult Synthesis on www.mentor.com, with links to product
datasheets, free software evaluation, technical publications, success stories, testimo-
nials and related ESL product information.
/>level synthesis/
Algorithmic C datatypes download page
The Algorithmic C arbitrary-length bit-accurate integer and fixed-point data types
allow designers to easily model bit-accurate behavior in their designs. The data types
were designed to approach the speed of plain C integers. It is no longer necessary to

compromise on bit-accuracy for the sake of speed or to explicitly code fixed-point
behavior using integers in combination with shifts and bit masking.
/>level synthesis/ac datatypes
Chapter 4
Synfora, Inc. is the premier provider of PICO family of algorithmic synthesis tools
to design complex application engines for SoCs and FPGAs. Synfora’s technology
helps to reduce design costs, dramatically speed IP development and verification,
xiii
MicroelectronicEmbedded Systrems Laboratory at UCSD hosts a number of projects
xiv List of Web sites
and reduce time-to-market. For the latest information on Synfora and PICO prod-
ucts, please visit
Chapter 5
More information on Cynthesizer from Forte Design Systems can be found at

Chapter 6
More information on AutoPilotTM from AutoESL Design Technologies can be
found at and />Chapter 7
Home Page for CyberWorkBench from NEC

Chapter 8
More information on Bluespec can be found at
Documentation, training materials, discussion forums, inquiries about Bluespec
SystemVerilog. />Open source hardware designs done by MIT and Nokia in Bluespec SystemVer-
ilog for H.264 decoder (baseline profile), OFDM transmitter and receiver, 802.11a
transmitter, and more.
Chapter 9
GAUT is an open source project at UEB-Lab-STICC. The software for this project
is freely available for download. It is provided with a graphical user interface, a
quick start guide, a user manual and several design examples. GAUT is currently

supported on Linux and Windows. GAUT has already been downloaded more than
200 times by people from industry and academia in 36 different countries. For more
information, please visit:
/>List of Web sites xv
Chapter 10
More information can be found on UGH from at UPMC-LIP6/SoC and INPG-
TIMA/SLS at />This web site contains introduction text, source code and tutorials (through CVS) of
the opensource Dysident framework that includes the UGH HLS tool.
Chapter 11
More information on Chapter 11 can be found at
/>Chapter 12
More information on MMAlpha can be found at
/>Chapter 13
More information Chapter 13 can be found on at
/>Chapter 14
More information on Chapter 14 can be found at
/>Chapter 15
More information on Chapter 15 can be found at
/>Chapter 1
User Needs
Pascal Urard, Joonhwan Yi, Hyukmin Kwon, and Alexandre Gouraud
Abstract One can see successful adoption in industry of innovative technologies
mainly in the cases where they provide acceptable solution to very concrete prob-
lems that this industry is facing. High-level synthesis promises to be one of the
solutions to cope with the significant increase in the demand for design productivity
beyond the state-of-the-art methodsand flows. It also offers an unparalleled possibil-
ity to explore the design space in an efficient way by dealing with higher abstraction
levels and fast implementation ways to prove the feasibility of algorithms and
enables optimisation of performances. Beyond the productivityimprovement, which
is of course very pertinent in the design practice, the system and SoC companies

are more and more concerned with their overall capability to design highly com-
plex systems providing sophisticated functions and services. High-level synthesis
may considerably contribute to maintain such a design capability in the context of
continuously increasing chip manufacturing capacities and ever growing customer
demand for function-rich products.
In this chapter three leading industrial users present their expectations with
regard to the high-level synthesis technology and the results of their experiments
in practical application of currently available HLS tools and flows. The users also
draw conclusions on the future directions in which they wish to see the high-level
synthesis evolves like multi-clock domain support, block interface synthesis, joint
optimisation of the datapath and control logic, integration of automated testing to
the generated hardware or efficient taking into account of the target implementation
technology for ASICs and FPGAs in the synthesis process.
Pascal Urard
STMicroelectronics
Joonhwan Yi and Hyukmin Kwon
Telecommunication R&D, Samsung Electronics Co., South Korea
Alexandre Gouraud
France Telecom R&D
P. Coussy and A. Morawiec (eds.) High-Level Synthesis.
c
 Springer Science + Business Media B.V. 2008
1
2 P. Ur ar d et al .
Keywords: High-level synthesis, Productivity, ESL, ASIC, SoC, FPGA, RTL,
ANSI C, C++, SystemC, VHDL, Verilog, Design, Verification, IP, TLM, Design
space exploration, Memory, Parallelism, Simulation, Prototyping
1.1 System Level Design Evolution and Needs for an IDM Point
of View: STMicroelectronics
1

Pascal Urard, STMicroelectronics
The complexity of digital integrated circuits has always increased from a technol-
ogy node to another. The designers often had to adapt to the challenge of providing
commercially acceptable solution with a reasonable effort. Many evolutions (and
sometimes revolutions) occurred in the past: back-end automation or logical syn-
thesis were part of those, enabling new area of innovation. Thanks to the increasing
integration factor offered by technology nodes, the complexity in latest SoC has
reached tens of millions of gates. Starting with 90 nm and bellow, RTL design flow
(Fig. 1.1) now shows its limits.
The gap between the productivity per designer and per year and the increasing
complexity of the SoC, even taking into account some really conservative number
of gates per technology node, lead to an explosion of the manpower for SoCs in the
coming technology node (Fig. 1.2).
There is a tremendous need for productivity improvement at design level. This
creates an outstanding opportunity for new design techniques to be adopted: design-
ers, facing this challenge, are hunger to progress and open to raise the level of
abstraction of the golden reference model they trust.
A new step is needed in productivity. Part of this step could be offered by ESLD:
Electronics System Level Design. This includes HW/SW co-design and High-Level
Synthesis (HLS).
HW/SW co-design deployment has occurred few years ago, thanks to SystemC
and TLM coding. HLS however is new and just starting to be deployed. Figure 1.3
shows the basis of STMicroelectronics C-level design methodology. A bit-accurate
reference model is described at functional level in C/C++ using SystemC or equiv-
alent datatypes. In the ideal case, this C-level description has to be extensively
validated using a C-level testbench, in the functional environment, in order to
become the golden model of the implementation flow. This is facilitated by the sim-
ulation speed of this C model, usually faster than other kinds of description. Then,
taking into account technology constraints, the HLS tool produces an RTL represen-
tation, compatible with RTL-to-GDS2 flow. Verification between C-level model and

RTL is done either thanks to sequential equivalence checking tools, or by extensive
simulations. Started in 2001 with selected CAD-vendors, the research on new flows
1
(C) Pascal Urard, STMicroelectronics Nov. 2006. Extracted for P. Urard presentation at ICCAD,
Nov. 2006, San Jos´e, California, USA.
1 User Needs 3
Gates
P&R
+
Layout
System
System
Analysis
Analysis
Algorithm
GDS2
RTL
code
Design
model
Target
Target
Asic
Logic
Synthesis
Technology files
(Standard Cells + RAM cuts)
Formal proof
(equivalence
checking)

Fig. 1.1 RTL Level design flow
~300~150~75~60~43~40~40~80~40~10
200k200k200k125k91k56k40k9k6k4k
60M30M15M7.5M4M2.2M1.5M750k250K50K
1.2M600k300k150k80k45k30k15k5k1k
324565900.130.180.250.350.50.7
Men / Years per 50 mm2 Die
#Gates per Designer per year
#Gates / Die (50mm2)
conservative numbers
2010200820062004200220001998100619941991
 It is urgent to win some productivity
Fig. 1.2 Design challenges for 65 nm and below
Fig. 1.3 High level synthesis flow
4 P. Ur ar d et al .
Design Productivity vs Manual RTL (base 1)
1X
5X
1/2X
t
%
Behavioral IP Reuse, further improves design productivity
10X
Fig. 1.4 Learning curve
has allowed some deployment of HLS tools within STMicroelectronics starting in
2004, with early division adopters. We clearly see in 2007 an acceleration of the
demand from designers. Those designers report to win a factor ×5to×10 in terms
of productivity when using C-level design methodology depending on the way they
reuse in design their IPs (Fig. 1.4). More promising: designers that moved to C-level
design usually don’t want to come back to RTL level to create their IPs

Side benefit of these C-level design automation, the IP reuse of signal processing
IP is now becoming reality. The flow automation allows to have C-IPs quite indepen-
dent of implementation constraints (technology, throughput, parameters), described
at functional level, easy to modify to cope with new specification and easy to re-
synthesize. Another benefit: the size of the manual description (C instead of RTL)
is reduced by roughly a factor 10. This reduces the time to modification (ECO) as
well as the number of functional bugs manually introduced in the final silicon.
The link with Transactional Level Modelling (TLM) platform has to be enhanced.
Prior to HLS flow, both TLM and RTL descriptions where done manually (Fig. 1.5).
HLS tools would be able to produce the TLM view needed for platform vali-
dation. However, the slowing-down of TLM standardization did not allow in 2006
neither H1-2007 to have a common agreement of what should be TLM 2.0 interface.
This lack of standardization has penalized the convergence of TLM platform flow
and C-level HW design flow. Designer community would benefit of such a common
agreement between major players of the SystemC TLM community.More and more,
we need CAD community to think in terms of flows in their global environment, and
not in terms of tools alone.
Another benefit of HLS tools automation is the micro-architecture exploration.
Figure 1.6 basically describes a change of paradigm: clock frequency can be
partially de-correlated from throughput constraints.
This means that, focusing on the functional constraints (throughput/latency),
designer can explore several solutions fulfilling the specifications, but using various
clock frequencies. Thanks to released clock constraint, the low-speed design will
not have the area penalty of the high-speed solution. Combining this exploration
1 User Needs 5
Spec
description
High level
algorithmic
description

C/TLM
model
RTL
model
TLM
TLM Reference
Platform
RTL Verification
Platform
HLS
tool
Compatible
thanks
to TLM 2.0
Fig. 1.5 Convergence of TLM and design flows
Fig. 1.6 One benefit of automation: exploration
to memory partitioning and management exploration leads to some very interesting
solutions. As an example, Fig. 1.7 shows that combining double buffering of an
LDPC encoder to a division by 2 of the clock speed, produces a ×0.63 lower power
solution for a 27% area penalty. The time-to-solution is dramatically reduced thanks
to automation. The designer can then take the most appropriated solution depend-
ing on application constraints (area/power). Currently, power is estimated at RTL
level, on automatically produced RTL, thanks to some specialized tools. Experience
shows that power savings can be greatly improved at architectural level, compared
to back-end design level.
There is currently no real power-driven synthesis solution known to us. This is
one of the major needs we have for the future. Power driven synthesis will have to be
much more than purely based on signals activity monitoring in the SoC buses. It will
need also to take into account leakage current, memory consumption and will have
to be compliant with multi-power-modes solutions (voltage and frequency scaling).

There are many parameters to take into account to determine a power optimized
solution, the ideal tool would have to take care of all these parameters in order to