Handbook of algorithms for physical design automation part 1 doc

Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C000 Finals Page i 9-10-2008 #1
Handbook
of
Algorithms
for
Physical
design
Automation
Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C000 Finals Page ii 9-10-2008 #2
Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C000 Finals Page iii 9-10-2008 #3
Handbook
of
Algorithms
for
Physical
design
Automation
Edited by
Charles J. alpert
Dinesh p. mehta
Sachin S. Sapatnekar
AN AUERBACH BOOK
CRC Press is an imprint of the
Taylor & Francis Group, an informa business
Boca Raton London New York
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Auerbach Publications
Taylor & Francis Group
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Boca Raton, FL 33487-2742

© 2009 by Taylor & Francis Group, LLC, except for Chapter 19, © by Jason Cong and Joseph R. Shinnerl. Printed with
permission.
Auerbach is an imprint of Taylor & Francis Group, an Informa business
No claim to original U.S. Government works
Printed in the United States of America on acid-free paper
10 9 8 7 6 5 4 3 2 1
International Standard Book Number-13: 978-0-8493-7242-1 (Hardcover)
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Library of Congress Cataloging-in-Publication Data
Handbook of algorithms for physical design automation / edited by Charles J. Alpert, Dinesh P. Mehta,
Sachin S. Sapatnekar.
p. cm.
Includes bibliographical references and index.
ISBN-13: 978-0-8493-7242-1
ISBN-10: 0-8493-7242-9

1. Integrated circuit layout Mathematics Handbooks, manuals, etc. 2. Integrated circuit
layout Data processing Handbooks, manuals, etc. 3. Integrated circuits Very large scale
integration Design and construction Data processing Handbooks, manuals, etc. 4. Algorithms. I.
Alpert, Charles J. II. Mehta, Dinesh P. III. Sapatnekar, Sachin S., 1967- IV. Title.
TK7874.55.H36 2009
621.3815 dc22 2008014182
Visit the Taylor & Francis Web site at

and the Auerbach Web site at

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Dedications
To the wonderful girls in my life:
Cheryl, Candice, Ciara, and Charlie
Charles J. Alpert
To the memory of my grandparents:
Nalinee and Gajanan Kamat, Radha and Shreenath Mehta
Dinesh P. Mehta
To Ofelia and Arunito
Sachin S. Sapatnekar
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Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C000 Finals Page vii 9-10-2008 #7
Contents
Editors xiii
Contributors xv
PART I Introduction
Chapter 1 Introduction to Physical Design 3
Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar
Chapter 2 Layout Synthesis: A Retrospective 9
Ralph H.J.M. Otten

Chapter 3 Metrics Used in Physical Design 29
Frank Liu and Sachin S. Sapatnekar
PART II Foundations
Chapter 4 Basic Data Structures 55
Dinesh P. Mehta and Hai Zhou
Chapter 5 Basic Algorithmic Techniques 73
Vishal Khandelwal and Ankur Srivastava
Chapter 6 Optimization Techniquesfor Circuit Design Applications 89
Zhi-Quan Luo
Chapter 7 Partitioning and Cluster ing 109
Dorothy Kucar
PART III Floorplanning
Chapter 8 Floorplanning: Early Research 139
Susmita Sur-Kolay
vii
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viii Contents
Chapter 9 Slicing Floorplans 161
Ting-Chi Wang and Martin D.F. Wong
Chapter 10 Floorplan Representations 185
Evangeline F.Y. Young
Chapter 11 Packing FloorplanRepresentations 203
Tung-Chieh Chen and Yao-Wen Chang
Chapter 12 Recent Advances in Floorplanning 239
Dinesh P. Mehta and Yan Feng
Chapter 13 Industrial Floorplanning and Prototyping 257
Louis K. Scheffer
PART IV Placement
Chapter 14 Placement: Introduction/Problem Formulation 277
Gi-Joon Nam and Paul G. Villarrubia

Chapter 15 Partitioning-Based Methods 289
Jarrod A. Roy and Igor L. Markov
Chapter 16 Placement Using Simulated Annealing 311
William Swartz
Chapter 17 Analytical Methods in Placement 327
Ulrich Brenner and Jens Vygen
Chapter 18 Force-Directed and Other Continuous Placement Methods 347
Andrew Kennings and Kristofer Vorwerk
Chapter 19 Enhancing Placement with Multilevel Techniques 377
Jason Cong and Joseph R. Shinnerl
Chapter 20 Legalization and Detailed Placement 399
Ameya R. Agnihotri and Patrick H. Madden
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Contents ix
Chapter 21 Timing-Driven Placement 423
David Z. Pan, Bill Halpin, and Haoxing Ren
Chapter 22 Congestion-Driven Physical Design 447
Saurabh N. Adya and Xiaojian Yang
PART V Net Layout and Optimization
Chapter 23 Global Routing FormulationandMaze Routing 469
Muhammet Mustafa Ozdal and Martin D.F. Wong
Chapter 24 Minimum Steiner Tree Construction 487
Gabriel Robins and Alexander Zelikovsky
Chapter 25 Timing-DrivenInterconnect Synthesis 509
Jiang Hu, Gabriel Robins, and Cliff C. N. Sze
Chapter 26 Buffer Insertion Basics 535
Jiang Hu, Zhuo Li, and Shiyan Hu
Chapter 27 Generalized Buffer Insertion 557
Miloš Hrki´c and John Lillis
Chapter 28 Buffering in the Layout Environment 569

Jiang Hu and Cliff C. N. Sze
Chapter 29 Wire Sizing 585
Sanghamitra Roy and Charlie Chung-Ping Chen
PART VI Routing Multiple Signal Nets
Chapter 30 Estimation of Routing Congestion 599
Rupesh S. Shelar and Prashant Saxena
Chapter 31 Rip-Up and Reroute 615
Jeffrey S. Salowe