Handbook of algorithms for physical design automation part 28 docx

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252 Handbook of Algorithms for Physical Design Automation
Suppose these modules are separated by a horizontal cut (i.e., heights must be added and widths
must be maxed). The width distribution list of the new rectangle is {(3, .18), (4, .02), (5, .5), (6, .3)}
and its height list is {(9, .2), (10, .5 ), (11, .3)}.
Repeating this process as the area evaluation algorithm traverses the slicing tree in a bottom-up
fashion finally results in distribution lists for chip height and width. The authors use these quantities
to compute a cost function that is the combination of expected area and standard deviation of area.
Including standard deviation in the cost function makes it more likely that the area of the floorplan
obtained by statistical floorplanning is close to the area of the final solution (i.e., after module
dimensions have all been finalized) relative to minimizing expected area alone. The paper also
considers a combined height/width distribution list (e.g., {(4, 5, .3), (6, 3, .7)}means that a module
has height 4 and width 5 with a pr obability of .3 and a height of 6 and a width of 3 with probability
of .7). This is a more realistic formulation, but experimental results have been more promising with
the separate distribution lists.
12.7 FLOORPLANNING FOR MANUFACTURABILITY
Floorplanning, as we have defined it so far, is concerned with the arrangement of components
within a single chip. In this section, we discuss a floorplanning-like problem that arises because of
the economics associated with manufacturing a chip. Recall that several chips can be manufactured
from a single wafer.To do this, a m ask set has to be prepared for the wafer.Thecost of creating a mask
set is substantial. For high-volume manufacturing (i.e., when many chips of the same type are to be
produced), thisone-timecost (X) is amortized overthenumber of chips (c) produced. For low-volume
manufacturing (few chips have to be produced), the cost per chip X/c becomes prohibitive. The
multiple project reticle concept addresses this problem for low-volume manufacturing by departing
from the assumption that all of the chips on a wafer have to be of the same type. Instead, different
chips (p ossibly sent to the fabrication facility b y different companies) are placed in a reticle. Several
copies of the reticle are arranged in rows and columns on a single wafer. The mask cost X can now
be spread out among the different companies. Suppose there are ten different chips from different
companies on a wafer, then the mask cost for each company is X/10. This is amortized over the
number of chips resulting in a cost per chip of X/10c.
However, this approach presents some new challenges. These differentchips have to be extracted

from the wafer by cutting (dicing) the wafer. Existing wafer dicing technologies are somewhat
restrictive, making chip location s o n the reticle vital to optimizing the chip yield. For example, the
side-to-sidewafer dicing technology cuts the wafer using horizontaland vertical cutlines that traverse
the entire length of the wafer (Figure 12.8). Within a given reticle, these lines may either cut through
dies rendering them useless or might leave large margins making the dies unacceptably large.
There are several associated algorithmic problems. The reticle floorplanning formulation pro-
poses that we comp ute a floorplan and positions of the cutlines assuming a side-to-side wafer dicing
technology. In Ref. [47], both reticle area and wafer yield were optimized using SA. In Ref. [48],
the yield was treated as a constraint and the reticle area was optimized. This strategy, coupled with
a branch-and-bound algorithm, resulted in better solutions than those in Ref. [47]. To further reduce
fabrication cost, projects requiring different num bers of metal layers can be put on the same shuttle.
In Ref. [49], Chen et al. proposed an integer linear programming (ILP)-based floorplanner shuttle
runs consisting of projects of different desired processes.
Another problem associated with reticle floorplanning was considered by Xu et al. [50]. In this
variation, the objective is to c ompute a floorplan that optimizes area and a quantity called postCMP
oxide topography variation. Minimizing this quantity provides the process with a larger margin.
PostCMP oxide topography variation is closely related to the feature density. One technique for
reducing the variation in feature density is to insert dummy features into the design. The floorplanning
algorithm uses SA on slicing floorplans with a cost function that approximates the topography
variation. (Topography variation minimization can be formulated as a linear programming problem,
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Recent Advances in Floorplanning 253
Reticle
Wafer
Cutting line
Die
FIGURE 12.8 Illustration of reticle floorplanning. A wafer contains many reticles, each of which contains
several dies in an identical configuration. The reticle floorplanning problem asks how these dies should be
configured in the reticle, given that the wafer will be diced using horizontal and vertical lines that cut through
the entire wafer.

but this is too time consuming to include in the SA loop.) SA is followed by a step that slides or
rotates the chip and by a third step that inserts a dummy feature.
12.8 CONCLUDING REMARKS
This chapter has been an effort to try and capture as much floorplanning research as possible with a
bias toward newer and inter esting problem formulations that are likely to be significant in practice.
We apologize in advance for any omissions.
ACKNOWLEDGMENTS
The authors thank Yao-Wen Chang, Tung-Chi Chen, Igor Markov, and Sachin Sapatnekar for
carefully reviewing the manuscript and suggesting improvements.
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BIBLIOGRAPHY
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13
Industrial Floorplanning
and Prototyping
Louis K. Scheffer
CONTENTS
13.1 Introduction 257
13.1.1 Floorplanning in the Design Flow 258
13.1.2 Evolution of Block-Based Designs [4] 259
13.2 History 259
13.2.1 Historyof Pin Assignment 261
13.2.2 History of Timing Budgets 261
13.2.3 Academic versus Industrial Floorplanning 261
13.3 Use of Hierarchy 261
13.3.1 Is Hierarchical DesignLess Efficient? 262
13.3.2 Logical versus Physical Hierarchy 262
13.4 Pin Assignment and Timing Budgeting 263

13.5 Routability Analysis 264
13.6 Bufferand Flip-Flop Insertion 265
13.7 Estimating Parasitics and Timing 265
13.8 Power Supply Design 266
13.9 ECOs and Accounting for Changes 267
13.10 Working with Incomplete and Inconsistent Designs 268
13.11 Conclusions and Future Work 268
Acknowledgments 270
References 270
13.1 INTRODUCTION
Industrial floorplanning and prototyping consist of the steps needed after the chip logic is defined,
but before the final detailed implementation of a production chip. Several of the steps, such as pure
block placement and mixed b lock and cell placement (also called the boulders and dust problem),
have received considerable academic interest and are covered in other sections. This chapter instead
concentratesonthepracticalproblemsthatmustbesolvedinthefloorplanningoflargeindustrialchips.
In this chapter we assume the chips to be designed consist of predefined blocks and standard cells.
Predefined blocks (commonly called IP blocks, where IP stands for intellectual p roperty) commonly
include memories, processorsand analogfunctions,and are presented to the designer as givens. Their
placement and orientation must be decided, but their contents cannot be changed. IP blocks come in
a wide variety of shapes and sizes, but are typically relatively large, perhaps the equivalent of a few
thousand to a few million gates. Standard cells, by contrast, are very small, usually incorporating just
one to a few logic gates. Usually they are of a uniform height (hence standard) and designed to be
abutted into rows. A crucial distinction in a typical design flow is that the IP blocks are selected by
the designer, and cannot be changed by the automatic tools, whereas the standard cells, are normally
257
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258 Handbook of Algorithms for Physical Design Automation
generatedb y logic synthesis [1],andcan be freely modifiedbythe tools as long as the logicalfunction
specified by the RTL is preserved.
A floorplanand a prototype are two different approximate versions of a chip, at differentlevels of

abstraction. The floorplan is the more abstract of the two, consisting of just a chip outline, placement
and orientation of the hard blocks, an IO placement, sites where the standard cells can go, and an
approximate power grid design. The blocks may be hard, or fully defined, or may be blocks that
are still under construction. These are commonly called soft if their size or aspect ratio is not fully
decided, or black or gray boxes if their size is fixed but their contents unknown. (In the terminology
of floorplanning, a black box is a cell where only the inputs, outputs, and function are known. By
analogy, white and gray boxes have contents fully and partially defined, respectively. Note that the
color of a box may vary according to purpose—the same block may be a black box for placement, a
gray box for timing, but a white box for logic verification.)
A prototype consists of everything from the floorplan, plus a detailed placement and at least a
rough route (normallyincluding at least layer and track assignment). The goal is to enable reasonably
accurate extraction and timing verification, and hence show a design is feasible and ready for the
more time-consuming steps of final placement and routing. The final detailed implementation may
or may not follow the prototype.
Like placement, a good floorplan or prototype is not unique. Typically, there are many different
possible floorplans for the same design, of comparable quality. One of the major questions, as in
placement, is how do you know you have got a good floorplan, compared with what might be
possible? This situation is even worse than the situation in placement, where there are at least a few
examples where the optimum solution is known [2].
13.1.1 FLOORPLANNING IN THE DESIGN FLOW
Design of a modern chip involves many steps. First, the exact function of the chip must be defined,
and shown to be correct. The formal definition of the function is usually specified in RTL, and
proving it correct is done by simulation, formal verification, and a host of other techniques. These
steps are collectively r eferred to as front-end design.
The RTL from the front-end process then goes to the back end where it is turned into a detailed
implementation. Normally, this involves mapping the function into an interconnected set of logic
gates (by logic synthesis), followed by p lacement, routing, extraction, timing analysis, and design
rule checking, and ultimately the fabrication of the masks, and then ICs.
In cases where engineering margins of performance, power, and cost are large, the front and back
ends can be largely independent. In many cases, however, they interact fairly strongly, particularly

when some feature of th e RTL is difficult or impossible to implement in the back end. This interaction
is made worse by the differing expertises involved. Most front-end designers are not familiar with the
back-end tools, and do not have time to run them in any case. Most back-end designers do not have
the expertise to change the RTL, even if they were allowed to do so. Floorplanners are an attempt to
bridge this gap with a tool accessible to both sides.
Floorplanningdecides the overall layout of the chip, and is used early in the chip design flow [3],
when the design is malleable and all fixes are possible. Normally it is used by a front-end user, or a
back-end expert working in close cooperation with a front-end group. One of the main objectives of
floorplanningis helping both the front- and back-end users understand the design. Which constraints
are easy, and which hard? Does it meet timing? Routability? Has enough routing resource been
allocated to the power supplies? Will the RTL work as is, or are changes needed to make it feasible to
meet the design constraints using the specified process and library? Because one of the main tasks of
a floorplanner is diagnostics (where is the routing hard, and why? Why is the timing hard to meet?),
easy-to-use graphical user interfaces (GUIs) and easy-to-understand feedback are critical.
Because one of the main points of floorplanning is to understand the d esign as early as possible,
a crucial featu re of a floorplanner is the ability to work with incomplete designs. Missing blocks,
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Industrial Floorplanning and Prototyping 259
incompleteconstraints, and even missing technologyinformationmust be h andled, often by allowing
designers to enter estimates for the missing data.
OncetheRTLisdeemed complete,or nearlyso,thenextstepisprototyping.Thisisafast(andoften
rough) pass through the entire physical design process of synthesis, placement, routing, extraction,
and timing analysis. This quick pass is meant to verify feasibility and completeness before starting on
the lengthy production-quality physical design steps. The prototype design produced may or may not
form theb asis ofthe finalimplementation. Normallyprototypingis donebya back-enduser,o r atleast
someone with experience in placement and routing. Because one of the main reasons for prototyping
is to ensure that everything is ready, it is much less tolerant of missing data than a floorplanner. The
prototyper will perform at least a rough version of the final implementation steps, including place
and route, extraction and timing analysis, so all required inputs must be present and consistent. This
includes libraries, the input hardware description language (or HDL), constraints, IP blocks, and so

on. Completion of a successful prototype shows the RTL should no longer need major changes.
Prototyping is also part of a business model for ASIC handoff. In this business model, respon-
sibility for a chip is split among the end customer, who wishes to logically design and sell a chip,
and the ASIC house, who does the detailed implementation and manufacturing. Several costs and
responsibilities are contractually obligated in such a relationship:
• The designer, usually working at the end customer, must supply an RTL that can be practi-
cally implemented in the specified process (even though they do not do this implementation
themselves).
• The ASIC house must quote a price for the detailed implementation. There are normally
additional charges if the RTL changes after implementation starts.
• The ASIC house must quote a price for each chip produced.
Prototyping (and to a lesser extent, floorplanning) helps a great deal with this interface between
companies. The designer uses prototyping to make sure their RTL can be implemented in the specified
process with the needed performance, and to ensure that all is ready for implementation, to avoid
additional charges for later changes. Also, a prototype serves as a concrete example of at least one
way to meet the design goals, though the ASIC house is not normally constrained to follow it. On the
other side, the ASIC house uses prototyping for QA on incoming designs, to make sure all required
information is ther e, and for cost estimates for both the detailed implementation process and the final
chip cost. A prototype, as a physically accurate model, also helps ensure that the chip will fit in the
specified package and can be bonded successfully.
Finally, a floorplanner or prototyper also serves as a central repositor y for data, especially in the
hierarchical design style. The input is the RTL for all groups, libraries, IO files, SDC constraints, and
so on. The output is a similar set of files for each physical block. This implies the use and reading o f
many languages: LEF/DEF, IO specifications, Verilog or VHDL, delay constraints, and so on.
13.1.2 EVOLUTION OF BLOCK-B ASED DESIGNS [4]
Floorplanners were originally built for designs with relatively few blocks, with the chip area dom-
inated by standard cells, as shown in Figure 13.1a. However, as chips have gotten larger, designers
have incorporated larger and larger fractions of blocks. The remaining standard cells, increasing in
number but decreasing in terms of percentage, must be placed into the spaces between the blocks.
An example of such a floorplan is shown in Figure 13.1b. This change in design style has several

implications for the algorithms and methods used in today’s floorplanners.
13.2 HISTORY
When chips were small, and tools primitive, what we currently call a floorplan could be drawn by
hand on a piece of paper. Place and route tools, when used, were only run after the netlist was
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260 Handbook of Algorithms for Physical Design Automation
(a) (b)
FIGURE 13.1 (a) Standard cell-dominated design on the left and (b) block-dominated design on the right.
(From Wein, E. and Benkoski, J., Electronics Engineering Times, August 20, 2004. With permission.)
finalized. Performance was verified by taking the final placed and routed results, running extraction,
then delay calculation, then timing analysis. Any performance optimizations, or corrections of errors
and omissions, were done using the place or route tool directly.
As chips grew past a few thousand gates, an additional tool began to make sense. Some of tasks
that were not well addressed by the old flow include:
• Designers wished to know if a design was feasible before (or without) doing the final layout
tasks such as a fully detailed power grid.
• Designers wanted to examine the feasibility of a design before all parts were complete.
• Designers wanted to divide a design up into two or more sections, each of which could be
treated separately.
• Designers wanted to understand where there design was easily implemented, and where
there were problems, early in the design cycle when RTL changes are still relatively
easy.
Floorplanners were invented to address these needs. Many of the initial uses of floorplanning envi-
sioned it as part o f a suite of integrated tools, such as VIVID [5,6], or the internal tools of DEC [7],
or CHEOPS [8]. By 1986, standalone floorplanners such as Mason were available [9].
In the late 1990s, as designs became bigger yet, they often ran into problems in detailed imple-
mentation even though they had what appeared to be a good floorplan. In particular, problems often
only showed up after detailed routing, extraction, and timing were complete, because many charac-
teristics of the final design are heavily influenced by the details of the routing. However, detailed
placement, routing, extraction, and verification often took a week or more—not unreasonable for the

final implementation, but too long for effective feedback to the earlier stages of the design process.
The technical solution was to do a very fast but fully detailed placement, followed by a very fast
(but rough) detailed route, and a fast approximate RC extract. If timing analysis on this indicated
all was well, then the relatively lengthy detailed implementation process could begin. A floorplan
that was verified through these additional steps was sometimes called a virtual silicon prototype,
and the process called prototyping. See Goering for an early reference [10], Chao and Lev [11] for
an informal explanation of the importance of detailed wiring, and Dai et al. [12] for a more formal
description of the process.
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Industrial Floorplanning and Prototyping 261
13.2.1 HISTORY OF PIN ASSIGNMENT
Early on, printed wiring boards (PWBs) served as modules. Assigning pins on these modules was
the equivalent of pin assignment in IC floorplanners. This was does as early as 1972 [13]. For ICs,
this problem was only seriously addressed in the 1980s.
By 1984,thepinassignment problemwas explicitlyaddressed [14]. By 1989,pinassignmentwas
being combined with global routing [15,16]. By 1990, it was combined with floorplanning [17,18],
and by 2002 with buffer planning [19]. See Section 13.4 for more details.
13.2.2 HISTORY OF TIMING BUDGETS
Time budgeting was first addressed in the context of breaking a path delay into individual net
delays, as in Ref. [20]. Many other approaches to this have been developed [21]. Then budgeting
was extended to hierarchical design, for example, by Venkatesh [22] or Kuo and Wu [23]. In a
floorplanner, it makes sense to use the hierarchy information as well [24].
13.2.3 ACADEMIC VERSUS INDUSTRIAL FLOORPLANNING
Although they both have activities called floorplanning, industry and academia mean very different
things by this term. In academia, floorplanning refers primarily to automatic placement of pure block
designs,or designs includinglarge fractionsof blocks, with objectives of good packingand minimum
wirelength. A related term, floorplacement, refers to the automatic simultaneous placement of blocks
and standard cells [25,26].
In contrast, in industrial floorplanning, manual input is allowed if not encouraged, and the main
goals are timing and routability, with area an d wirelength tr eated as means to an end , and n ot an

objective by themselves. Industrial floorplanning includes, and is often dominated by, practical con-
cerns such as power grid design, dealing with partially specified or contradictory data, multivoltage
support for power reduction, buffer insertion, ease of clock tree design, and so on.
13.3 USE OF HIERARCHY
Floorplanning and prototyping may be flat or hierarchical. In a flat floorplan, the entire design is
treated as a single problem, and any cell or block can be placed at any location in the design. There
is no need to assign cells and pins to the blocks, or create block budgets for timing or power. This
flat design style is conceptu ally straightforward and provides maximum implementation flexibility.
However, it has several disadvantages, especially for large designs. It may stress the limits of tools
(which often cannot handle a large design flat) as well as humans, who may not be able to easily
understand such a design. Because every detail of the design interacts, there may be no easy way to
divide the work among teams. Flat design may well make changes more difficult, because they are
less localized, which can also impact design closure [27]. For these and other reasons, many chips
are designed hierarchically. In this case, the chip surface is divided into areas, commonly called
blocks. Each block represents an independent design problem—all cells assigned to the block must
be placed inside it, and all wires purely internal to the block must be routed within its boundary.
Signals that connect to the rest of the design are brought to pins, where the routing from the rest of
the design will connect. These pins must be assigned locations and layers for each block, and each
block must be assigned a definite size and location within the chip. All design constraints must be
budgeted among the blocks. Foremost among these constraints are timing and power. The budgeting
process is crucial, in particular, one infeasible budget (among tens of thousands of pins) can make
the whole design infeasible, where it might be easily completed using a flat flow.
There are also intermediate design styles, intended to combine the advantages of flat and hier-
archical design. For example, placement might be hierarchical, to limit the scope of changes, but
routing done flat, to avoid the need for pin assignment. A similar approach is a flat floorplan with
regions. In this particular case, the cells are confined to specific regions as in a hierarchical design,