Handbook of algorithms for physical design automation part 40 pdf

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372 Handbook of Algorithms for Physical Design Automation
(a)
(b)
FIGURE 18.12 Illustration of the adaptec2 circuit from the ISPD05 benchmark suite [39] where (a)
sho ws the circuit’s fixed obstacles and I/O pads before placement and (b) shows that after the placement of cells
after a single QP, many cells may become trapped (or block ed) by fixed obstacles.
slot constraints on the placement prob lem. An illust ration of heterogeneous resources within Altera’s
HC230 structured ASIC is shown in Figure18.13.
Although APlace [32] handles geometric constraints, slot constraints represent another type of
constraint not properly handled geometrically.So, the question arises as to what is the best method to
handle discrete slot constraints during force-directed placement. Traditional force-directed placers
cannot compel heterogeneous cells to be placed at discrete slots—in the best case, these methods can
coerce heterogeneous cells toward discrete slots. In Ref. [41], an extension to a force-directed placer
to handle heterogeneous resources is presented. In effect, the cell distributions for d ifferent types of
cells are maintained in separate layers—spreading forces for different types of cells are computed
in the appropriate layer. This enhancement was shown to yield placements where cells are placed
reasonably closely to the appropriate type of resource. Once again, however,it is worthwhile to ask if
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Force-Directed and Other Continuous Placement Methods 373
M4K RAM blocks
IOE
Array
of HCells
Fast
PLL
IOE IOEs
Array
of HCells
Array
of HCells

M-RAM block
Array
of HCells
Array
of HCells
Array
of HCells
Enhanced
PLL
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
M4K RAM blocks
FIGURE 18.13 Partial floorplan of an HC230 structured ASIC [42]. Heterogeneous resources including I/Os,
M4K RAMs, PLLs, and mega-RAMs must be placed into disjoint slots. (From Altera corporation, Hard Copy
Series Handbook, Altera, 2005. With permission.)
even more effective techniques for dealing with heterogeneous resources can be developed because
the placement of these resources can have a large impact o n the overall quality of the placement.
18.7 CONCLUSIONS
With the advent of Kraftwerk in the late 1990s, force-directed placement methods have received
a great deal of attention from academia and industry. These methods have been used successfully to

place multimillion gate designs, a nd have continually improved in quality, scalability, and robustness
each year.
In this chapter, we have examined force-directed methods by highlighting the similarities and
differences between the various implemen tations described in the literature. We have also examined
continuous methods that, like force-directed methods, do not rely on partitioning to remove cell
overlap and share similarities with the more traditional force-directed methods. Many of the meth-
ods presented in this chapter have been extended to accommodate other practical VLSI placement
objectives, which were beyond the scope of the discussion in this chapter. These objectives include
timing-, congestion-, and thermal-driven placements. For the interested reader, force-directed plac-
ers incorporating timing constraints through netweighting are described in Refs. [32,43,44], while
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374 Handbook of Algorithms for Physical Design Automation
a timing-oriented hypergraph model based on Steiner trees is described in Ref. [45]. Congestion
minimization within force-directed methods have also been examined in the context of cell bloat-
ing [32]. Force-directed methods for thermal placement in three-dimensional architectureshave been
examined [46].
The future of force-directed methods is a promising area of research in the field of VLSI CAD.
The ease with which the placement problem can be analogized to spreading forces continues to spur
research and advancement—new app roaches that raise the bar in terms of performan ce and quality
are being conceived at a tremendous pace. Continued improvements in force-directed methods will
no doubt serve to strengthen the prominence of these methods.
REFERENCES
1. Adya, S. N., Chaturvedi, S., Roy, J. A., Papa, D. A., and Markov, I. L. Unification of partitioning, placement
and floorplanning. In Proc. ICCAD, November 2004, pp. 550–557, San Jose, CA.
2. Fisk, C., Caskey, D., and West, L. Automated circuit card etching layout. In Proc. IEEE, 55: 1971–1982,
1967.
3. Kahng, A. B. and Reda, S. A tale of two nets: Studies of wirelength progression in physical design. In Proc.
System-Level Interconnect Prediction, March 2006, pp. 17–24, Munich, Germany.
4. Eisenmann, H. and Johannes, F. M. Generic global placement and floorplanning. In Proc. DAC, June 1998,
pp. 269–274, San Francisco, CA.

5. Hall,K.M. An r-dimensional quadratic placement algorithm. Manage. Sci. 17 (November): 219–229, 1970.
6. Vygen, J. Algorithms for large-scale flat placement. In Proc. DAC, June 1997, pp. 746–751, Anaheim, CA.
7. Kennings, A. and Markov, I. L. Smoothing max-terms and analytical minimization of half-perimeter wire
length. VLSI Design 14, 3: 229–237, 2002.
8. Viswanathan, N. and Chu, C. C. -N. Fastplace: Efficient analytical placement using cell shifting, iterative
local refinement and a hybrid net model. IEEE Trans. CAD 24, 5 (May): 722–733, 2005. (ISPD 2004) .
9. Viswanathan, N., Pan, M., and Chu, C. C. -N. Fastplace: An analytical placer for mixed-mode designs. In
Pr oc. ISPD, April 2005, pp. 221–223, San Francisco, CA.
10. Saad, Y. Iterative Methods for Sparse Linear Systems. SIAM, 2003.
11. Qian, H. and Sapatnekar, S. S. A hybrid linear equation solver and its application in quadratic placement.
In Proc. ICCAD, N ovember 2005, pp. 905–909, San Jose, CA.
12. Obermeier, B. and Johannes, F. M. Quadratic placement using an improved timing model. In Proc. DAC,
June 2004, pp. 705–710, San Diego, C A.
13. Yao, B., Chen, H., Cheng, C. -K., Chou, N. -C., Liu, L. -T., and Suaris, P. Unified quadratic programming
approach for mixed mode placement. In Proc. ISPD, April 2005, pp. 193–199, San Francisco, CA.
14. Spindler, P. and Johannes, F. M. Fast and robust quadratic placement combined with an exact linear net
model. In Proc. ICCAD, November, 2006, pp. 179–186, San Jose, CA.
15. Kennings, A. and Markov, I. L. A nalytical minimization of half-perimeter wire-length. In Proc. ASPDAC,
January 2000, pp. 179–184, Yokohama, Japan.
16. Vorwerk, K., Kennings, A., and Vannelli, A. Engineering details of a stable analytic placer. In Proc. ICCAD,
November 2004, pp. 573–580, San Jose, CA.
17. Barnes, J. and Hut, P. A h ierarchical O(n log n) force calculation algorithm. Natur e 324, 4: 446–449, 1986.
18. Etawil, H., Areibi, S., and Vannelli, A. Attractor-repeller approach for global placement. In Proc. ICCAD,
November 1999, pp. 20–24, San Jose, CA.
19. Hu, B. and Marek-Sadowska, M. Multilevel expansion-based VLSI placement with blockages. In Proc.
ICCAD, N ovember 2004, pp. 558–564, San Jose, CA.
20. Hu, B. and Marek-Sadowska, M. Multilevel fixed-point-addition-based VLSI placement. IEEE Trans. CAD
24, 8 (August): 1188–1203, 2005.
21. Chaudhary, K. and Nag, S. K. Method f o ranalytical placement of cells using density surface representations.
United States Patent 6,415,425, July 2002.

22. Nussbaumer, H. J. Fast Fourier Transform and Conv olution Algorithms. Springer-Verlag, New York, 1982.
23. Goto, S. An ef ficient algorithm f or the two-dimensional placement problem in electrical circuit l ayout.
IEEE Trans. Circuits Syst. CAS-28, 1: 12–18, 1981.
24. Vorwerk, K. and Kennings, A. An improved multi-level framework for force-directed placement. In Proc.
DATE, March 2005, pp. 902–907, Munich, Germany.
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25. Karypis, G. Multilevel Optimization and VLSICAD. Kluwer Academic Publishers, Boston, MA, 2002, ch. 3.
26. Alpert, C., Kahng, A. B., Nam, G. -J., Reda, S., and Villarubia, P. A semi-persistent clustering technique
for VLSI circuit placement. In Proc. ISPD, April 2005, pp. 200–207, San Francisco, CA.
27. Chan, T. F., Cong, J., Kong, T., Shinnerl, J. R., and Sze, K. An enhanced multilevel algorithm for circuit
placement. In Proc. ICCAD, November 2003, pp. 299–306, San Jose, CA.
28. Chan, T., Cong, J., and Sze, K. Multilevel generalized force-directed method for circuit placement. In Proc.
ISPD, April 2005, pp. 185–192, San Francisco, CA.
29. Kahng, A. B., Reda, S., and Wang, Q. Architecture and details of a high quality, large-scale analytical placer.
In Proc. ICCAD, November 2005, pp. 891–898, San Jose, CA.
30. Sigl, G., Doll, K., and Johannes, F. M. Analytical placement: A linear or a quadratic objective function? In
Proc. DAC, June 1991, pp. 427–432, San Francisco, CA.
31. Alpert, C. J., Chan, T., Huang, D. J. -H., Markov, I. L., and Yan, K. Quadratic placement revisited. In Proc.
DAC, J une 1997, pp. 752–757, Anaheim, CA.
32. Kahng, A. B. and Wang, Q. Implementation and extensibility of an analytic placer. IEEE Trans. CAD 24,
5 (May): 734–747, 2005. (ISPD 2004).
33. Naylor, W., Donelly, R., and Sha, L. Non-linear optimization system and method for wire length and density
within an automatic electronic circuit placer. United States Patent 6,662,348, July 2001.
34. Kahng, A. B. and Wang, Q. An analytic placer for mix ed-size p lacement and timing-driven placement. In
Proc. ICCAD, November 2004, pp. 565–572, San Jose, CA.
35. Kahng, A. B., Reda, S., and Wang, Q. Aplace: A general analytic placement framework. In Proc. ISPD,
April 2005, pp. 233–235, San Francisco, CA.
36. Ames,W.F.(ed.).Numerical Methods for Partial Differential Equations. Academic Press, New York, 1977.
37. Arrow, K. J., Hurwicz, L., and Uzawa, H. (eds.). Studies in Nonlinear Programming. University Press,

Stanford, CA, 1958.
38. Westra, J. and Groeneveld, P. Towards integration of quadratic pl acemnt and pin assignment. In Proc. IEEE
Symp. VLSI, M ay 2005, pp. 284–286, Tampa, FL.
39. Nam, G. -J., Alpert, C. J., Villarrubia, P., Winter, B., and Yildiz, M. The ISPD2005 placement contest and
benchmark suite. In P roc. ISPD, April 2005, pp. 216–220, San Francisco, CA.
40. Selvakkumaran, N., Ranjan, A., Raje, S., and Karypis, G. Multi-resource aware partitioning algorithms for
FPGAS w ith heterogeneous resources. In Proc. DAC, June 2004, pp. 741–746, San Diego, C A.
41. Hu, B. Timing-dri ven placement for heterogeneous field programmable g ate array. In Proc. ICCAD,
November 2006, pp. 383–388, San Jose, CA.
42. Altera Corporation. HardCopy Series Handbook, Volume 1—Section 1: HardCopy II Device Family Data
Sheet. Altera, 2005.
43. Mo, F., Tabbara, A., and Brayton, R. K. A timing-driven macro-cell p lacement algorithm. In Proc. ICCAD,
November 2001, pp. 322–327, San Jose, CA.
44. Hur, S. -W., Cao, T., Rajagopal, K., Parasuram, Y., Chowdhary, A., Tiourin, V., and Halpin, B. Force directed
Mongrel with physical net constraints. In Proc. DAC, June 2003, pp. 214–219, Anaheim, CA.
45. Obermeier, B., Ranke, H., and Johannes, F. M. Kraftwerk: A versatile placement approach. In Proc. ISPD,
April 2005, pp. 242–244, San Francisco, CA.
46. Goplen, B. and S apatnekar, S. S. Efficient thermal placement of standard cells in 3D ICs using a force
directed approach. In Proc. ICCAD, November 2003, pp. 86–89, San Jose, CA.
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19
Enhancing Placement with
Multilevel Techniques
Jason Cong and Joseph R. Shinnerl
CONTENTS
19.1 Introduction to Placement by Multiscale Optimization 378
19.1.1 Characterization of Multiscale Algorithms 378
19.2 Basic Principles of Multiscale Optimization 380
19.2.1 Multiscale Model Problem for Quadratic Placement 380

19.2.2 Simple Examples of Interpolation 382
19.2.3 Strict Aggregation versus Weighted Aggregation 383
19.2.4 Scalability 383
19.2.5 Convergence Properties 384
19.2.5.1 Error-Correcting Algorithm MG/Opt 384
19.3 Multiscale Placement in Practice 385
19.3.1 Clustering-Based Precursors 385
19.3.2 Coarsening 386
19.3.2.1 Best-Choice Clustering 387
19.3.2.2 Location-Based Clustering 388
19.3.2.3 Mutual Contraction and Fine-Granularity Clustering 389
19.3.2.4 Net Cluster 389
19.3.2.5 Coarsest Level 391
19.3.2.6 Numbers of Levels 391
19.3.3 Iteration Flow 391
19.3.4 Relaxation 392
19.3.4.1 mPL6 392
19.3.4.2 APlace 392
19.3.4.3 FDP/LSD 393
19.3.4.4 Dragon 393
19.3.5 Interpolation 393
19.3.6 Multiscale Legalization and Detailed Placement 394
19.4 Conclusion 394
Acknowledgment 395
References 395
The increased importance o f interconnect delay on VLSI circuit performance has spurred rapid
progress in algorithms for large-scale global placement. The new algorithms often generalize previ-
ously stud ied heuristics or embed them within a hierarchical framework, either top-down recursive
partitioning or multilevel (a.k.a. mu ltiscale) optimization. This chapter presents a brief tuto rial on the
377

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378 Handbook of Algorithms for Physical Design Automation
multilevel approach and describes some leading con temporary multiscale algorithms for large-scale
global placement.
Multiscale methods have emerged as a means of generating scalable solutions to many diverse
mathematical problems in the gigascale range. However, multiscale methods for partial differential
equations(PDEs) [1,2] are not readily transferredto large-scalecombinatorial optimizationproblems
like placement. Lack of continuity presents one obstacle; myriad local extrema present another. Lack
of a n atural grid structure presents a challenge as well. Although there has been progress in the
so-called algebraic multigrid (AMG) PDE solvers over general, unstructured graphs, extensions of
these methods to hypergraphs are not generally available.
Hierarchical levels of abstraction are indispensable in the design of gigascale complex systems,
but hierarchies must properly represent physical relationships, viz., interconnects,among constituent
parts. The flexibility of the multiscale heuristic provides the opportunity both to merge previously
distinct phases in the design flow and to simultaneously model very diverse, heterogeneous kinds
of objectives and constraints. Adaptability to complex formulations of standard objectives and con-
straints su ch as timing (Chapter 2 1) [3,4], routability (Chapter 22) [5–7], and power (Chapter 22 ) [8 ]
is a demonstrated core attribute of the multilevel ap proach. For simplicity, however, attention in
this chapter is restricted to the standard mo del problem in which weighted half-perimeter wire-
length (HPWL) is minimized subject to upper-bounds on the module area density in every bin of a
superimposed rectangular grid (Chapter 14).
This chapter has the following aims:
1. Introduce basic ideas and vocabulary.
2. Summarize known basic principles of general multiscale algorithms for g lobal optimization.
3. Summarize properties of leading contemporary multiscale placemen t algorithms.
4. Compare current practice to the known theory and identify likely areas of research
opportunity.
Each of these aims is addressed below in its own section.
19.1 INTRODUCTION TO PLACEMENT BY MULTISCALE OPTIMIZATION
By multiscale optimizatio n [9], we mean (1) the use of optimization at every level of a hierarchy

of problem formulations, wherein (2) each variable at any given coarser level represents a subset
of variables at the adjacent finer level. In particular, each coarse-level formulation can be viewed
directly as a coarse representation of the originalproblem. Therefore, coarse-level solutions implicitly
provide approximate solutions at the finest level as well.
19.1.1 CHARACTERIZATION OF MULTISCALE ALGORITHMS
A generic schematic of the classic V-cycle m ultiscale-optim ization paradigm is shown in Figure 19.1.
A generic example of multiscale placement is illustrated in Figures 19.2 and 19.6.
Multiscale algorithms share the following common components. Each is discussed in more
detail below.
1. Hierarchy co nstruction (coarsening, aggregation). Although the construction is usually from
the bottom-up by recursive aggregation, top-down construction s based on recursive netlist
partitioning are sometimes used. On hypergraphs or graphs, aggregation typically amounts
to some form of clustering. On graphs, less restrictive forms have been successful, in which
a finer-level variable is directly associated with multiple coarse-level variables (see the
discussion of weighted aggregation below).
2. Relaxation. In placement, the purpose of intralevel optimization is efficient, iterative explo-
ration of the solution space at that level. Continuous, discrete, local, global, stochastic, and
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Enhancing P lacement with Multilevel Techniques 379
( etc. )
Aggregation
Aggregation
Aggregation
Aggregation
( etc. )
Coarsest-level problem
and solution
Solution at finest
granularity
Interpolation

Interpolation
Interpolation
Interpolation
Given problem at finest
granularity
Intermediate-level problem
Intermediate-level problem Intermediate-level solution
Intermediate-level solution
FIGURE 19.1 Multiscale formulation of global optimization.
deterministic formulations may be used in various combinations. The critical requirement
is that the iterations make rapid p rogress by changing variables in amounts proportionate
to the modeling scale at the given level. The starting configuration is the solution obtained
at an adjacent level, either coarser or finer.
3. Interpolation. A coarse-level solution can be transferred to and represented at its adjacent
finer level in a variety of ways. The simplest and m ost common is simply the placement
of all components of a cluster concentrically at the cluster’s center. More sophisticated
approaches are discussed in Section 19.3.5 below. I n the placement literature, interpolation
is variously referred to as declustering, disaggregation, or uncoarsening. See Figure19.5
for an illustration.
4. Iteration flow. The levels of the hierarchy may be traversed in different ways. A single
pass of successive top-down refinement from the coarsest to the finest level is still the
(a) Initial placement at level 2 (b) Optimization at level 2 (c) Interpolation to adjacent
level 1
(d) Optimization at level 1 (e) Interpolation to adjacent
level 0
(f) Optimization at level 0
FIGURE 19.2 Multiscale placement by successive top-down refinement.
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380 Handbook of Algorithms for Physical Design Automation
Coarse

Fine Fine
Coarse CoarseCoarse
(d) W-cycle
Fine
Coarse
Fine
Fine
Fine
CoarseCoarse
Coarse
Coarse
(c) FMG
(a) Successive
refinement
(b) Classic V-cycle
FIGURE 19.3 Some iteration flows for multiscale optimization. Points nearer the bottom of each diagram
represent coarser levels of approximation.
most common. It is illustrated schematically in Figure 19.3 a and graphically in Figure 19.2.
Alternatives include standard flows such as a single V-cycle, multiple V-cycles, W-cycles,
and the full multigrid (FMG) F-cycle (see Figure 19.3). In these more general flows, the
outcome of relaxation at finer levels is often used to construct the next set of coarser levels.
That is hierarchies may be constructed dynamically and adaptively rather than a priori.
The forms taken by these components are usually tightly coupled with the diverse objective and
constraint models used by different algorithms.
When the hierarchy is defined by recursive bottom-up clustering, the combined flow of recursive
clustering followed by recursive top-down optimization and interpolation is traditionally referred
to as a V-cycle (Figure 19.3; the bottom of the V corresponds to the coarsest or top level of the
hierarchy). While the u sual iteration flow in VLSICAD proceeds top down, from coarsest to finest
level, in the elementary theory of convergence of multigrid PDE solvers [1,2], the use of relaxation
in the coarsening phase plays a vital role. In placement, such usage translates to location-based or

physical clustering, an active area of placement research discussed in Sections19.2 and 19.3.
19.2 BASIC PRINCIPLES OF MULTISCALE OPTIMIZATION
Multiscale methods originated asgeometricmultigrid methodsinthecontextofuniformly discretized
PDEs, where the resolution and regularity of the discretization make the notion of m odeling scale
obvious. Although at first glance it might appear that multiscale methods are limited to explicitly
discretized problems, subsequent research on algebr aic multigrid for general problems lacking any
obvious, geometrically regular discretization has borne out the generality and applicability of the
multiscale metaheuristic. The important requirement is not the geometric regularity, but the locality
of the coupling among the variables. (The locality assumption can also be weakened [9].)
In this section, we define a simple model problem for quadratic placement and use it to draw
connections to elementary general properties of multiscale optimization.
19.2.1 MULTISCALE MODEL PROBLEM FOR QUADRATIC PLACEMENT
General formulations of placementare described in Chapter 14.The following simplified formis used
here only for exposition of basic principles and techniques. As illustrated in Section 19.3, multiscale
algorithms for placement are not limited to this form.
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Enhancing P lacement with Multilevel Techniques 381
Let vector s = (x, y) ∈ R
n
denote the 2D coordinates of all movable modules to be placed (n is
twice the number of movable modules). Let matrix Q ∈ R
n×n
denote the (weighted) graph Laplacian
satisfying, e.g.,
q(s) =
1
2
s
T
Qs −b

T
s =
1
2

netse

i,j∈e
w
ij
[(x
i
− x
j
)
2
+ (y
i
− y
j
)
2
] (19.1)
where vector b ∈ R
n
captures connections between fixed terminals and movable objects. (The
simplified notation above suggests but need not be limited to a clique model of each net.) Matrix Q
is symmetric positive semidefinite.
The quadratic model problem is simply to find an unconstrained minimizer s
∗

of q(s).As
described in Chapter 18, this problem forms a template for one iteration to many force-directed
algorithms [10–14].
†
In the presence of fixed terminals, Q is positive definite, and the quadratic
function q(s) has a unique minimizer s
∗
satisfying
Qs
∗
= b (19.2)
That is, the simplified quadratic model reduces placement to a linear system of linear equations. In
this form, multiscale algorithms for placement are more readily examined in the context of general
multiscale algorith ms for global optimization or PDEs.
Iterative relaxation on the linear-system model p roblem (Equation19.2) may p roceed, e.g., by
the Gauss–Seidel iterations, i.e., one variable at a time,
s
i
=
1
q
ii

b
i
−

j=i
q
ij

s
j

(19.3)
for each i = 1, , n. Such iterations are known to converge on sym metric positive-definite linear
systems [15]. Because real netlists for placement are dominated by low-degree nets, placement
exhibits local structure; i.e., for most i, q
ij
= 0 for all but a small subset of j = i. Hence, an entire
sweep of Gauss–Seidel relaxation proceeds in runtime essentially linear in the number of movable
components.
Next, consider the representation of formulation (Equation19.2) at an adjacent coarser level in
a multiscale flow. Mathematically, it is convenient to proceed as follows:
1. Formulate the coarse-level problem in terms of the error e = s
∗
−˜s in a given approximate
solution ˜s at the finer level.
2. Define interpolation before defining coarsening (see examples in Section 19.2.2).
First, following step 1 above, rewrite Equation 19.2 in terms of the desired perturbation e to the given
approximate solution ˜s as Q(˜s +e) = b, or, equivalently, as the residual equation
Qe = r (19.4)
where the r = b − Q˜s = r(˜s ) is the residual of Equation 19.2 associated with ˜s.
Second, following step 2 above, suppose the finer-level variables e ∈ R
n
are interpolated from
coarse-level variables e
c
∈ R
m
by the linear map P: R

m
→ R
n
as follows (m < n):
e = Pe
c
(19.5)
†
Iterati vely computed, artificial, fixed, target terminals defined by spreading forces are typically used to produce a sequence
of such models whose solutions converge to a sufficiently uniform density profile.