Compal confidential schematics document Mobile Penryn uFCPGA with Intel cantiga_pm+ich9-m core logic pdf
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Compal confidential
schematics document
Mobile Penryn uFCPGA with Intel
cantiga_pm+ich9-m core logic
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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Cover Sheet
Custom
153Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
Mobile Penryn uFCPGA with Intel
Cantiga_PM+ICH9-M core logic
2008-02-25
Compal confidential
Schematics Document
www.kythuatvitinh.com
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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Block Diagram
Custom
253Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
Compal confidential
Thermal Sensor
EMC1402
Fan conn
Mobile Penryn
uFCPGA-478 CPU
FSB
667/800/1066 MHz 1.05V
H_A#(3 35)
H_D#(0 63)
FCBGA 1329
Intel Cantiga MCH
DMI X4
BANK 0, 1, 2, 3
DDR2 SO-DIMM X2
DDR2 667MHz 1.8V
Dual Channel
Mini-Card*2
Power On/Off CKT.
LPC BUS
DC/DC Interface CKT.
RTC CKT.
mBGA-676
Intel ICH9-M
Touch Pad CONN.
Int.KBD
ENE
Realtek
811C(Gbe)
RJ45/11 CONN
PCI-E BUS*5
LED
SATA HDD Connector
SATA Master-1
SATA Slave
C-Link
Codec_IDT9271B7
Audio CKT AMP & Audio Jack
TPA6017A2
USB conn x3
USB2.0 X12
Azalia
BT Conn
KB926
P6,7, 8
P9, 10, 11, 12, 13, 14
P15, 16
P25,26,27,28
P29
P30
P30
P26
P31
P33 P35
P36
P39
P38
P38
P41
P6
P6
Montevina Consumer Discrete
SPI
Clock Generator
SLG8SP553V
P17
CK505
72QFN
P29
e-SATA Connector
New Card
P31
WLAN & Robson
P36
USB Camera
MDC
FPR Conn
Touch Screen Conn
CIR Conn
Dock
Capsense switch Conn
SATA ODD Connector
P35
P19
P34
P29
P37
SPI ROM
25LF080A
Support V1.3
Discrete
P19
CRT
LVDS Panel
Interface
P18
Nvidia
NB9M-GE
P20,21,22
VRAM DDR2
page 23,24
HDMI
P42
128/512MB
64bits
Dock connecter
SATA Slave
Flash Memory Card
Controller
JMB385
7 in1 Slot
P32
P32
P39
With 3'th USB
TV out
CRT
P40
P39
P40
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Digitally signed by dd
DN: cn=dd, o=dd, ou=dd,
email=, c=US
Date: 2009.11.12 09:18:54 +07'00'
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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Notes List
Custom
353Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
O MEANS ON
X MEANS
OFF
Voltage Rails
+0.9V
S3
+3VS
X
+3VALW
+5VS
S1
+2.5VS
+CPU_CORE
+VCCP
power
plane
O
S5 S4/ Battery only
+B
State
+1.5VS
+1.8V
S5 S4/AC & Battery
don't exist
S5 S4/AC
+5VALW
S0
SERIAL
EEPROM
SMB_EC_CK2
SOURCE
KB926
INVERTER BATT
Thermal
Sensor
SODIMM CLK CHIP
SMBUS Control Table
ICH_SMBCLK
ICH_SMBDATA
ICH9
MINI CARD
SMB_EC_DA2
SMB_EC_CK1
SMB_EC_DA1
DDC2_CLK
DDC2_DATA
NB9M
X V
1 0 1 0 0 1 0 0A4
I2C / SMBUS ADDRESSING
1 0 1 0 0 0 0 0
D2
A0
CLOCK GENERATOR (EXT.)
HEX
DDR SO-DIMM 1
ADDRESS
DDR SO-DIMM 0
1 1 0 1 0 0 1 0
DEVICE
+1.8VS
O
O
O
O
O
O
O
O
O
O
O
O
O
X
X
X
X
X
X
X
XX
V
V
VVV
V
X
X
X
X
X
X
X
X
X
X
X
X
X
XX
X
KB926
+NVVDD
+PCIE
Sensor board
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
DEBUG@ : means just reserve for
debug.
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-8 MiniCard(WWAN/TV)
USB-1 Right side
USB-7 Finger Printer
USB-3 Dock
USB-9 Express card
USB-10 X
USB-2 Left side(with ESATA)
USB-0 Right side
USB-11 X
USB assignment:
PCIe-2 X
PCIe-1 TV tuner/WWAN/Robeson
PCIe assignment:
PCIe-3 WLAN
PCIe-6 New Card
PCIe-5 Card reader
PCIe-4 GLAN (Marvell)
NB9M
NB9M
Thermal
Sensor
X
V
X
V
X
X
SOURCE LVDS CRT
X
X
NB9M SMBUS Control Table
3VDDCDA
3VDDCCL
HDMIDAT_VGA
HDMICLK_VGA
NB9M
NB9M
HDMI
XX
X
X
V
V
V
G-sensor
X
X
V
www.kythuatvitinh.com
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2
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1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Power delivery
C
453Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
VIN
AC
DC BATT
B+
INVPWR_B+
B++
B+++
+NVVDDP +NVVDD
LVDS CON
+3VALW
+5VALW
ICH9
+3VAUX_BT
SPI ROM
+3VALW_EC
+3VS
Finger printer
PC Camera
MDC 1.5
New card
ICH9
0.3A
278mA
300mA
60mA
20mA
10mA
+1.8V
0.27A
NB9M (VGA)
2.725A
LAN
+3VS_DVDD
ALC268
25mA
+5VS
+VDDA
IDT 9271B7
35mA
50mA
1A
177mA
35mA
+LCDVDD
1.5A
+3VS_CK505
250mA
+5VAMP
10mA
ODD
1.8A
SATA
700mA
MCH
3.7A
DDR2 800Mhz 4G x2
8 A
+0.9V
50mA
+VCCP
ICH9
MCH
1.26A
CPU
2.3A
1.17A
LVDS CON
50mA
5.39A5.89A
3.7 X 3=11.1V
1.7A
2A
1.3A0.58A
12.11A1.9A
4.7A
7A
+V_BATTERY Dock con
1A
+1.5VS
ICH_VCC1_5
ICH9
657mA
ICH9
1.56A
2.2A0.3A
Muti Bay
1.8A
JMB385
550mA
CPU_B+ +VCC_CORE
10mA2A
CPU
34A/1.025V
NB9M (VGA)
360mA
NB9M (VGA)
390mA
+1.1V_PCIE +PCIE
0.19A
NB9M (VGA)
2A/1.1V
Mini card (WLAN)
1A
Mini card (TV tu/WWAN/Robeson)
1A
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A
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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Power sequence
Custom
553Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
www.kythuatvitinh.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_THERMDA
H_THERMDC
THERM#
SMB_EC_DA2
SMB_EC_CK2
H_PROCHOT# OCP#
H_PROCHOT#
H_THERMDC
H_THERMTRIP#
H_THERMDAH_THERMDA_R
H_THERMDC_R
H_HITM#
H_HIT#
H_RESET#
H_TRDY#
H_RS#1
H_RS#2
H_RS#0
H_LOCK#
XDP_HOOK1
XDP_HOOK1
XDP_BPM#3
XDP_DBRESET#_R
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_PRE
XDP_DBRESET#XDP_DBRESET#_R
XDP_TDI
XDP_TMS
XDP_TCK
XDP_TRST#
XDP_TCK
XDP_TDO
H_RESET#
XDP_TRST#
XDP_TMS
XDP_TDO
XDP_TDI
H_PWRGOOD_R
H_RESET#_R
XDP_BPM#5
CLK_CPU_XDP#
CLK_CPU_XDP
XDP_BPM#4
XDP_BPM#5
H_IERR#
H_A#3
H_A#10
H_A#13
H_A#11
H_ADSTB#0
H_A#7
H_A#9
H_A#16
H_A#6
H_A#8
H_A#12
H_A#15
H_A#5
H_A#14
H_A#4
H_REQ#2
H_REQ#4
H_REQ#1
H_REQ#3
H_A#32
H_A#34
H_A#35
H_A#33
H_A#18
H_A#30
H_A#27
H_A#26
H_A#21
H_A#17
H_A#20
H_A#25
H_REQ#0
H_ADSTB#1
H_A#28
H_A#29
H_A#19
H_A#23
H_A#24
H_A#22
H_A#31
H_SMI#
H_STPCLK#
H_INTR
H_IGNNE#
H_A20M#
H_FERR#
H_NMI
CLK_CPU_BCLK#
CLK_CPU_BCLK
XDP_BPM#0
XDP_BPM#2
XDP_BPM#3
XDP_TRST#
XDP_BPM#1
XDP_TCK
XDP_TMS
XDP_TDO
XDP_TDI
XDP_DBRESET#
XDP_BPM#5
XDP_BPM#4
H_BNR#
H_ADS#
H_BPRI#
H_DEFER#
H_DBSY#
H_DRDY#
H_BR0#
H_INIT#
H_IERR#
+FAN
OCP# 27
H_THERMTRIP# 9,26
H_HIT# 9
H_HITM# 9
H_RESET# 9
H_RS#0 9
H_RS#1 9
H_RS#2 9
H_TRDY# 9
H_LOCK# 9
FAN_PWM38
H_PWRGOOD7,26 CLK_CPU_XDP 17
CLK_CPU_XDP# 17
H_A#[3 16]9
H_ADSTB#09
H_REQ#09
H_REQ#19
H_REQ#29
H_A#[17 35]9
H_ADSTB#19
H_REQ#49
H_REQ#39
H_A20M#26
H_FERR#26
H_IGNNE#26
H_STPCLK#26
H_INTR26
H_NMI26
H_SMI#26
CLK_CPU_BCLK 17
CLK_CPU_BCLK# 17
XDP_DBRESET# 27
H_ADS# 9
H_BNR# 9
H_BPRI# 9
H_DEFER# 9
H_DRDY# 9
H_DBSY# 9
H_BR0# 9
H_INIT# 26
SMB_EC_CK2 21,38
SMB_EC_DA2 21,38
+3VS
+3VS
+VCCP
+VCCP
+5VS
+3VS
+VCCP+VCCP
+VCCP
+VCCP
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Penryn(1/3)-AGTL+/ITP-XDP
Custom
653Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
Address:100_1100
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
For Merom, R14 and R15 are 0ohm
For Penryn, R14 and R15 are 100ohm.
PWM Fan Control circuit
Place R191 within 200ps (~1") to CPU
This shall place near CPU
ITP-XDP Connector
Change value in 5/02
Removed at 5/30.(Follow
Chimay)
Place TP with a
GND 0.1" away
$SI change lib
#PV follow check list ver:1.5 change to 56 ohm
#PV follow check list ver:1.5 change to 51 ohm
#PV follow check list ver:1.5 change to 0 ohm
C2
0.1U_0402_16V4Z
1
2
R18
56_0402_5%
1 2
R8 51_0402_1%
1 2
R11 0_0402_1%
12
T1
@
D1
RB751V_SOD323
2 1
R12
0_0402_5%
1 2
R16
10K_0402_5%
1 2
R4 51_0402_1%
1 2
U1
EMC1402-1-ACZL-TR_MSOP8
DN
3
DP
2
VDD
1
ALERT#
6
SMCLK
8
THERM#
4
GND
5
SMDATA
7
C3
2200P_0402_50V7K
1 2
R6 54.9_0402_1%@
1 2
S
G
D
Q2
SI3456BDV-T1-E3_TSOP6
3
6
2
4 5
1
R1
1K_0402_5%
@
1 2
R15 100_0402_5%
1 2
R17
56_0402_5%
@
12
C1 0.1U_0402_16V4Z
12
R10 1K_0402_1%
1 2
C4
4.7U_0805_10V4Z
1
2
JP2
ACES_88231-02001
1
1
2
2
G1
3
G2
4
ZZZ1
PCB
C5
0.1U_0402_16V4Z
1
2
D2
RLZ5.1B_LL34
@
12
ADDR GROUP_0
ADDR GROUP_1
CONTROL
XDP/ITP SIGNALS
H CLK
THERMAL
RESERVED
ICH
JCPU1A
Penryn
A[10]#
N3
A[11]#
P5
A[12]#
P2
A[13]#
L2
A[14]#
P4
A[15]#
P1
A[16]#
R1
A[17]#
Y2
A[18]#
U5
A[19]#
R3
A[20]#
W6
A[21]#
U4
A[22]#
Y5
A[23]#
U1
A[24]#
R4
A[25]#
T5
A[26]#
T3
A[27]#
W2
A[28]#
W5
A[29]#
Y4
A[3]#
J4
A[30]#
U2
A[31]#
V4
RSVD[01]
M4
RSVD[02]
N5
RSVD[03]
T2
RSVD[04]
V3
RSVD[05]
B2
RSVD[06]
D2
RSVD[07]
D22
A[4]#
L5
A[5]#
L4
A[6]#
K5
A[7]#
M3
A[8]#
N2
A[9]#
J1
A20M#
A6
ADS#
H1
ADSTB[0]#
M1
ADSTB[1]#
V1
RSVD[08]
D3
BCLK[0]
A22
BCLK[1]
A21
BNR#
E2
BPM[0]#
AD4
BPM[1]#
AD3
BPM[2]#
AD1
BPM[3]#
AC4
BPRI#
G5
BR0#
F1
DBR#
C20
DBSY#
E1
DEFER#
H5
DRDY#
F21
FERR#
A5
HIT#
G6
HITM#
E4
IERR#
D20
IGNNE#
C4
INIT#
B3
LINT0
C6
LINT1
B4
LOCK#
H4
PRDY#
AC2
PREQ#
AC1
PROCHOT#
D21
REQ[0]#
K3
REQ[1]#
H2
REQ[2]#
K2
REQ[3]#
J3
REQ[4]#
L1
RESET#
C1
RS[0]#
F3
RS[1]#
F4
RS[2]#
G3
SMI#
A3
STPCLK#
D5
TCK
AC5
TDI
AA6
TDO
AB3
THERMTRIP#
C7
THERMDA
A24
THERMDC
B25
TMS
AB5
TRDY#
G2
TRST#
AB6
A[32]#
W3
A[33]#
AA4
A[34]#
AB2
A[35]#
AA3
RSVD[09]
F6
JP1
SAMTE_BSH-030-01-L-D-ACONN@
GND0
1
OBSFN_A0
3
OBSFN_A1
5
GND2
7
OBSDATA_A0
9
OBSDATA_A1
11
GND4
13
OBSDATA_A2
15
OBSDATA_A3
17
GND6
19
OBSFN_B0
21
OBSFN_B1
23
GND8
25
OBSDATA_B0
27
OBSDATA_B1
29
GND10
31
OBSDATA_B2
33
OBSDATA_B3
35
GND12
37
PWRGOOD/HOOK0
39
HOOK1
41
VCC_OBS_AB
43
HOOK2
45
HOOK3
47
GND14
49
SDA
51
SCL
53
TCK1
55
TCK0
57
GND16
59
GND1
2
OBSFN_C0
4
OBSFN_C1
6
GND3
8
OBSDATA_C0
10
OBSDATA_C1
12
GND5
14
OBSDATA_C2
16
OBSDATA_C3
18
GND7
20
OBSFN_D0
22
OBSFN_D1
24
GND9
26
OBSDATA_D0
28
OBSDATA_D1
30
GND11
32
OBSDATA_D2
34
OBSDATA_D3
36
GND13
38
ITPCLK/HOOK4
40
ITPCLK#/HOOK5
42
VCC_OBS_CD
44
RESET#/HOOK6
46
DBR#/HOOK7
48
GND15
50
TD0
52
TRST#
54
TDI
56
TMS
58
GND17
60
E
B
C
Q1
MMBT3904_NL_SOT23-3
@
2
3 1
R5 51_0402_1%
1 2
R14 100_0402_5%
1 2
R13 56_0402_1%
1 2
R7 51_0402_1%
1 2
R2 51_0402_1%
1 2
R9
1K_0402_5%
12
R3 51_0402_1%
1 2
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+V_CPU_GTLREF
H_D#4
H_D#14
H_D#10
H_D#9
H_D#3
H_D#13
H_D#6
H_D#2
H_D#8
H_D#12
H_D#1
H_D#5
H_D#7
H_D#11
H_D#0
H_D#15
H_D#27
H_D#25
H_D#31
H_D#24
H_D#20
H_D#30
H_D#23
H_D#19
H_D#29
H_D#16
H_D#18
H_D#22
H_D#26
H_D#28
H_D#17
H_D#21
H_DINV#0
H_DINV#1
H_DSTBP#1
H_DSTBN#1
H_DSTBP#0
H_DSTBN#0
+VCCPA
+VCCPB
VSSSENSE
VCCSENSE
VSSSENSE
VCCSENSE
+V_CPU_GTLREF
TEST4
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
TEST1
TEST2
TEST3
TEST5
TEST6
TEST7
H_D#35
H_D#46
H_D#47
H_D#37
H_D#34
H_D#41
H_D#45
H_D#43
H_D#33
H_D#39
H_D#40
H_D#44
H_D#32
H_D#42
H_D#38
H_D#36
H_DINV#2
H_DSTBN#2
H_DSTBP#2
H_DINV#3
H_DSTBN#3
H_DSTBP#3
H_D#48
H_D#56
H_D#52
H_D#59
H_D#63
H_D#55
H_D#51
H_D#62
H_D#58
H_D#54
H_D#50
H_D#57
H_D#61
H_D#53
H_D#49
H_D#60
COMP0
COMP2
COMP3
COMP1
H_PWRGOOD
H_CPUSLP#
H_DPSLP#
H_DPRSTP#
H_PSI#
H_DPWR#
VCCSENSE 49
VSSSENSE 49
H_D#[0 15]9
H_DSTBN#09
H_DSTBP#09
H_DINV#09
H_D#[16 31]9
H_DSTBN#19
H_DSTBP#19
H_DINV#19
CPU_VID0 49
CPU_VID1 49
CPU_VID2 49
CPU_VID3 49
CPU_VID4 49
CPU_VID5 49
CPU_VID6 49
CPU_BSEL017
CPU_BSEL117
CPU_BSEL217
H_D#[32 47] 9
H_DSTBN#2 9
H_DSTBP#2 9
H_DINV#2 9
H_D#[48 63] 9
H_DSTBN#3 9
H_DSTBP#3 9
H_DINV#3 9
H_DPRSTP# 9,26,49
H_DPSLP# 26
H_CPUSLP# 9
H_DPWR# 9
H_PWRGOOD 6,26
H_PSI# 49
+VCCP
+VCCP
+1.5VS
+VCC_CORE +VCC_CORE
+VCC_CORE
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Penryn(2/3)-AGTL+/ITP-XDP
Custom
753Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
Close to CPU pin AD26
within 500mils.
CPU_BSEL CPU_BSEL2 CPU_BSEL1
166
200
01
CPU_BSEL0
Resistor placed within 0.5"
of CPU pin.Trace should be
at least 25 mils away from
any other toggling signal.
COMP[0,2] trace width is 18
mils. COMP[1,3] trace width
is 4 mils.
Length match within 25 mils.
The trace width/space/other is 20/7/25.
Close to CPU pin within
500mils.
Near pin B26
* Route the TEST3 and TEST5 signals through
a ground referenced Zo = 55-ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope
connection.
266
1
10
00
0
0
T2
@
R19
0_0402_5%
1 2
R26
27.4_0402_1%
12
C7
10U_0805_6.3V6M
1
2
R21 1K_0402_5%@
1 2
C8
0.01U_0402_16V7K
1
2
JCPU1C
Penryn
.
VCC[001]
A7
VCC[002]
A9
VCC[003]
A10
VCC[004]
A12
VCC[005]
A13
VCC[006]
A15
VCC[007]
A17
VCC[008]
A18
VCC[009]
A20
VCC[010]
B7
VCC[011]
B9
VCC[012]
B10
VCC[013]
B12
VCC[014]
B14
VCC[015]
B15
VCC[016]
B17
VCC[017]
B18
VCC[018]
B20
VCC[019]
C9
VCC[020]
C10
VCC[021]
C12
VCC[022]
C13
VCC[023]
C15
VCC[024]
C17
VCC[025]
C18
VCC[026]
D9
VCC[027]
D10
VCC[028]
D12
VCC[029]
D14
VCC[030]
D15
VCC[031]
D17
VCC[032]
D18
VCC[033]
E7
VCC[034]
E9
VCC[035]
E10
VCC[036]
E12
VCC[037]
E13
VCC[038]
E15
VCC[039]
E17
VCC[040]
E18
VCC[041]
E20
VCC[042]
F7
VCC[043]
F9
VCC[044]
F10
VCC[045]
F12
VCC[046]
F14
VCC[047]
F15
VCC[048]
F17
VCC[049]
F18
VCC[050]
F20
VCC[051]
AA7
VCC[052]
AA9
VCC[053]
AA10
VCC[054]
AA12
VCC[055]
AA13
VCC[056]
AA15
VCC[057]
AA17
VCC[058]
AA18
VCC[059]
AA20
VCC[060]
AB9
VCC[061]
AC10
VCC[062]
AB10
VCC[063]
AB12
VCC[064]
AB14
VCC[065]
AB15
VCC[066]
AB17
VCC[067]
AB18
VCC[068]
AB20
VCC[069]
AB7
VCC[070]
AC7
VCC[071]
AC9
VCC[072]
AC12
VCC[073]
AC13
VCC[074]
AC15
VCC[075]
AC17
VCC[076]
AC18
VCC[077]
AD7
VCC[078]
AD9
VCC[079]
AD10
VCC[080]
AD12
VCC[081]
AD14
VCC[082]
AD15
VCC[083]
AD17
VCC[084]
AD18
VCC[085]
AE9
VCC[086]
AE10
VCC[087]
AE12
VCC[088]
AE13
VCC[089]
AE15
VCC[090]
AE17
VCC[091]
AE18
VCC[092]
AE20
VCC[093]
AF9
VCC[094]
AF10
VCC[095]
AF12
VCC[096]
AF14
VCC[097]
AF15
VCC[098]
AF17
VCC[099]
AF18
VCC[100]
AF20
VCCA[01]
B26
VCCP[03]
J6
VCCP[04]
K6
VCCP[05]
M6
VCCP[06]
J21
VCCP[07]
K21
VCCP[08]
M21
VCCP[09]
N21
VCCP[10]
N6
VCCP[11]
R21
VCCP[12]
R6
VCCP[13]
T21
VCCP[14]
T6
VCCP[15]
V21
VCCP[16]
W21
VCCSENSE
AF7
VID[0]
AD6
VID[1]
AF5
VID[2]
AE5
VID[3]
AF4
VID[4]
AE3
VID[5]
AF3
VID[6]
AE2
VSSSENSE
AE7
VCCA[02]
C26
VCCP[01]
G21
VCCP[02]
V6
R24
27.4_0402_1%
12
R30 100_0402_1%
1 2
R22 1K_0402_5%@
1 2
T6
R28 100_0402_1%
1 2
DATA GRP 0
DATA GRP 1
DATA GRP 2DATA GRP 3
MISC
JCPU1B
Penryn
COMP[0]
R26
COMP[1]
U26
COMP[2]
AA1
COMP[3]
Y1
D[0]#
E22
D[1]#
F24
D[10]#
J24
D[11]#
J23
D[12]#
H22
D[13]#
F26
D[14]#
K22
D[15]#
H23
D[16]#
N22
D[17]#
K25
D[18]#
P26
D[19]#
R23
D[2]#
E26
D[20]#
L23
D[21]#
M24
D[22]#
L22
D[23]#
M23
D[24]#
P25
D[25]#
P23
D[26]#
P22
D[27]#
T24
D[28]#
R24
D[29]#
L25
D[3]#
G22
D[30]#
T25
D[31]#
N25
D[32]#
Y22
D[33]#
AB24
D[34]#
V24
D[35]#
V26
D[36]#
V23
D[37]#
T22
D[38]#
U25
D[39]#
U23
D[4]#
F23
D[40]#
Y25
D[41]#
W22
D[42]#
Y23
D[43]#
W24
D[44]#
W25
D[45]#
AA23
D[46]#
AA24
D[47]#
AB25
D[48]#
AE24
D[49]#
AD24
D[5]#
G25
D[50]#
AA21
D[51]#
AB22
D[52]#
AB21
D[53]#
AC26
D[54]#
AD20
D[55]#
AE22
D[56]#
AF23
D[57]#
AC25
D[58]#
AE21
D[59]#
AD21
D[6]#
E25
D[60]#
AC22
D[61]#
AD23
D[62]#
AF22
D[63]#
AC23
D[7]#
E23
D[8]#
K24
D[9]#
G24
TEST5
AF1
DINV[0]#
H25
DINV[1]#
N24
DINV[2]#
U22
DINV[3]#
AC20
DPRSTP#
E5
DPSLP#
B5
DPWR#
D24
DSTBN[0]#
J26
DSTBN[1]#
L26
DSTBN[2]#
Y26
DSTBN[3]#
AE25
DSTBP[0]#
H26
DSTBP[1]#
M26
DSTBP[2]#
AA26
DSTBP[3]#
AF24
GTLREF
AD26
PSI#
AE6
PWRGOOD
D6
SLP#
D7
TEST3
C24
BSEL[0]
B22
BSEL[1]
B23
BSEL[2]
C21
TEST2
D25
TEST4
AF26
TEST6
A26
TEST1
C23
TEST7
C3
T4
T5
R20
0_0402_5%
1 2
R23
54.9_0402_1%
12
R29
2K_0402_1%
12
R27
1K_0402_1%
12
R25
54.9_0402_1%
12
+
C6
330U_D2E_2.5VM_R7
1
2
T3
@
www.kythuatvitinh.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCCP
+VCC_CORE
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Penryn(3/3)-AGTL+/ITP-XDP
Custom
853Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
Inside CPU center cavity in 2 rows
Mid Frequence Decoupling
Place these capacitors on
L8 (North side,Secondary
Layer)
ESR <= 1.5m ohm
Capacitor > 1980uF
Near CPU CORE regulator
5
5
5
5
5
Place these capacitors on
L8 (North side,Secondary
Layer)
Place these capacitors on
L8 (North side,Secondary
Layer)
Place these capacitors on
L8 (North side,Secondary
Layer)
#SI change to 7m ohm
C30
10U_0805_6.3V6M
1
2
+
C44
330U_D2E_2.5VM_R7
1
2
C18
10U_0805_6.3V6M
1
2
C50
0.1U_0402_10V6K
1
2
C38
10U_0805_6.3V6M
1
2
C34
10U_0805_6.3V6M
1
2
C48
0.1U_0402_10V6K
1
2
C45
0.1U_0402_10V6K
1
2
C39
10U_0805_6.3V6M
1
2
C31
10U_0805_6.3V6M
1
2
C20
10U_0805_6.3V6M
1
2
C25
10U_0805_6.3V6M
1
2
C19
10U_0805_6.3V6M
1
2
C29
10U_0805_6.3V6M
1
2
C17
10U_0805_6.3V6M
1
2
C24
10U_0805_6.3V6M
1
2
C47
0.1U_0402_10V6K
1
2
C23
10U_0805_6.3V6M
1
2
C28
10U_0805_6.3V6M
1
2
C10
10U_0805_6.3V6M
1
2
C46
0.1U_0402_10V6K
1
2
C36
10U_0805_6.3V6M
1
2
C33
10U_0805_6.3V6M
1
2
C21
10U_0805_6.3V6M
1
2
C22
10U_0805_6.3V6M
1
2
C27
10U_0805_6.3V6M
1
2
C49
0.1U_0402_10V6K
1
2
+
C43
330U_D2E_2.5VM_R7
1
2
C37
10U_0805_6.3V6M
1
2
JCPU1D
Penryn
.
VSS[082]
P6
VSS[148]
AE11
VSS[002]
A8
VSS[003]
A11
VSS[004]
A14
VSS[005]
A16
VSS[006]
A19
VSS[007]
A23
VSS[008]
AF2
VSS[009]
B6
VSS[010]
B8
VSS[011]
B11
VSS[012]
B13
VSS[013]
B16
VSS[014]
B19
VSS[015]
B21
VSS[016]
B24
VSS[017]
C5
VSS[018]
C8
VSS[019]
C11
VSS[020]
C14
VSS[021]
C16
VSS[022]
C19
VSS[023]
C2
VSS[024]
C22
VSS[025]
C25
VSS[026]
D1
VSS[027]
D4
VSS[028]
D8
VSS[029]
D11
VSS[030]
D13
VSS[031]
D16
VSS[032]
D19
VSS[033]
D23
VSS[034]
D26
VSS[035]
E3
VSS[036]
E6
VSS[037]
E8
VSS[038]
E11
VSS[039]
E14
VSS[040]
E16
VSS[041]
E19
VSS[042]
E21
VSS[043]
E24
VSS[044]
F5
VSS[045]
F8
VSS[046]
F11
VSS[047]
F13
VSS[048]
F16
VSS[049]
F19
VSS[050]
F2
VSS[051]
F22
VSS[052]
F25
VSS[053]
G4
VSS[054]
G1
VSS[055]
G23
VSS[056]
G26
VSS[057]
H3
VSS[058]
H6
VSS[059]
H21
VSS[060]
H24
VSS[061]
J2
VSS[062]
J5
VSS[063]
J22
VSS[064]
J25
VSS[065]
K1
VSS[066]
K4
VSS[067]
K23
VSS[068]
K26
VSS[069]
L3
VSS[070]
L6
VSS[071]
L21
VSS[072]
L24
VSS[073]
M2
VSS[074]
M5
VSS[075]
M22
VSS[076]
M25
VSS[077]
N1
VSS[078]
N4
VSS[079]
N23
VSS[080]
N26
VSS[081]
P3
VSS[162]
A25
VSS[161]
AF21
VSS[160]
AF19
VSS[159]
AF16
VSS[158]
AF13
VSS[157]
AF11
VSS[156]
AF8
VSS[155]
AF6
VSS[154]
A2
VSS[153]
AE26
VSS[152]
AE23
VSS[151]
AE19
VSS[083]
P21
VSS[084]
P24
VSS[085]
R2
VSS[086]
R5
VSS[087]
R22
VSS[088]
R25
VSS[089]
T1
VSS[090]
T4
VSS[091]
T23
VSS[092]
T26
VSS[093]
U3
VSS[094]
U6
VSS[095]
U21
VSS[096]
U24
VSS[097]
V2
VSS[098]
V5
VSS[099]
V22
VSS[100]
V25
VSS[101]
W1
VSS[102]
W4
VSS[103]
W23
VSS[104]
W26
VSS[105]
Y3
VSS[107]
Y21
VSS[108]
Y24
VSS[109]
AA2
VSS[110]
AA5
VSS[111]
AA8
VSS[112]
AA11
VSS[113]
AA14
VSS[114]
AA16
VSS[115]
AA19
VSS[116]
AA22
VSS[117]
AA25
VSS[118]
AB1
VSS[119]
AB4
VSS[120]
AB8
VSS[121]
AB11
VSS[122]
AB13
VSS[123]
AB16
VSS[124]
AB19
VSS[125]
AB23
VSS[126]
AB26
VSS[127]
AC3
VSS[128]
AC6
VSS[129]
AC8
VSS[130]
AC11
VSS[131]
AC14
VSS[132]
AC16
VSS[133]
AC19
VSS[134]
AC21
VSS[135]
AC24
VSS[136]
AD2
VSS[137]
AD5
VSS[138]
AD8
VSS[139]
AD11
VSS[140]
AD13
VSS[141]
AD16
VSS[142]
AD19
VSS[143]
AD22
VSS[144]
AD25
VSS[145]
AE1
VSS[146]
AE4
VSS[106]
Y6
VSS[001]
A4
VSS[149]
AE14
VSS[150]
AE16
VSS[147]
AE8
VSS[163]
AF25
C9
10U_0805_6.3V6M
1
2
C40
10U_0805_6.3V6M
1
2
C15
10U_0805_6.3V6M
1
2
C16
10U_0805_6.3V6M
1
2
+
C41
330U_D2E_2.5VM_R7
@
1
2
C35
10U_0805_6.3V6M
1
2
C14
10U_0805_6.3V6M
1
2
C12
10U_0805_6.3V6M
1
2
C11
10U_0805_6.3V6M
1
2
C13
10U_0805_6.3V6M
1
2
C32
10U_0805_6.3V6M
1
2
C26
10U_0805_6.3V6M
1
2
+
C42
330U_D2E_2.5VM_R7
<BOM Structure>
1
2
www.kythuatvitinh.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PM_EXTTS#0
V_DDR_MCH_REF
H_RCOMP
CLKREQ#_7
+H_SWNG
H_D#32
H_D#24
H_D#19
H_D#59
H_D#42
H_D#36
H_D#3
H_D#40
H_RCOMP
H_D#55
H_D#4
H_D#60
H_D#30
H_D#34
H_D#27
H_D#1
H_D#23
H_D#51
H_D#48
H_D#46
H_D#44
H_D#39
H_D#22
H_D#15
H_D#14
H_D#9
H_D#56
H_D#54
H_D#8
H_RESET#
H_D#37
H_D#35
H_D#28
H_D#25
H_D#12
H_D#38
H_D#26
H_D#11
H_D#7
H_D#53
H_D#52
H_D#41
H_D#18
H_D#10
+H_VREF
H_D#57
H_D#33
H_D#29
+H_SWNG
H_D#6
H_D#45
H_D#43
H_D#20
H_D#61
H_D#17
H_D#63
H_D#58
H_D#21
H_D#16
H_D#50
H_CPUSLP#
H_D#62
H_D#5
H_D#49
H_D#31
H_D#2
H_D#47
H_D#13
H_D#0
H_A#7
H_A#12
H_A#32
H_A#24
H_A#3
H_A#18
H_A#21
H_A#16
H_A#19
H_A#31
H_A#27
H_A#5
H_A#30
H_A#9
H_A#26
H_A#14
H_A#11
H_A#22
H_A#23
H_A#34
H_A#20
H_A#8
H_A#15
H_A#6
H_A#25
H_A#17
H_A#4
H_A#13
H_A#33
H_A#29
H_A#28
H_A#10
H_A#35
CLK_MCH_BCLK#
H_LOCK#
CLK_MCH_BCLK
H_ADSTB#1
H_DEFER#
H_HITM#
H_ADS#
H_BR0#
H_DBSY#
H_HIT#
H_BPRI#
H_DRDY#
H_BNR#
H_DPWR#
H_ADSTB#0
H_TRDY#
+H_VREF
H_DINV#0
H_DINV#3
H_DINV#1
H_DINV#2
H_DSTBN#1
H_DSTBN#3
H_DSTBN#0
H_DSTBN#2
H_DSTBP#2
H_DSTBP#0
H_DSTBP#3
H_DSTBP#1
H_REQ#0
H_REQ#3
H_REQ#1
H_REQ#4
H_REQ#2
H_RS#1
H_RS#0
H_RS#2
MCH_CLKSEL0
SMRCOMP_VOL
+CL_VREF
MCH_ICH_SYNC#
CLKREQ#_7
CL_CLK0
CL_DATA0
CL_RST#
M_PWROK
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
CLK_MCH_3GPLL#
CLK_MCH_3GPLL
SM_PWROK
TP_SM_DRAMRST#
SM_REXT
V_DDR_MCH_REF
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
M_CLK_DDR2
M_CLK_DDR0
M_CLK_DDR1
SMRCOMP_VOH
SMRCOMP_VOL
M_ODT1
SMRCOMP#
M_ODT3
M_ODT0
M_ODT2
SMRCOMP
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE3_DIMMB
DDR_CS1_DIMMA#
DDR_CKE2_DIMMB
DDR_CS0_DIMMA#
DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
MCH_CLKSEL1
MCH_CLKSEL2
CFG11
CFG9
CFG7
CFG10
CFG6
CFG14
CFG16
CFG15
CFG17
CFG8
CFG5
CFG13
CFG18
CFG19
CFG12
CFG20
H_DPRSTP#
THERMTRIP#
PM_PWROK
PM_EXTTS#1
PM_EXTTS#0
PM_BMBUSY#
DPRSLPVR
SMRCOMP_VOH
PLT_RST#
PM_EXTTS#1
TSATN#
V_DDR_MCH_REF15,16
H_D#[0 63]7
H_CPUSLP#7
H_RESET#6
H_A#[3 35] 6
H_ADS# 6
H_ADSTB#1 6
H_ADSTB#0 6
H_BPRI# 6
H_BNR# 6
H_DEFER# 6
H_BR0# 6
H_DBSY# 6
CLK_MCH_BCLK 17
CLK_MCH_BCLK# 17
H_DPWR# 7
H_DRDY# 6
H_HIT# 6
H_HITM# 6
H_LOCK# 6
H_TRDY# 6
H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7
H_DSTBN#0 7
H_DSTBN#1 7
H_DSTBN#2 7
H_DSTBN#3 7
H_DSTBP#0 7
H_DSTBP#1 7
H_DSTBP#2 7
H_DSTBP#3 7
H_REQ#3 6
H_REQ#2 6
H_REQ#1 6
H_REQ#4 6
H_REQ#0 6
H_RS#2 6
H_RS#1 6
H_RS#0 6
MCH_CLKSEL017
MCH_CLKSEL117
MCH_CLKSEL217
TSATN# 38
MCH_ICH_SYNC# 27
CL_CLK0 27
CL_DATA0 27
M_PWROK 27,38
CL_RST# 27
DMI_TXP0 27
DMI_RXN0 27
DMI_RXP0 27
DMI_TXN0 27
DMI_TXN1 27
DMI_TXN2 27
DMI_TXN3 27
DMI_TXP1 27
DMI_TXP2 27
DMI_TXP3 27
DMI_RXN1 27
DMI_RXN2 27
DMI_RXN3 27
DMI_RXP1 27
DMI_RXP2 27
DMI_RXP3 27
CLK_MCH_3GPLL 17
CLK_MCH_3GPLL# 17
DDR_CKE0_DIMMA 15
DDR_CKE1_DIMMA 15
DDR_CKE2_DIMMB 16
DDR_CKE3_DIMMB 16
DDR_CS0_DIMMA# 15
DDR_CS1_DIMMA# 15
DDR_CS2_DIMMB# 16
DDR_CS3_DIMMB# 16
M_CLK_DDR0 15
M_CLK_DDR1 15
M_CLK_DDR2 16
M_CLK_DDR3 16
M_CLK_DDR#0 15
M_CLK_DDR#1 15
M_CLK_DDR#2 16
M_CLK_DDR#3 16
M_ODT0 15
M_ODT1 15
M_ODT2 16
M_ODT3 16
CLKREQ#_7 17
CFG511
CFG911
CFG1111
CFG1011
CFG611
CFG711
CFG1311
CFG1211
CFG1611
CFG1811
CFG2011
CFG1911
CFG811
CFG1411
CFG1511
CFG1711
PM_BMBUSY#27
H_DPRSTP#7,26,49
PM_EXTTS#015
DPRSLPVR27,49
PM_EXTTS#116
PM_PWROK27,38
H_THERMTRIP#6,26
PLT_RST#20,25,30,31,32
+VCCP
+VCCP
+3VS
+1.8V
+1.8V
+VCCP
+1.8V
+VCCP
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Cantiga(1/6)-AGTL/DMI/DDR
Custom
953Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
Layout Note: V_DDR_MCH_REF
trace width and spacing is 20/20.
Near B3 pinwithin 100 mils from NB
Layout note:
Route H_SCOMP and H_SCOMP# with trace
width, spacing and impedance (55 ohm) same as
FSB data traces
0621 add CLK and DAT for DVI
Follow Design Guide
For Cantiga: 80.6ohm
80% of 1.8V VCC_SM
20% of 1.8V VCC_SM
#PV follow check list ver:1.5 change to 10K ohm
T18
R48
10K_0402_1%
12
T24
T29 PAD
@
T9
T10
R35 80.6_0402_1%
1 2
R47
221_0603_1%
12
C53
2.2U_0603_6.3V4Z
1
2
T27
R45
10K_0402_1%
12
HOST
U2A
CANTIGA ES_FCBGA1329
H_A#_10
P16
H_A#_11
R16
H_A#_12
N17
H_A#_13
M13
H_A#_14
E17
H_A#_15
P17
H_A#_16
F17
H_A#_17
G20
H_A#_18
B19
H_A#_19
J16
H_A#_20
E20
H_A#_21
H16
H_A#_22
J20
H_A#_23
L17
H_A#_24
A17
H_A#_25
B17
H_A#_26
L16
H_A#_27
C21
H_A#_28
J17
H_A#_29
H20
H_A#_3
A14
H_A#_30
B18
H_A#_31
K17
H_A#_4
C15
H_A#_5
F16
H_A#_6
H13
H_A#_7
C18
H_A#_8
M16
H_A#_9
J13
H_ADS#
H12
H_ADSTB#_0
B16
H_ADSTB#_1
G17
H_BNR#
A9
H_BPRI#
F11
H_BREQ#
G12
HPLL_CLK#
AH6
H_CPURST#
C12
HPLL_CLK
AH7
H_D#_0
F2
H_REQ#_2
F13
H_REQ#_3
B13
H_D#_1
G8
H_D#_10
M9
H_D#_20
L6
H_D#_30
N10
H_D#_40
AA8
H_D#_50
AA2
H_D#_60
AE11
H_D#_8
D4
H_D#_9
H3
H_DBSY#
B10
H_D#_11
M11
H_D#_12
J1
H_D#_13
J2
H_D#_14
N12
H_D#_15
J6
H_D#_16
P2
H_D#_17
L2
H_D#_18
R2
H_D#_19
N9
H_D#_2
F8
H_D#_21
M5
H_D#_22
J3
H_D#_23
N2
H_D#_24
R1
H_D#_25
N5
H_D#_26
N6
H_D#_27
P13
H_D#_28
N8
H_D#_29
L7
H_D#_3
E6
H_D#_31
M3
H_D#_32
Y3
H_D#_33
AD14
H_D#_34
Y6
H_D#_35
Y10
H_D#_36
Y12
H_D#_37
Y14
H_D#_38
Y7
H_D#_39
W2
H_D#_4
G2
H_D#_41
Y9
H_D#_42
AA13
H_D#_43
AA9
H_D#_44
AA11
H_D#_45
AD11
H_D#_46
AD10
H_D#_47
AD13
H_D#_48
AE12
H_D#_49
AE9
H_D#_5
H6
H_D#_51
AD8
H_D#_52
AA3
H_D#_53
AD3
H_D#_54
AD7
H_D#_55
AE14
H_D#_56
AF3
H_D#_57
AC1
H_D#_58
AE3
H_D#_59
AC3
H_D#_6
H2
H_D#_61
AE8
H_D#_62
AG2
H_D#_63
AD6
H_D#_7
F6
H_DEFER#
E9
H_DINV#_0
J8
H_DINV#_1
L3
H_DINV#_2
Y13
H_DINV#_3
Y1
H_DPWR#
J11
H_DRDY#
F9
H_DSTBN#_0
L10
H_DSTBN#_1
M7
H_DSTBN#_2
AA5
H_DSTBN#_3
AE6
H_DSTBP#_0
L9
H_DSTBP#_1
M8
H_DSTBP#_2
AA6
H_DSTBP#_3
AE5
H_AVREF
A11
H_DVREF
B11
H_TRDY#
C9
H_HIT#
H9
H_HITM#
E12
H_LOCK#
H11
H_REQ#_0
B15
H_REQ#_1
K13
H_REQ#_4
B14
H_A#_32
B20
H_A#_33
F21
H_A#_34
K21
H_A#_35
L20
H_SWING
C5
H_CPUSLP#
E11
H_RCOMP
E3
H_RS#_0
B6
H_RS#_1
F12
H_RS#_2
C8
C56
0.1U_0402_16V4Z
1
2
T26
T16
C52
0.01U_0402_25V7K
1
2
R34 80.6_0402_1%
1 2
T7
R37 499_0402_1%
1 2
C59
0.1U_0402_16V4Z
1
2
T23
T33
R44
499_0402_1%
12
C55
0.1U_0402_16V4Z
@
1
2
T22
R33
1K_0402_1%
12
T13
R32
3.01K_0402_1%
12
T35
T30
T11
T31
C54
0.01U_0402_25V7K
1
2
R40 10K_0402_5%
1 2
T37
T8
R39 10K_0402_5%
1 2
R46
1K_0402_1%
12
C57
0.1U_0402_16V4Z
1
2
T21
R55
100_0402_1%
12
T14
T20
T34
T12
T19
R52
2K_0402_1%
12
R41
100_0402_5%
1 2
R31
1K_0402_1%
12
R49
56_0402_5%
1 2
R43
1K_0402_1%
12
T28
T25
C58
0.1U_0402_16V4Z
1
2
R38 10K_0402_5%
1 2
R54
24.9_0402_1%
12
T36
T32
T15
T17
R36 0_0402_5%
1 2
R42
0_0402_5%
1 2
PM
MISC
NC
DDR CLK/ CONTROL/COMPENSATION
CLK
DMI
CFG
RSVD
GRAPHICS VID
MEHDA
U2B
CANTIGA ES_FCBGA1329
SA_CK_0
AP24
SA_CK_1
AT21
SB_CK_0
AV24
SA_CK#_0
AR24
SA_CK#_1
AR21
SB_CK#_0
AU24
SA_CKE_0
BC28
SA_CKE_1
AY28
SB_CKE_0
AY36
SB_CKE_1
BB36
SA_CS#_0
BA17
SA_CS#_1
AY16
SB_CS#_0
AV16
SB_CS#_1
AR13
SM_DRAMRST#
BC36
SA_ODT_0
BD17
SA_ODT_1
AY17
SB_ODT_0
BF15
SB_ODT_1
AY13
SM_RCOMP
BG22
SM_RCOMP#
BH21
CFG_18
P29
CFG_19
R28
CFG_2
P25
CFG_0
T25
CFG_1
R25
CFG_20
T28
CFG_3
P20
CFG_4
P24
CFG_5
C25
CFG_6
N24
CFG_7
M24
CFG_8
E21
CFG_9
C23
CFG_10
C24
CFG_11
N21
CFG_12
P21
CFG_13
T21
CFG_14
R20
CFG_15
M20
CFG_16
L21
CFG_17
H21
PM_SYNC#
R29
PM_EXT_TS#_0
N33
PM_EXT_TS#_1
P32
PWROK
AT40
RSTIN#
AT11
DPLL_REF_CLK
B38
DPLL_REF_CLK#
A38
DPLL_REF_SSCLK
E41
DPLL_REF_SSCLK#
F41
DMI_RXN_0
AE41
DMI_RXN_1
AE37
DMI_RXN_2
AE47
DMI_RXN_3
AH39
DMI_RXP_0
AE40
DMI_RXP_1
AE38
DMI_RXP_2
AE48
DMI_RXP_3
AH40
DMI_TXN_0
AE35
DMI_TXN_1
AE43
DMI_TXN_2
AE46
DMI_TXN_3
AH42
DMI_TXP_0
AD35
DMI_TXP_1
AE44
DMI_TXP_2
AF46
DMI_TXP_3
AH43
RESERVED
AL34
RESERVED
AN35
RESERVED
AK34
RESERVED
AM35
RESERVED
BG23
RESERVED
BF23
RESERVED
BH18
RESERVED
BF18
PM_DPRSTP#
B7
SB_CK_1
AU20
SB_CK#_1
AV20
RESERVED
AY21
RESERVED
AH9
RESERVED
AH10
RESERVED
AH12
RESERVED
AH13
RESERVED
M36
RESERVED
N36
RESERVED
R33
RESERVED
T33
GFX_VID_0
B33
GFX_VID_1
B32
GFX_VID_2
G33
GFX_VID_3
F33
GFX_VR_EN
C34
SM_RCOMP_VOH
BF28
SM_RCOMP_VOL
BH28
THERMTRIP#
T20
DPRSLPVR
R32
RESERVED
K12
CL_CLK
AH37
CL_DATA
AH36
CL_PWROK
AN36
CL_RST#
AJ35
CL_VREF
AH34
NC
A47
NC
BG48
NC
BF48
NC
BD48
NC
BC48
NC
BH47
NC
BG47
NC
BE47
NC
BH46
NC
BF46
NC
BG45
NC
BH44
NC
BH43
NC
BH6
NC
BH5
NC
BG4
SDVO_CTRLCLK
G36
SDVO_CTRLDATA
E36
CLKREQ#
K36
RESERVED
T24
ICH_SYNC#
H36
TSATN#
B12
PEG_CLK#
E43
PEG_CLK
F43
NC
BH3
GFX_VID_4
E33
RESERVED
B31
DDPC_CTRLCLK
N28
NC
BF3
NC
BH2
NC
BG2
NC
BE2
NC
BG1
NC
BF1
NC
BD1
NC
BC1
NC
F1
SM_VREF
AV42
SM_PWROK
AR36
SM_REXT
BF17
RESERVED
M1
HDA_BCLK
B28
HDA_RST#
B30
HDA_SDI
B29
HDA_SDO
C29
HDA_SYNC
A28
DDPC_CTRLDATA
M28
RESERVED
B2
C51
2.2U_0603_6.3V4Z
1
2
www.kythuatvitinh.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_MA0
DDR_A_MA1
DDR_A_MA4
DDR_A_MA2
DDR_A_MA3
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12
DDR_A_MA13
DDR_A_MA11
DDR_A_MA10
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#3
DDR_A_DQS#2
DDR_A_DQS#5
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DM7
DDR_A_DM5
DDR_A_DM2
DDR_A_DM1
DDR_A_DM6
DDR_A_DM4
DDR_A_DM0
DDR_A_DM3
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D53
DDR_A_D52
DDR_A_D47
DDR_A_D46
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D45
DDR_A_D44
DDR_A_D39
DDR_A_D38
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D37
DDR_A_D36
DDR_A_D31
DDR_A_D30
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D15
DDR_A_D14
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D13
DDR_A_D12
DDR_A_D29
DDR_A_D28
DDR_A_D23
DDR_A_D22
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D21
DDR_A_D20
DDR_A_D8
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D7
DDR_A_D6
DDR_A_D2
DDR_A_D1
DDR_A_D0
DDR_A_MA14
DDR_B_RAS#
DDR_B_MA14
DDR_B_MA10
DDR_B_DQS#7
DDR_B_DQS#2
DDR_B_DQS7
DDR_B_DQS2
DDR_B_DM3
DDR_B_D51
DDR_B_D39
DDR_B_D18
DDR_B_MA7
DDR_B_DQS0
DDR_B_D7
DDR_B_D54
DDR_B_D4
DDR_B_D36
DDR_B_D21
DDR_B_MA4
DDR_B_DM0
DDR_B_D62
DDR_B_D34
DDR_B_D19
DDR_B_D13
DDR_B_MA5
DDR_B_MA11
DDR_B_BS2
DDR_B_D42
DDR_B_D35
DDR_B_D31
DDR_B_D24
DDR_B_D15
DDR_B_MA3
DDR_B_DQS#6
DDR_B_DM7
DDR_B_D50
DDR_B_D38
DDR_B_D32
DDR_B_D23
DDR_B_MA6
DDR_B_D6
DDR_B_D53
DDR_B_D33
DDR_B_D3
DDR_B_D20
DDR_B_DQS#5
DDR_B_BS1
DDR_B_D61
DDR_B_D59
DDR_B_D46
DDR_B_D12
DDR_B_DQS3
DDR_B_D47
DDR_B_D30
DDR_B_D14
DDR_B_MA0
DDR_B_DQS#0
DDR_B_DM6
DDR_B_DM4
DDR_B_D55
DDR_B_D44
DDR_B_D29
DDR_B_D27
DDR_B_D22
DDR_B_MA13
DDR_B_MA1
DDR_B_D57
DDR_B_D52
DDR_B_D2
DDR_B_D17
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D9
DDR_B_D60
DDR_B_D58
DDR_B_D45
DDR_B_DQS4
DDR_B_MA9
DDR_B_DQS#4
DDR_B_DM5
DDR_B_DM2
DDR_B_D49
DDR_B_D41
DDR_B_D28
DDR_B_D11
DDR_B_WE#
DDR_B_MA12
DDR_B_D56
DDR_B_D48
DDR_B_D16
DDR_B_D1
DDR_B_MA2
DDR_B_DQS5
DDR_B_D8
DDR_B_D63
DDR_B_D37
DDR_B_D0
DDR_B_BS0
DDR_B_D5
DDR_B_MA8
DDR_B_DQS#3
DDR_B_DQS6
DDR_B_DM1
DDR_B_CAS#
DDR_B_D43
DDR_B_D40
DDR_B_D26
DDR_B_D25
DDR_B_D10
DDR_A_BS0 15
DDR_A_BS1 15
DDR_A_BS2 15
DDR_A_D[0 63]15
DDR_A_MA[0 14] 15
DDR_A_DQS#[0 7] 15
DDR_A_DQS[0 7] 15
DDR_A_DM[0 7] 15
DDR_A_CAS# 15
DDR_A_RAS# 15
DDR_A_WE# 15
DDR_B_D[0 63]16
DDR_B_BS0 16
DDR_B_BS1 16
DDR_B_BS2 16
DDR_B_CAS# 16
DDR_B_RAS# 16
DDR_B_WE# 16
DDR_B_DM[0 7] 16
DDR_B_DQS[0 7] 16
DDR_B_DQS#[0 7] 16
DDR_B_MA[0 14] 16
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Cantiga(2/6)-DDR2 A/B CH
Custom
10 53Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
DDR SYSTEM MEMORY B
U2E
CANTIGA ES_FCBGA1329
SB_DQ_0
AK47
SB_DQ_1
AH46
SB_DQ_10
BA48
SB_DQ_11
AY48
SB_DQ_12
AT47
SB_DQ_13
AR47
SB_DQ_14
BA47
SB_DQ_15
BC47
SB_DQ_16
BC46
SB_DQ_17
BC44
SB_DQ_18
BG43
SB_DQ_19
BF43
SB_DQ_2
AP47
SB_DQ_20
BE45
SB_DQ_21
BC41
SB_DQ_22
BF40
SB_DQ_23
BF41
SB_DQ_24
BG38
SB_DQ_25
BF38
SB_DQ_26
BH35
SB_DQ_27
BG35
SB_DQ_28
BH40
SB_DQ_29
BG39
SB_DQ_3
AP46
SB_DQ_30
BG34
SB_DQ_31
BH34
SB_DQ_32
BH14
SB_DQ_33
BG12
SB_DQ_34
BH11
SB_DQ_35
BG8
SB_DQ_36
BH12
SB_DQ_37
BF11
SB_DQ_38
BF8
SB_DQ_39
BG7
SB_DQ_4
AJ46
SB_DQ_40
BC5
SB_DQ_41
BC6
SB_DQ_42
AY3
SB_DQ_43
AY1
SB_DQ_44
BF6
SB_DQ_45
BF5
SB_DQ_46
BA1
SB_DQ_47
BD3
SB_DQ_48
AV2
SB_DQ_49
AU3
SB_DQ_5
AJ48
SB_DQ_50
AR3
SB_DQ_51
AN2
SB_DQ_52
AY2
SB_DQ_53
AV1
SB_DQ_54
AP3
SB_DQ_55
AR1
SB_DQ_56
AL1
SB_DQ_57
AL2
SB_DQ_58
AJ1
SB_DQ_59
AH1
SB_DQ_6
AM48
SB_DQ_60
AM2
SB_DQ_61
AM3
SB_DQ_62
AH3
SB_DQ_63
AJ3
SB_DQ_7
AP48
SB_DQ_8
AU47
SB_DQ_9
AU46
SB_BS_0
BC16
SB_BS_1
BB17
SB_BS_2
BB33
SB_CAS#
BG16
SB_DM_0
AM47
SB_DM_1
AY47
SB_DM_2
BD40
SB_DM_3
BF35
SB_DM_4
BG11
SB_DM_5
BA3
SB_DM_6
AP1
SB_DM_7
AK2
SB_DQS_0
AL47
SB_DQS_1
AV48
SB_DQS_2
BG41
SB_DQS_3
BG37
SB_DQS_4
BH9
SB_DQS_5
BB2
SB_DQS_6
AU1
SB_DQS_7
AN6
SB_DQS#_0
AL46
SB_DQS#_1
AV47
SB_DQS#_2
BH41
SB_DQS#_3
BH37
SB_DQS#_4
BG9
SB_DQS#_5
BC2
SB_DQS#_6
AT2
SB_DQS#_7
AN5
SB_MA_0
AV17
SB_MA_1
BA25
SB_MA_10
BB16
SB_MA_11
AW33
SB_MA_12
AY33
SB_MA_13
BH15
SB_MA_2
BC25
SB_MA_3
AU25
SB_MA_4
AW25
SB_MA_5
BB28
SB_MA_6
AU28
SB_MA_7
AW28
SB_MA_8
AT33
SB_MA_9
BD33
SB_MA_14
AU33
SB_RAS#
AU17
SB_WE#
BF14
DDR SYSTEM MEMORY A
U2D
CANTIGA ES_FCBGA1329
SA_DQ_0
AJ38
SA_DQ_1
AJ41
SA_DQ_10
AU40
SA_DQ_11
AT38
SA_DQ_12
AN41
SA_DQ_13
AN39
SA_DQ_14
AU44
SA_DQ_15
AU42
SA_DQ_16
AV39
SA_DQ_17
AY44
SA_DQ_18
BA40
SA_DQ_19
BD43
SA_DQ_2
AN38
SA_DQ_20
AV41
SA_DQ_21
AY43
SA_DQ_22
BB41
SA_DQ_23
BC40
SA_DQ_24
AY37
SA_DQ_25
BD38
SA_DQ_26
AV37
SA_DQ_27
AT36
SA_DQ_28
AY38
SA_DQ_29
BB38
SA_DQ_3
AM38
SA_DQ_30
AV36
SA_DQ_31
AW36
SA_DQ_32
BD13
SA_DQ_33
AU11
SA_DQ_34
BC11
SA_DQ_35
BA12
SA_DQ_36
AU13
SA_DQ_37
AV13
SA_DQ_38
BD12
SA_DQ_39
BC12
SA_DQ_4
AJ36
SA_DQ_40
BB9
SA_DQ_41
BA9
SA_DQ_42
AU10
SA_DQ_43
AV9
SA_DQ_44
BA11
SA_DQ_45
BD9
SA_DQ_46
AY8
SA_DQ_47
BA6
SA_DQ_48
AV5
SA_DQ_49
AV7
SA_DQ_5
AJ40
SA_DQ_50
AT9
SA_DQ_51
AN8
SA_DQ_52
AU5
SA_DQ_53
AU6
SA_DQ_54
AT5
SA_DQ_55
AN10
SA_DQ_56
AM11
SA_DQ_57
AM5
SA_DQ_58
AJ9
SA_DQ_59
AJ8
SA_DQ_6
AM44
SA_DQ_60
AN12
SA_DQ_61
AM13
SA_DQ_62
AJ11
SA_DQ_63
AJ12
SA_DQ_7
AM42
SA_DQ_8
AN43
SA_DQ_9
AN44
SA_BS_0
BD21
SA_BS_1
BG18
SA_BS_2
AT25
SA_CAS#
BD20
SA_DM_0
AM37
SA_DM_1
AT41
SA_DM_2
AY41
SA_DM_3
AU39
SA_DM_4
BB12
SA_DM_5
AY6
SA_DM_6
AT7
SA_DQS_0
AJ44
SA_DQS_1
AT44
SA_DQS_2
BA43
SA_DQS_3
BC37
SA_DQS_4
AW12
SA_DQS_5
BC8
SA_DQS_6
AU8
SA_DQS_7
AM7
SA_DM_7
AJ5
SA_DQS#_0
AJ43
SA_DQS#_1
AT43
SA_DQS#_2
BA44
SA_DQS#_3
BD37
SA_DQS#_4
AY12
SA_DQS#_5
BD8
SA_DQS#_6
AU9
SA_DQS#_7
AM8
SA_MA_0
BA21
SA_MA_1
BC24
SA_MA_10
BC21
SA_MA_11
BG26
SA_MA_12
BH26
SA_MA_13
BH17
SA_MA_2
BG24
SA_MA_3
BH24
SA_MA_4
BG25
SA_MA_5
BA24
SA_MA_6
BD24
SA_MA_7
BG27
SA_MA_8
BF25
SA_MA_9
AW24
SA_RAS#
BB20
SA_WE#
AY20
SA_MA_14
AY25
www.kythuatvitinh.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG5
PEG_RXN4
PEG_TXN5
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_TXN7
PEG_RXP4
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP14
PEG_RXP12
PEG_RXP3
PEG_RXP2
PEG_RXP0
PEG_RXP13
PEG_RXP15
PEG_RXP10
PEG_RXP8
PEG_RXP1
PEG_RXP9
PEG_RXP11
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXN12
PEG_RXN0
PEG_RXN12
PEG_RXN3
PEG_RXN2
PEG_RXN10
PEG_RXN8
PEG_RXN13
PEG_RXN15
PEG_RXN14
PEG_TXN9
PEG_RXN9
PEG_RXN11
PEG_TXN6
PEG_TXN10
PEG_TXN11
PEG_TXN8
PEG_TXP13
PEG_TXP7
PEG_TXN4
PEG_TXP5
PEG_TXP6
PEG_TXP12
PEG_TXP14
PEG_TXP15
PEG_TXP11
PEG_TXP9
PEG_TXP8
PEG_TXP10
PEG_TXP4
PEG_TXP1
PEG_TXP0
PEG_TXP2
PEG_TXN0
PEG_TXP3
PEG_TXN1
PEG_RXN1
PEG_TXN3
PEG_TXN2
CFG59
CFG69
CFG79
CFG89
CFG99
CFG109
CFG119
CFG129
CFG139
CFG149
CFG159
CFG179
CFG189
CFG169
CFG199
CFG209
PEG_M_TXN3 20
PEG_M_TXN2 20
PEG_M_TXN1 20
PEG_M_TXN0 20
PEG_M_TXP2 20
PEG_M_TXP3 20
PEG_M_TXP1 20
PEG_M_TXP0 20
PEG_RXN3 20
PEG_RXN2 20
PEG_RXN1 20
PEG_RXN0 20
PEG_RXN5 20
PEG_RXN7 20
PEG_RXN6 20
PEG_RXN4 20
PEG_RXN13 20
PEG_RXN15 20
PEG_RXN14 20
PEG_RXN12 20
PEG_RXN9 20
PEG_RXN11 20
PEG_RXN10 20
PEG_RXN8 20
PEG_RXP5 20
PEG_RXP7 20
PEG_RXP6 20
PEG_RXP4 20
PEG_RXP12 20
PEG_RXP3 20
PEG_RXP2 20
PEG_RXP0 20
PEG_RXP8 20
PEG_RXP13 20
PEG_RXP15 20
PEG_RXP14 20
PEG_RXP1 20
PEG_RXP9 20
PEG_RXP11 20
PEG_RXP10 20
PEG_M_TXN7 20
PEG_M_TXN6 20
PEG_M_TXN5 20
PEG_M_TXN4 20
PEG_M_TXN10 20
PEG_M_TXN9 20
PEG_M_TXN8 20
PEG_M_TXN14 20
PEG_M_TXN13 20
PEG_M_TXN12 20
PEG_M_TXN11 20
PEG_M_TXP6 20
PEG_M_TXP5 20
PEG_M_TXP4 20
PEG_M_TXN15 20
PEG_M_TXP10 20
PEG_M_TXP9 20
PEG_M_TXP8 20
PEG_M_TXP7 20
PEG_M_TXP13 20
PEG_M_TXP12 20
PEG_M_TXP11 20
PEG_M_TXP15 20
PEG_M_TXP14 20
+VCC_PEG
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Cantiga(3/6)-VGA/LVDS/TV
Custom
11 53Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
PEGCOMP trace width
and spacing is 20/25 mils.
000 = FSB 1066MHz
CFG[4:3]
Reserved
CFG6
0 = The iTPM Host Interface is enable
1 = The iTPM Host Interface is disable
*
Reserved
CFG10
(Default)11 = Normal Operation
10 = All Z Mode Enabled
00 = Reserved
01 = XOR Mode Enabled
*
0 = Enable
1 = Disable
*
CFG9 (PCIE Graphics
Lane Reversal)
CFG[2:0] FSB Freq
select
Reserved
Reserved
CFG[15:14]
Strap Pin Table
Reserved
CFG[18:17]
(Lane number in Order)
Others = Reserved
011 = FSB 667MHz
010 = FSB 800MHz
*
1 = Reverse Lane
0 = Reverse Lane,15->0, 14->1
1 = Enabled
0 = Normal Operation
0 = Disabled
*
0 = DMI x 2
*
*
*
1 = PCIE/SDVO are operating simu.
0 = Only PCIE or SDVO is operational.
*
1 = Normal Operation,Lane Number in
order
1 = DMI x 4
0 =(TLS)chiper suite with no confidentiality
1 =(TLS)chiper suite with confidentiality
CFG5 (DMI select)
CFG19 (DMI Lane Reversal)
CFG16 (FSB Dynamic ODT)
CFG7
CFG20
CFG11
CFG[13:12] (XOR/ALLZ)
CFG8
(Intel Management
Engine Crypto strap)
(PCIE
Lookback
enable)
(PCIE/SDVO
concurrent)
#PV follow check list ver:1.5
R71
4.02K_0402_1%
12
C1315 0.1U_0402_16V4Z
1 2
R81
2.21K_0402_1%
1 2
C1303 0.1U_0402_16V4Z
1 2
R73
4.02K_0402_1%
@
1 2
R77
2.21K_0402_1%
1 2
C1295 0.1U_0402_16V4Z
1 2
C1293 0.1U_0402_16V4Z
1 2
C1313 0.1U_0402_16V4Z
1 2
C1304 0.1U_0402_16V4Z
1 2
R74
2.21K_0402_1%
@
12
C1296 0.1U_0402_16V4Z
1 2
R72
4.02K_0402_1%
1 2
R82
2.21K_0402_1%
@
1 2
C1292 0.1U_0402_16V4Z
1 2
C1294 0.1U_0402_16V4Z
1 2
C1310 0.1U_0402_16V4Z
1 2
R75
4.02K_0402_1%
@
1 2
C1309 0.1U_0402_16V4Z
1 2
C1298 0.1U_0402_16V4Z
1 2
C1297 0.1U_0402_16V4Z
1 2
C1300 0.1U_0402_16V4Z
1 2
C1314 0.1U_0402_16V4Z
1 2
R148
0_0402_5%
@
1 2
R84
2.21K_0402_1%
@
1 2
C1316 0.1U_0402_16V4Z
1 2
C1305 0.1U_0402_16V4Z
1 2
C1320 0.1U_0402_16V4Z
1 2
C1312 0.1U_0402_16V4Z
1 2
R76
2.21K_0402_1%
@
1 2
C1289 0.1U_0402_16V4Z
1 2
C1319 0.1U_0402_16V4Z
1 2
R85
2.21K_0402_1%
@
1 2
C1306 0.1U_0402_16V4Z
1 2
C1317 0.1U_0402_16V4Z
1 2
C1302 0.1U_0402_16V4Z
1 2
C1299 0.1U_0402_16V4Z
1 2
R83
2.21K_0402_1%
@
1 2
C1307 0.1U_0402_16V4Z
1 2
R79
2.21K_0402_1%
@
1 2
C1291 0.1U_0402_16V4Z
1 2
C1318 0.1U_0402_16V4Z
1 2
R87
2.21K_0402_1%
@
1 2
C1308 0.1U_0402_16V4Z
1 2
R57
49.9_0402_1%
1 2
R78
2.21K_0402_1%
1 2
C1301 0.1U_0402_16V4Z
1 2
R80
2.21K_0402_1%
@
1 2
LVDS
PCI-EXPRESS GRAPHICS
TV VGA
U2C
CANTIGA ES_FCBGA1329
PEG_COMPI
T37
PEG_COMPO
T36
PEG_RX#_0
H44
PEG_RX#_1
J46
PEG_RX#_2
L44
PEG_RX#_3
L40
PEG_RX#_4
N41
PEG_RX#_5
P48
PEG_RX#_6
N44
PEG_RX#_7
T43
PEG_RX#_8
U43
PEG_RX#_9
Y43
PEG_RX#_10
Y48
PEG_RX#_11
Y36
PEG_RX#_12
AA43
PEG_RX#_13
AD37
PEG_RX#_14
AC47
PEG_RX#_15
AD39
PEG_RX_0
H43
PEG_RX_1
J44
PEG_RX_2
L43
PEG_RX_3
L41
PEG_RX_4
N40
PEG_RX_5
P47
PEG_RX_6
N43
PEG_RX_7
T42
PEG_RX_8
U42
PEG_RX_9
Y42
PEG_RX_10
W47
PEG_RX_11
Y37
PEG_RX_12
AA42
PEG_RX_13
AD36
PEG_RX_14
AC48
PEG_RX_15
AD40
PEG_TX#_0
J41
PEG_TX#_10
Y40
PEG_TX#_3
M40
PEG_TX#_4
M42
PEG_TX#_5
R48
PEG_TX#_6
N38
PEG_TX#_7
T40
PEG_TX#_8
U37
PEG_TX#_9
U40
PEG_TX#_1
M46
PEG_TX#_11
AA46
PEG_TX#_12
AA37
PEG_TX#_13
AA40
PEG_TX#_14
AD43
PEG_TX#_15
AC46
PEG_TX#_2
M47
PEG_TX_0
J42
PEG_TX_1
L46
PEG_TX_2
M48
PEG_TX_3
M39
PEG_TX_4
M43
PEG_TX_5
R47
PEG_TX_6
N37
PEG_TX_7
T39
PEG_TX_8
U36
PEG_TX_9
U39
PEG_TX_10
Y39
PEG_TX_11
Y46
PEG_TX_12
AA36
PEG_TX_13
AA39
PEG_TX_14
AD42
PEG_TX_15
AD46
L_CTRL_CLK
M32
L_CTRL_DATA
M33
L_DDC_CLK
K33
L_DDC_DATA
J33
L_VDD_EN
M29
LVDS_IBG
C44
LVDS_VBG
B43
LVDS_VREFH
E37
LVDS_VREFL
E38
LVDSA_CLK#
C41
LVDSA_CLK
C40
LVDSA_DATA#_0
H47
LVDSA_DATA#_1
E46
LVDSA_DATA#_2
G40
LVDSA_DATA_1
D45
LVDSA_DATA_2
F40
LVDSB_CLK#
B37
LVDSB_CLK
A37
LVDSB_DATA#_0
A41
LVDSB_DATA#_1
H38
LVDSB_DATA#_2
G37
LVDSB_DATA_1
G38
LVDSB_DATA_2
F37
L_BKLT_EN
G32
TVA_DAC
F25
TVB_DAC
H25
TVC_DAC
K25
TV_RTN
H24
CRT_BLUE
E28
CRT_DDC_CLK
H32
CRT_DDC_DATA
J32
CRT_GREEN
G28
CRT_HSYNC
J29
CRT_TVO_IREF
E29
CRT_RED
J28
CRT_IRTN
G29
CRT_VSYNC
L29
LVDSA_DATA_0
H48
LVDSB_DATA_0
B42
L_BKLT_CTRL
L32
TV_DCONSEL_0
C31
TV_DCONSEL_1
E32
LVDSA_DATA#_3
A40
LVDSA_DATA_3
B40
LVDSB_DATA#_3
J37
LVDSB_DATA_3
K37
C1290 0.1U_0402_16V4Z
1 2
C1311 0.1U_0402_16V4Z
1 2
R86
2.21K_0402_1%
@
1 2
www.kythuatvitinh.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.05VS_A_SM
+1.05VS_A_SM_CK
+1.05VS_HPLL
+1.05VS_MPLL
+VCCP
+1.05VS_PEGPLL
+VCCP
+VCCP
+V1.05VS_AXF
+VCCP
+1.05VS_DMI
+1.8V
+1.8V_SM_CK
+1.5VS
+1.5VS_TVDAC
+VCC_PEG
+VCCP
+1.5VS_PEG_BG
+1.5VS
+1.05VS_PEGPLL
+VCCP
+VCCP
+VCCP
+3VS
+VCCP_D
+3VS_HV
+VCCP
+3VS
+1.05VS_DMI
+VCC_PEG
+3VS_HV
+1.8V_SM_CK
+V1.05VS_AXF
+1.05VS_MPLL
+1.05VS_HPLL
+1.5VS_TVDAC
+1.05VS_PEGPLL
+1.05VS_HPLL
+1.5VS
+1.5VS_QDAC
+1.5VS_QDAC
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Cantiga(4/6)-PWR
Custom
12 53Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
73mA
2.68mA
852mA
64.8mA
720mA
24mA
139.2mA
50mA
414uA
13.2mA
64.8mA
26mA
321.35mA
118.8mA
124mA
105.3mA
1732mA
456mA
TVA 24.15mA
TVB 39.48mA
TVX 24.15mA
26mA
50mA
58.67mA
48.363mA
157.2mA
50mA
60.31mA
#SI discrete don't use HDA #SI VCCD_QDAC connect to 1.5VS
C80
0.47U_0603_10V7K
1
2
C83
10U_0805_10V4Z
@
1
2
D3
CH751H-40PT_SOD323-2
2 1
C79
1U_0603_10V4Z
1
2
R97
0_0603_5%
1 2
R96
0_0603_5%
@
1 2
C104
1U_0603_10V4Z
1
2
C120
0.1U_0402_16V4Z
1
2
C103
10U_0805_10V4Z
1
2
R105
10_0402_5%
1 2
C93
0.1U_0402_16V4Z
1
2
C96
4.7U_0805_10V4Z
1
2
C119
0.01U_0402_16V7K
1
2
R93
0_0603_5%
1 2
C109
0.1U_0402_16V4Z
1
2
C100
10U_0805_10V4Z
1
2
C84
10U_0805_10V4Z
1
2
C102
1U_0603_10V4Z
1
2
C99
0.1U_0402_16V4Z
1
2
R101
MBK2012121YZF_0805
1 2
C112
0.47U_0603_10V7K
1
2
+
C94
220U_D2_4VM
<BOM Structure>
1
2
C108
10U_0805_10V4Z
1
2
C106
0.1U_0402_16V4Z
1
2
R104
0_0603_5%
1 2
C85
0.1U_0402_16V4Z
1
2
+
C98
220U_D2_4VM
1
2
L1
BLM18PG121SN1D_0603
1 2
C107
0.1U_0402_16V4Z
1
2
R112
100_0603_1%
1 2
C89
0.1U_0402_16V4Z
1
2
R107
0_0402_5%
1 2
C81
4.7U_0805_10V4Z
1
2
R106
0_0402_5%
1 2
C95
10U_0805_10V4Z
1
2
R100
0_0805_5%
1 2
C78
10U_0805_10V4Z
1
2
C110
0.47U_0603_10V7K
1
2
C105
0.1U_0402_16V4Z
1
2
C82
2.2U_0805_16V4Z
1
2
C91
10U_0805_10V4Z
1
2
C90
0.1U_0402_16V4Z
1
2
C92
0.022U_0402_16V7K
1
2
+
C71
220U_D2_4VM
<BOM Structure>
1
2
C72
4.7U_0805_10V4Z
1
2
C101
10U_0805_10V4Z
1
2
C97
1U_0603_10V4Z
1
2
R102
0_0805_5%
1 2
POWER
CRTPLLA PEGA SMTV
D TV/CRT
LVDS
VTTLF
PEG
SM CK
AXF
VTT
DMI
HV
A CK
A LVDS
HDA
U2H
CANTIGA ES_FCBGA1329
VTT
V3
VTT
U3
VTT
V2
VTT
U2
VCCA_PEG_BG
AD48
VCCA_PEG_PLL
AA48
VCCA_CRT_DAC
B27
VCCA_CRT_DAC
A26
VCCA_DPLLA
F47
VCCA_DPLLB
L48
VCCA_HPLL
AD1
VCCA_LVDS
J48
VCCA_MPLL
AE1
VCCA_TV_DAC
B24
VCCA_TV_DAC
A24
VCCD_PEG_PLL
AA47
VTT
U6
VTT
T6
VTT
U5
VTT
T5
VTT
T8
VTT
U7
VTT
T7
VCCD_HPLL
AF1
VTT
U13
VTT
T13
VTT
T12
VTT
U11
VTT
T11
VTT
U10
VTT
T10
VTT
U9
VTT
T9
VTT
U8
VTT
U12
VCCA_SM_CK
AP28
VCCA_SM_CK
AN28
VCCA_DAC_BG
A25
VCCD_TVDAC
M25
VTTLF
A8
VTTLF
L1
VTTLF
AB2
VCC_DMI
AH48
VCC_DMI
AF48
VCC_SM_CK
BF21
VCC_SM_CK
BH20
VCC_SM_CK
BG20
VCC_SM_CK
BF20
VCCD_LVDS
M38
VCCD_QDAC
L28
VCC_AXF
B22
VCC_AXF
B21
VCC_AXF
A21
VCCA_SM
AR20
VCCA_SM
AP20
VCCA_SM
AN20
VCCA_SM
AR17
VCCA_SM
AP17
VCCA_SM
AT16
VCCA_SM
AR16
VCCA_SM
AP16
VCC_TX_LVDS
K47
VSSA_LVDS
J47
VCC_HV
C35
VCC_HV
B35
VCC_PEG
V48
VCCD_LVDS
L37
VCC_PEG
U48
VCC_PEG
V47
VCC_PEG
U47
VCC_PEG
U46
VCCA_SM
AN17
VCCA_SM_CK
AP25
VCCA_SM_CK
AN25
VCCA_SM_CK
AN24
VCCA_SM_CK_NCTF
AM28
VCCA_SM_CK_NCTF
AM26
VCCA_SM_CK_NCTF
AM25
VCCA_SM_CK_NCTF
AL25
VCCA_SM_CK_NCTF
AM24
VCCA_SM_CK_NCTF
AL24
VCCA_SM_CK_NCTF
AM23
VTT
T2
VTT
V1
VTT
U1
VCC_HV
A35
VCC_DMI
AH47
VCC_DMI
AG47
VSSA_DAC_BG
B25
VCCA_SM_CK_NCTF
AL23
VCC_HDA
A32
R98
MBK2012121YZF_0805
1 2
C111
0.47U_0603_10V7K
1
2
R103
0_0603_5%
1 2
R99
0_0805_5%
1 2
R95
0_0805_5%
1 2
www.kythuatvitinh.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCSM_LF2
VCCSM_LF3
VCCSM_LF1
VCCSM_LF6
VCCSM_LF7
VCCSM_LF4
VCCSM_LF5
+VCCP
+VCCP
+1.8V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Cantiga(5/6)-PWR/GND
Custom
13 53Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
3000mA
6326.84mA
Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA
0317 change value
+
C126
330U_D2E_2.5VM_R7
1
2
C125
0.1U_0402_16V4Z
1
2
POWER
VCC NCTF
VCC CORE
U2F
CANTIGA ES_FCBGA1329
VCC_NCTF
AM32
VCC_NCTF
AC30
VCC_NCTF
AJ29
VCC_NCTF
AK25
VCC_NCTF
AA32
VCC_NCTF
Y32
VCC_NCTF
W32
VCC_NCTF
U32
VCC_NCTF
AM30
VCC_NCTF
AL30
VCC_NCTF
AK30
VCC_NCTF
AG30
VCC_NCTF
AF30
VCC_NCTF
AE30
VCC_NCTF
AL32
VCC_NCTF
W30
VCC_NCTF
V30
VCC_NCTF
AK32
VCC_NCTF
AH29
VCC_NCTF
AG29
VCC_NCTF
AE29
VCC_NCTF
AL28
VCC_NCTF
AK28
VCC_NCTF
AL26
VCC_NCTF
AK26
VCC_NCTF
AJ32
VCC_NCTF
AK24
VCC_NCTF
AH32
VCC_NCTF
AG32
VCC_NCTF
AE32
VCC_NCTF
AC32
VCC_NCTF
AC29
VCC_NCTF
AA29
VCC_NCTF
Y29
VCC_NCTF
W29
VCC_NCTF
V29
VCC_NCTF
U30
VCC_NCTF
AL29
VCC_NCTF
AK29
VCC_NCTF
AH30
VCC_NCTF
AB30
VCC_NCTF
AA30
VCC_NCTF
Y30
VCC
AG34
VCC
AC34
VCC
AB34
VCC
AA34
VCC
Y34
VCC
V34
VCC
U34
VCC
AM33
VCC
AK33
VCC
AJ33
VCC
AG33
VCC
AF33
VCC
AE33
VCC
AC33
VCC
AA33
VCC
Y33
VCC
W33
VCC
V33
VCC
U33
VCC
AH28
VCC
AF28
VCC
AC28
VCC
AA28
VCC
AJ26
VCC
AG26
VCC
AE26
VCC
AC26
VCC
AH25
VCC
AG25
VCC
AF25
VCC
AG24
VCC
AJ23
VCC
AH23
VCC
AF23
VCC
T32
VCC_NCTF
AK23
C143 0.47U_0402_6.3V6K
1
2
C133
0.22U_0402_10V4Z
1
2
T43PAD
@
C145 1U_0603_10V4Z
1
2
+
C131
220U_D2_4VM
1
2
C132
0.22U_0402_10V4Z
1
2
C123
0.01U_0402_16V7K
1
2
C140 0.1U_0402_16V4Z
1
2
C124
10U_0805_10V4Z
1
2
C141 0.22U_0603_10V7K
1
2
C122
10U_0805_10V4Z
1
2
C144 1U_0603_10V4Z
1
2
C142 0.22U_0603_10V7K
1
2
C130
10U_0805_10V4Z
1
2
T42PAD
@
C139 0.1U_0402_16V4Z
1
2
POWER
VCC SMVCC GFX
VCC GFX NCTF
VCC SM LF
U2G
CANTIGA ES_FCBGA1329
VCC_SM
AY32
VCC_SM
BF31
VCC_SM
AW29
VCC_SM
BD32
VCC_SM
BC32
VCC_SM
BB32
VCC_SM
BA32
VCC_SM
AW32
VCC_SM
AV32
VCC_SM
AU32
VCC_SM
AT32
VCC_SM
AR32
VCC_SM
AP32
VCC_SM
AN32
VCC_SM
BH31
VCC_SM
BG31
VCC_SM
AN33
VCC_SM
BG30
VCC_SM
BH29
VCC_SM
BG29
VCC_SM
BF29
VCC_SM
BD29
VCC_SM
BC29
VCC_SM
BB29
VCC_SM
BA29
VCC_SM
AY29
VCC_SM
BH32
VCC_SM
AV29
VCC_SM
AU29
VCC_SM
AT29
VCC_SM
AR29
VCC_AXG_NCTF
V23
VCC_AXG_NCTF
AM21
VCC_AXG_NCTF
AL21
VCC_AXG_NCTF
AK21
VCC_AXG_NCTF
W21
VCC_AXG_NCTF
V21
VCC_AXG_NCTF
U21
VCC_AXG_NCTF
AM20
VCC_AXG_NCTF
AK20
VCC_AXG_NCTF
W20
VCC_AXG_NCTF
V28
VCC_AXG_NCTF
U20
VCC_AXG_NCTF
AM19
VCC_AXG_NCTF
AL19
VCC_AXG_NCTF
AK19
VCC_AXG_NCTF
AJ19
VCC_AXG_NCTF
AH19
VCC_AXG_NCTF
AG19
VCC_AXG_NCTF
AF19
VCC_AXG_NCTF
AE19
VCC_AXG_NCTF
AB19
VCC_AXG_NCTF
W26
VCC_AXG_NCTF
AA19
VCC_AXG_NCTF
Y19
VCC_AXG_NCTF
W19
VCC_AXG_NCTF
V19
VCC_AXG_NCTF
U19
VCC_AXG_NCTF
AM17
VCC_AXG_NCTF
AK17
VCC_AXG_NCTF
AH17
VCC_AXG_NCTF
AG17
VCC_AXG_NCTF
AF17
VCC_AXG_NCTF
V26
VCC_AXG_NCTF
AE17
VCC_AXG_NCTF
AC17
VCC_AXG_NCTF
AB17
VCC_AXG_NCTF
Y17
VCC_AXG_NCTF
W17
VCC_AXG_NCTF
V17
VCC_AXG_NCTF
AM16
VCC_AXG_NCTF
AL16
VCC_AXG_NCTF
AK16
VCC_AXG_NCTF
AJ16
VCC_AXG_NCTF
W25
VCC_AXG_NCTF
AH16
VCC_AXG_NCTF
AG16
VCC_AXG_NCTF
AF16
VCC_AXG_NCTF
AE16
VCC_AXG_NCTF
AC16
VCC_AXG_NCTF
AB16
VCC_AXG_NCTF
AA16
VCC_AXG_NCTF
V25
VCC_AXG_NCTF
W24
VCC_AXG_NCTF
V24
VCC_AXG_NCTF
W23
VCC_SM
AP29
VCC_SM
BG32
VCC_SM
BF32
VCC_AXG_NCTF
W28
VCC_SM
AP33
VCC_AXG
Y26
VCC_AXG
AE25
VCC_AXG
AB25
VCC_AXG
AA25
VCC_AXG
AE24
VCC_AXG
AC24
VCC_AXG
AA24
VCC_AXG
Y24
VCC_AXG
AE23
VCC_AXG
AC23
VCC_AXG
AB23
VCC_AXG
AA23
VCC_AXG
AJ21
VCC_AXG
AG21
VCC_AXG
AE21
VCC_AXG
AC21
VCC_AXG
AA21
VCC_AXG
Y21
VCC_AXG
AH20
VCC_AXG
AF20
VCC_AXG
AE20
VCC_AXG
AC20
VCC_AXG
AB20
VCC_AXG
AA20
VCC_AXG
T17
VCC_AXG
AM15
VCC_AXG
AL15
VCC_AXG
AJ15
VCC_AXG
AH15
VCC_AXG
AF15
VCC_AXG
AB15
VCC_SM_LF
AV44
VCC_SM_LF
BA37
VCC_SM_LF
AM40
VCC_SM_LF
AV21
VCC_SM_LF
AY5
VCC_SM_LF
AM10
VCC_SM_LF
BB13
VCC_AXG
T16
VCC_AXG
AG15
VCC_AXG
AA15
VCC_AXG
Y15
VCC_AXG
V15
VCC_AXG
U15
VCC_AXG
AN14
VCC_AXG
AM14
VCC_AXG
U14
VCC_AXG
T14
VCC_AXG_SENSE
AJ14
VSS_AXG_SENSE
AH14
VCC_AXG_NCTF
Y16
VCC_AXG_NCTF
W16
VCC_AXG_NCTF
V16
VCC_AXG_NCTF
U16
VCC_SM/NC
BA36
VCC_SM/NC
BB24
VCC_SM/NC
BD16
VCC_SM/NC
BB21
VCC_SM/NC
AW16
VCC_SM/NC
AW13
VCC_SM/NC
AT13
VCC_AXG
AE15
www.kythuatvitinh.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Cantiga(6/6)-PWR/GND
Custom
14 53Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
VSS
U2I
CANTIGA ES_FCBGA1329
VSS
AU48
VSS
A23
VSS
AR48
VSS
AL48
VSS
BB47
VSS
AW47
VSS
AN47
VSS
AJ47
VSS
AF47
VSS
AD47
VSS
AB47
VSS
Y47
VSS
T47
VSS
N47
VSS
L47
VSS
G47
VSS
BD46
VSS
BA46
VSS
AV46
VSS
AR46
VSS
AM46
VSS
V46
VSS
R46
VSS
P46
VSS
H46
VSS
F46
VSS
BF44
VSS
AH44
VSS
AD44
VSS
AA44
VSS
Y44
VSS
U44
VSS
T44
VSS
M44
VSS
F44
VSS
BC43
VSS
AV43
VSS
AU43
VSS
AM43
VSS
J43
VSS
C43
VSS
BG42
VSS
AY42
VSS
AT42
VSS
AN42
VSS
AJ42
VSS
AE42
VSS
N42
VSS
L42
VSS
BD41
VSS
AU41
VSS
AM41
VSS
AH41
VSS
AD41
VSS
AA41
VSS
Y41
VSS
U41
VSS
T41
VSS
M41
VSS
G41
VSS
B41
VSS
BG40
VSS
BB40
VSS
AV40
VSS
AN40
VSS
H40
VSS
E40
VSS
AT39
VSS
AM39
VSS
AJ39
VSS
AE39
VSS
N39
VSS
L39
VSS
B39
VSS
BH38
VSS
BC38
VSS
BA38
VSS
AU38
VSS
AH38
VSS
AD38
VSS
AA38
VSS
Y38
VSS
U38
VSS
T38
VSS
J38
VSS
F38
VSS
C38
VSS
BD36
VSS
AM36
VSS
AE36
VSS
P36
VSS
L36
VSS
J36
VSS
F36
VSS
B36
VSS
AH35
VSS
AA35
VSS
Y35
VSS
U35
VSS
T35
VSS
BF34
VSS
AM34
VSS
AJ34
VSS
AF34
VSS
AE34
VSS
W34
VSS
B34
VSS
A34
VSS
BG33
VSS
BC33
VSS
BA33
VSS
AV33
VSS
AR33
VSS
AL33
VSS
AH33
VSS
AB33
VSS
P33
VSS
L33
VSS
H33
VSS
N32
VSS
K32
VSS
F32
VSS
C32
VSS
A31
VSS
AN29
VSS
T29
VSS
N29
VSS
K29
VSS
H29
VSS
F29
VSS
A29
VSS
BG28
VSS
BD28
VSS
BA28
VSS
AV28
VSS
AT28
VSS
AR28
VSS
AJ28
VSS
AG28
VSS
AE28
VSS
AB28
VSS
Y28
VSS
P28
VSS
K28
VSS
H28
VSS
F28
VSS
C28
VSS
BF26
VSS
AH26
VSS
AF26
VSS
AB26
VSS
AA26
VSS
C26
VSS
B26
VSS
BH25
VSS
BD25
VSS
BB25
VSS
AV25
VSS
AR25
VSS
AJ25
VSS
AC25
VSS
Y25
VSS
N25
VSS
L25
VSS
J25
VSS
G25
VSS
E25
VSS
BF24
VSS
BF37
VSS
BB37
VSS
AW37
VSS
AT37
VSS
AN37
VSS
AJ37
VSS
H37
VSS
C37
VSS
BG36
VSS
AU36
VSS
AT24
VSS
AH24
VSS
AB24
VSS
L24
VSS
AY46
VSS
G24
VSS
E24
VSS
AG23
VSS
B23
VSS
AY24
VSS
AJ24
VSS
AF24
VSS
R24
VSS
K24
VSS
J24
VSS
F24
VSS
BH23
VSS
Y23
VSS
AK15
VSS
AD12
VSS
AJ6
VSS
VSS NCTF
VSS SCB
NC
U2J
CANTIGA ES_FCBGA1329
VSS
BG21
VSS
AW21
VSS
AU21
VSS
AP21
VSS
AN21
VSS
AH21
VSS
AF21
VSS
AB21
VSS
R21
VSS
M21
VSS
J21
VSS
G21
VSS
BC20
VSS
BA20
VSS
AW20
VSS
AT20
VSS
AJ20
VSS
AG20
VSS
Y20
VSS
N20
VSS
K20
VSS
F20
VSS
C20
VSS
A20
VSS
BG19
VSS
A18
VSS
BG17
VSS
BC17
VSS
AW17
VSS
AT17
VSS
R17
VSS
M17
VSS
H17
VSS
C17
VSS
BA16
VSS
AU16
VSS
AN16
VSS
N16
VSS
K16
VSS
G16
VSS
E16
VSS
BG15
VSS
W15
VSS
A15
VSS
BG14
VSS
AA14
VSS
C14
VSS
BG13
VSS
BC13
VSS
BA13
VSS
AN13
VSS
AJ13
VSS
AE13
VSS
N13
VSS
L13
VSS
G13
VSS
E13
VSS
BF12
VSS
AV12
VSS
AT12
VSS
AM12
VSS
AA12
VSS
J12
VSS
A12
VSS
BD11
VSS
BB11
VSS
AY11
VSS
AN11
VSS
AH11
VSS
Y11
VSS
N11
VSS
G11
VSS
C11
VSS
BG10
VSS
AV10
VSS
AT10
VSS
AJ10
VSS
AE10
VSS
AA10
VSS
BH8
VSS
B9
VSS
G9
VSS
AD9
VSS
AM9
VSS
AN9
VSS
BC9
VSS
M10
VSS
BF9
VSS
AH8
VSS
Y8
VSS
L8
VSS
E8
VSS
B8
VSS
AY7
VSS
AU7
VSS
AN7
VSS
AJ7
VSS
AE7
VSS
AA7
VSS
N7
VSS
J7
VSS
BG6
VSS
BD6
VSS
AV6
VSS
AT6
VSS
AC15
VSS
AM6
VSS
M6
VSS
C6
VSS
BA5
VSS
AH5
VSS
AD5
VSS
Y5
VSS
L5
VSS
J5
VSS
H5
VSS
F5
VSS
BE4
VSS
BC3
VSS
AV3
VSS
AL3
VSS_NCTF
AF32
VSS_NCTF
AB32
VSS_NCTF
V32
VSS_NCTF
AJ30
VSS_NCTF
AM29
VSS_NCTF
AF29
VSS_NCTF
AB29
VSS_NCTF
U26
VSS_NCTF
U23
VSS_NCTF
AL20
VSS_NCTF
V20
VSS_NCTF
AC19
VSS_NCTF
AL17
VSS_NCTF
AJ17
VSS_NCTF
AA17
VSS_NCTF
U17
VSS_SCB
BH48
VSS_SCB
BH1
VSS_SCB
A48
VSS_SCB
C1
VSS_SCB
A3
NC
E1
NC
D2
NC
C3
NC
B4
NC
A5
NC
A6
NC
A43
NC
A44
NC
B45
NC
C46
NC
D47
NC
B47
NC
A46
NC
F48
NC
E48
NC
C48
NC
B48
VSS
R3
VSS
P3
VSS
BA2
VSS
AR2
VSS
AU2
VSS
AP2
VSS
F3
VSS
AW2
VSS
AE2
VSS
AF2
VSS
AH2
VSS
AJ2
VSS
AD2
VSS
AC2
VSS
Y2
VSS
M2
VSS
K2
VSS
AM1
VSS
AA1
VSS
P1
VSS
H1
VSS
BB8
VSS
AV8
VSS
AT8
VSS
U24
VSS
U28
VSS
U25
VSS
U29
VSS
L12
www.kythuatvitinh.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
V_DDR_MCH_REF
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR#0
M_CLK_DDR#1
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
CLK_SMBCLK
DDR_A_MA1
DDR_A_MA10
DDR_A_MA3
DDR_A_MA9 DDR_A_MA7
DDR_A_MA12
DDR_A_MA5
DDR_A_WE#
DDR_A_D8
DDR_A_D17
DDR_A_D16
DDR_A_D27
DDR_A_D26
DDR_A_DQS1
DDR_A_DQS0
DDR_A_DQS2
DDR_A_DM3
DDR_A_DM1
DDR_A_DM2
DDR_A_DM0
DDR_A_DQS4
DDR_A_DQS6
DDR_A_DQS7
CLK_SMBDATA
DDR_CKE0_DIMMA
DDR_A_MA8
DDR_CS1_DIMMA#
DDR_A_MA11
DDR_A_MA2
DDR_A_MA0
DDR_A_MA4
DDR_A_MA6
DDR_A_CAS#
DDR_A_BS1
DDR_A_RAS#
DDR_A_D20
DDR_A_D21
DDR_A_D53
DDR_A_D52
DDR_A_D55
DDR_A_DM6
DDR_A_DM4
DDR_A_DM5
DDR_A_DM7
DDR_A_MA13
DDR_A_DQS5
DDR_A_BS0
DDR_A_BS2
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
M_ODT1
M_ODT0
DDR_A_D51DDR_A_D54
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D42
DDR_A_D39
DDR_A_D22
DDR_A_D23
DDR_A_D12
DDR_A_D13
DDR_A_D10 DDR_A_D14
DDR_A_D11 DDR_A_D15
DDR_A_D9
DDR_A_D0
DDR_A_D1
DDR_A_D3
DDR_A_D2
DDR_A_D4
DDR_A_D6
DDR_A_D5
DDR_A_D7
DDR_A_D18
DDR_A_D19
DDR_A_D31
DDR_A_D30
DDR_A_D28DDR_A_D29
DDR_A_D25DDR_A_D24
DDR_A_D36
DDR_A_D38
DDR_A_D37
DDR_A_D35
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D44
DDR_A_D45
DDR_A_D40
DDR_A_D41
DDR_A_D46
DDR_A_D60
DDR_A_D61 DDR_A_D57
DDR_A_D56
DDR_A_D58
DDR_A_D63
DDR_A_D59
DDR_A_D62
DDR_A_MA14
DDR_CKE1_DIMMA
DDR_A_MA4
DDR_A_BS2
DDR_A_MA6
DDR_CKE0_DIMMA
DDR_A_MA2
DDR_A_CAS#
DDR_A_BS0
DDR_A_MA10
M_ODT1
DDR_CS1_DIMMA#
DDR_A_WE#
M_ODT0
DDR_A_MA13
DDR_A_MA14
DDR_A_D47 DDR_A_D43
DDR_A_MA9
DDR_A_MA12
DDR_A_MA1
DDR_A_MA3
DDR_A_MA8
DDR_A_MA5
DDR_A_MA0
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_BS1
DDR_A_MA11
DDR_A_MA7
DDR_A_D[0 63]10
DDR_CKE0_DIMMA9
DDR_A_BS210
DDR_A_BS010
DDR_A_WE#10
DDR_A_CAS#10
M_ODT19
DDR_CS1_DIMMA#9
M_CLK_DDR0 9
M_CLK_DDR#0 9
DDR_CKE1_DIMMA 9
DDR_A_BS1 10
DDR_A_RAS# 10
DDR_CS0_DIMMA# 9
M_CLK_DDR#1 9
M_ODT0 9
V_DDR_MCH_REF 9,16
M_CLK_DDR1 9
PM_EXTTS#0 9
CLK_SMBDATA16,17
CLK_SMBCLK16,17
DDR_A_DQS#[0 7]10
DDR_A_DM[0 7]10
DDR_A_DQS[0 7]10
DDR_A_MA[0 14]10
+1.8V
+3VS
+1.8V
+1.8V
+0.9V
+0.9V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
DDRII-SODIMM SLOT1
Custom
15 53Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"
Layout Note:
Place near
JP3
Layout Note:
Place one cap close to every 2
pullup
resistors terminated to +0.9VS
SO-DIMM A
510
RP556_0404_4P2R_5%
1 4
2 3
C162
0.1U_0402_16V4Z
1
2
C155
2.2U_0805_16V4Z
1
2
RP4 56_0404_4P2R_5%
14
23
RP13 56_0404_4P2R_5%
14
23
C160
0.1U_0402_16V4Z
1
2
C149
0.1U_0402_16V4Z
1
2
R115
10K_0402_5%
12
C168
0.1U_0402_16V4Z
1
2
RP756_0404_4P2R_5%
1 4
2 3
C166
0.1U_0402_16V4Z
1
2
RP6 56_0404_4P2R_5%
14
23
R116
10K_0402_5%
12
C172
0.1U_0402_16V4Z
1
2
C161
0.1U_0402_16V4Z
1
2
C170
0.1U_0402_16V4Z
1
2
C158
0.1U_0402_16V4Z
1
2
RP2 56_0404_4P2R_5%
14
23
C151
0.1U_0402_16V4Z
1
2
C163
0.1U_0402_16V4Z
1
2
RP8 56_0404_4P2R_5%
14
23
C171
2.2U_0603_6.3V4Z
1
2
C167
0.1U_0402_16V4Z
1
2
C165
0.1U_0402_16V4Z
1
2
C159
0.1U_0402_16V4Z
1
2
C154
2.2U_0805_16V4Z
1
2
C146
2.2U_0805_16V4Z
1
2
+
C150
330U_D2E_2.5VM_R7
1
2
C164
0.1U_0402_16V4Z
1
2
RP156_0404_4P2R_5%
1 4
2 3
C157
0.1U_0402_16V4Z
1
2
RP12 56_0404_4P2R_5%
14
23
RP10 56_0404_4P2R_5%
14
23
RP956_0404_4P2R_5%
1 4
2 3
C156
0.1U_0402_16V4Z
1
2
JDIMM1
FOX_ASOA426-M4R-TR
VREF
1
VSS
3
DQ0
5
DQ1
7
VSS
9
DQS0#
11
DQS0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
VSS
41
DQ16
43
DQ17
45
VSS
47
DQS2#
49
DQS2
51
VSS
53
DQ18
55
DQ19
57
VSS
59
DQ24
61
DQ25
63
VSS
65
DM3
67
NC
69
VSS
71
DQ26
73
DQ27
75
VSS
77
CKE0
79
VDD
81
NC
83
BA2
85
VDD
87
A12
89
A9
91
A8
93
VDD
95
A5
97
A3
99
A1
101
VDD
103
A10/AP
105
BA0
107
WE#
109
VDD
111
CAS#
113
NC/S1#
115
VDD
117
NC/ODT1
119
VSS
121
DQ32
123
DQ33
125
VSS
127
DQS4#
129
DQS4
131
VSS
133
DQ34
135
DQ35
137
VSS
139
DQ40
141
DQ41
143
VSS
2
DQ4
4
DQ5
6
VSS
8
DM0
10
VSS
12
DQ6
14
DQ7
16
VSS
18
DQ12
20
DQ13
22
VSS
24
DM1
26
VSS
28
CK0
30
CK0#
32
VSS
34
DQ14
36
DQ15
38
VSS
40
VSS
42
DQ20
44
DQ21
46
VSS
48
NC
50
DM2
52
VSS
54
DQ22
56
DQ23
58
VSS
60
DQ28
62
DQ29
64
VSS
66
DQS3#
68
DQS3
70
VSS
72
DQ30
74
DQ31
76
VSS
78
NC/CKE1
80
VDD
82
NC/A15
84
NC/A14
86
VDD
88
A11
90
A7
92
A6
94
VDD
96
A4
98
A2
100
A0
102
VDD
104
BA1
106
RAS#
108
S0#
110
VDD
112
ODT0
114
NC/A13
116
VDD
118
NC
120
VSS
122
DQ36
124
DQ37
126
VSS
128
DM4
130
VSS
132
DQ38
134
DQ39
136
VSS
138
DQ44
140
DQ45
142
VSS
144
VSS
145
DM5
147
VSS
149
DQ42
151
DQ43
153
VSS
155
DQ48
157
DQ49
159
VSS
161
NC,TEST
163
VSS
165
DQS6#
167
DQS6
169
VSS
171
DQ50
173
DQ51
175
VSS
177
DQ56
179
DQ57
181
VSS
183
DM7
185
VSS
187
DQ58
189
DQ59
191
VSS
193
SDA
195
SCL
197
VDDSPD
199
DQS5#
146
DQS5
148
VSS
150
DQ46
152
DQ47
154
VSS
156
DQ52
158
DQ53
160
VSS
162
CK1
164
CK1#
166
VSS
168
DM6
170
VSS
172
DQ54
174
DQ55
176
VSS
178
DQ60
180
DQ61
182
VSS
184
DQS7#
186
DQS7
188
VSS
190
DQ62
192
DQ63
194
VSS
196
SAO
198
SA1
200
RP1156_0404_4P2R_5%
1 4
2 3
C169
0.1U_0402_16V4Z
1
2
RP356_0404_4P2R_5%
1 4
2 3
C153
2.2U_0805_16V4Z
1
2
R117 56_0402_5%
1 2
C152
2.2U_0805_16V4Z
1
2
C148
0.1U_0402_16V4Z
1
2
C147
2.2U_0805_16V4Z
1
2
www.kythuatvitinh.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_B_DQS#4
DDR_B_D14
DDR_B_DQS4
DDR_B_BS2
DDR_B_MA2
DDR_CKE2_DIMMB
DDR_B_D8
DDR_B_DM3
DDR_B_D54
DDR_B_D45
DDR_B_MA3
DDR_B_D32
DDR_B_D40
DDR_B_D6
DDR_B_MA7
DDR_B_D13
DDR_B_D1
DDR_B_DQS#0
DDR_CS3_DIMMB#
M_ODT3
DDR_B_MA11
DDR_B_D47
DDR_B_WE#
DDR_B_D7
DDR_B_D11
DDR_B_MA10
DDR_B_D48
DDR_B_D34
DDR_B_D41
DDR_B_DQS5
M_ODT2
DDR_B_DQS2
DDR_B_DQS#7
DDR_B_MA6
DDR_B_D9
DDR_B_D44
DDR_B_D62
DDR_B_DM7
DDR_B_BS0
DDR_B_MA5
DDR_B_D56
DDR_B_DQS#3
DDR_B_D10
DDR_B_D12
DDR_B_D19
DDR_B_D55
DDR_B_D37
DDR_B_DQS7
DDR_B_D42
DDR_B_D36
DDR_CKE3_DIMMB
DDR_B_DQS0
DDR_B_D46
DDR_B_MA1
DDR_B_MA8
DDR_B_DQS#2
DDR_B_DQS#5
DDR_B_MA12
DDR_B_DQS3
DDR_B_RAS#
DDR_B_MA4
DDR_B_DM5
DDR_B_D35
DDR_B_D43
DDR_B_D2
DDR_B_MA13
DDR_B_D33
DDR_B_DQS1
DDR_B_BS1
DDR_B_D59
DDR_B_DQS#6
DDR_B_D49
DDR_B_DM4
DDR_B_DQS6
DDR_B_DQS#1
DDR_B_D51
DDR_B_MA9
DDR_B_MA0
DDR_B_D3
DDR_B_D15
DDR_B_CAS#
DDR_B_D18
DDR_CS2_DIMMB#
DDR_B_DM0
DDR_B_DM1
DDR_B_D0
DDR_B_DM6
DDR_B_D60
DDR_B_D50
DDR_B_DM2
DDR_B_D53
DDR_B_D52
DDR_B_D38
DDR_B_D39
DDR_B_D31
DDR_B_D30
DDR_B_D27
DDR_B_D28
DDR_B_D20
DDR_B_D16DDR_B_D21
DDR_B_D17
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_D5
DDR_B_D4
DDR_B_D23
DDR_B_D22
DDR_B_D29
DDR_B_D24DDR_B_D25
DDR_B_D26
DDR_B_D61 DDR_B_D57
DDR_B_D58
DDR_B_D63
V_DDR_MCH_REF
DDR_B_MA8
DDR_B_MA0
DDR_B_BS1
DDR_B_MA14
DDR_CKE3_DIMMB
CLK_SMBCLK
CLK_SMBDATA
DDR_B_MA11
DDR_B_MA14
DDR_CS3_DIMMB#
M_ODT3
DDR_B_BS0
DDR_B_WE#
DDR_B_MA10
DDR_B_CAS#
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_CKE2_DIMMB
M_ODT2
DDR_B_MA13
DDR_CS2_DIMMB#
DDR_B_RAS#
DDR_B_MA2
DDR_B_MA4
DDR_B_MA6
DDR_B_MA7
DDR_CKE3_DIMMB 9
DDR_CS2_DIMMB# 9
V_DDR_MCH_REF 9,15
DDR_B_WE#10
DDR_B_BS1 10
DDR_B_RAS# 10
DDR_B_CAS#10
M_ODT39
DDR_CKE2_DIMMB9
DDR_CS3_DIMMB#9
DDR_B_BS210
DDR_B_BS010
M_ODT2 9
PM_EXTTS#1 9
M_CLK_DDR2 9
M_CLK_DDR#2 9
M_CLK_DDR3 9
M_CLK_DDR#3 9
CLK_SMBDATA15,17
CLK_SMBCLK15,17
DDR_B_MA[0 14]10
DDR_B_D[0 63]10
DDR_B_DQS#[0 7]10
DDR_B_DM[0 7]10
DDR_B_DQS[0 7]10
+1.8V
+3VS
+3VS
+1.8V
+1.8V
+0.9V
+0.9V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
DDRII-SODIMM SLOT2
16 53Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
SO-DIMM B
Layout Note:
Place near
JP10
Layout Note:
Place one cap close to every 2
pullup
resistors terminated to +0.9VS
Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"
0612 add
510
5
RP1656_0404_4P2R_5%
1 4
2 3
C188
0.1U_0402_16V4Z
1
2
C191
0.1U_0402_16V4Z
1
2
JDIMM2
FOX_AS0A426-N8RN-7F
VREF
1
VSS
3
DQ0
5
DQ1
7
VSS
9
DQS0#
11
DQS0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
VSS
41
DQ16
43
DQ17
45
VSS
47
DQS2#
49
DQS2
51
VSS
53
DQ18
55
DQ19
57
VSS
59
DQ24
61
DQ25
63
VSS
65
DM3
67
NC
69
VSS
71
DQ26
73
DQ27
75
VSS
77
CKE0
79
VDD
81
NC
83
BA2
85
VDD
87
A12
89
A9
91
A8
93
VDD
95
A5
97
A3
99
A1
101
VDD
103
A10/AP
105
BA0
107
WE#
109
VDD
111
CAS#
113
NC/S1#
115
VDD
117
NC/ODT1
119
VSS
121
DQ32
123
DQ33
125
VSS
127
DQS4#
129
DQS4
131
VSS
133
DQ34
135
DQ35
137
VSS
139
DQ40
141
DQ41
143
VSS
145
DM5
147
VSS
149
DQ42
151
DQ43
153
VSS
155
DQ48
157
DQ49
159
VSS
161
NC,TEST
163
VSS
165
DQS6#
167
DQS6
169
VSS
171
DQ50
173
DQ51
175
VSS
177
DQ56
179
DQ57
181
VSS
183
DM7
185
VSS
187
DQ58
189
DQ59
191
VSS
193
SDA
195
SCL
197
VDDSPD
199
VSS
2
DQ4
4
DQ5
6
VSS
8
DM0
10
VSS
12
DQ6
14
DQ7
16
VSS
18
DQ12
20
DQ13
22
VSS
24
DM1
26
VSS
28
CK0
30
CK0#
32
VSS
34
DQ14
36
DQ15
38
VSS
40
VSS
42
DQ20
44
DQ21
46
VSS
48
NC
50
DM2
52
VSS
54
DQ22
56
DQ23
58
VSS
60
DQ28
62
DQ29
64
VSS
66
DQS3#
68
DQS3
70
VSS
72
DQ30
74
DQ31
76
VSS
78
NC/CKE1
80
VDD
82
NC/A15
84
NC/A14
86
VDD
88
A11
90
A7
92
A6
94
VDD
96
A4
98
A2
100
A0
102
VDD
104
BA1
106
RAS#
108
S0#
110
VDD
112
ODT0
114
NC/A13
116
VDD
118
NC
120
VSS
122
DQ36
124
DQ37
126
VSS
128
DM4
130
VSS
132
DQ38
134
DQ39
136
VSS
138
DQ44
140
DQ45
142
VSS
144
DQS5#
146
DQS5
148
VSS
150
DQ46
152
DQ47
154
VSS
156
DQ52
158
DQ53
160
VSS
162
CK1
164
CK1#
166
VSS
168
DM6
170
VSS
172
DQ54
174
DQ55
176
VSS
178
DQ60
180
DQ61
182
VSS
184
DQS7#
186
DQS7
188
VSS
190
DQ62
192
DQ63
194
VSS
196
SA0
198
SA1
200
RP26 56_0404_4P2R_5%
14
23
C193
0.1U_0402_16V4Z
1
2
RP2056_0404_4P2R_5%
1 4
2 3
C176
2.2U_0805_16V4Z
1
2
R120 56_0402_5%
1 2
C185
0.1U_0402_16V4Z
1
2
C182
0.1U_0402_16V4Z
1
2
R118
10K_0402_5%
1 2
C178
0.1U_0402_16V4Z
1
2
C181
0.1U_0402_16V4Z
1
2
RP19 56_0404_4P2R_5%
14
23
C184
0.1U_0402_16V4Z
1
2
C186
0.1U_0402_16V4Z
1
2
C190
0.1U_0402_16V4Z
1
2
C179
0.1U_0402_16V4Z
1
2
R119
10K_0402_5%
12
C183
2.2U_0805_16V4Z
1
2
C198
0.1U_0402_16V4Z
1
2
C194
0.1U_0402_16V4Z
1
2
RP17 56_0404_4P2R_5%
14
23
C192
0.1U_0402_16V4Z
1
2
RP2456_0404_4P2R_5%
1 4
2 3
C177
2.2U_0805_16V4Z
1
2
RP1456_0404_4P2R_5%
1 4
2 3
C195
0.1U_0402_16V4Z
1
2
RP2256_0404_4P2R_5%
1 4
2 3
C180
0.1U_0402_16V4Z
1
2
C187
0.1U_0402_16V4Z
1
2
RP23 56_0404_4P2R_5%
14
23
RP25 56_0404_4P2R_5%
14
23
RP15 56_0404_4P2R_5%
14
23
C173
2.2U_0805_16V4Z
1
2
C189
0.1U_0402_16V4Z
1
2
C175
2.2U_0805_16V4Z
1
2
C196
0.1U_0402_16V4Z
1
2
C174
2.2U_0805_16V4Z
1
2
RP21 56_0404_4P2R_5%
14
23
RP1856_0404_4P2R_5%
1 4
2 3
C197
2.2U_0603_6.3V4Z
1
2
www.kythuatvitinh.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FSC
FSB
FSA
H_STP_CPU#
H_STP_PCI#
R_CLKREQ#_7
CLK_48M_ICH
CLK_14M_ICH
CLK_PCI_ICH
CLK_PCI_EC
CLK_XTAL_IN
CLK_XTAL_OUT
CLK_SMBCLK
CLK_SMBDATA
ITP_EN PCI_CLK3
ITP_EN
REF1
FSA
R_CKPWRGD
FSB
CLK_XTAL_OUT
CLK_XTAL_IN
FSC
CLK_SMBDATA
CLK_SMBCLK
PCI2_2
27_SEL
PCI_CLK3
R_CLK_PCIE_VGA
R_CLK_PCIE_VGA# SSCDREFCLK#
SSCDREFCLK
R_PCIE_ICH
R_PCIE_ICH#
R_PCIE_SATA
R_PCIE_SATA#
R_CLKREQ#_C
R_CLKREQ#_4
R_CLK_PCIE_LAN#
R_CLK_PCIE_NCARD
R_CLK_PCIE_NCARD#
R_CLK_PCIE_MCARD0#
R_CLK_PCIE_MCARD0
R_CLK_PCIE_LAN
R_CLK_PCIE_MCARD2#
R_CLK_PCIE_MCARD2
R_CLKREQ#_6
R_MCH_3GPLL#
R_MCH_3GPLL
R_CPU_BCLK
R_CPU_BCLK#
R_MCH_BCLK
R_MCH_BCLK#
R_CPU_XDP#
R_CPU_XDP
R_CLKREQ#_10
R_CLK_SRC11
R_CLK_SRC11#
R_CLKREQ#_9
PCI2_1
CPU_BSEL27
MCH_CLKSEL2 9
CPU_BSEL17
MCH_CLKSEL1 9
CPU_BSEL07
MCH_CLKSEL0 9
H_STP_CPU# 27
CLKREQ#_79
ICH_SMBCLK21,27,31,37
ICH_SMBDATA21,27,31,37
CLK_PCI_ICH25
CLK_48M_ICH27
VGATE27,49
CLK_ENABLE#49
CK_PWRGD27
CLK_14M_ICH27
CLK_SMBDATA15,16
CLK_SMBCLK15,16
CLK_DEBUG_PORT_037
CLK_PCI_EC38
27M_CLK 21
27M_SSC 21
CLK_PCIE_ICH 27
CLK_PCIE_ICH# 27
CLK_PCIE_SATA# 26
CLK_PCIE_SATA 26
CLKREQ#_C 27
CLKREQ#_4 31
CLK_PCIE_LAN# 30
CLK_PCIE_LAN 30
CLK_PCIE_NCARD 31
CLK_PCIE_NCARD# 31
CLK_PCIE_MCARD0# 31
CLK_PCIE_MCARD0 31
CLK_PCIE_MCARD2# 31
CLK_PCIE_MCARD2 31
CLKREQ#_6 31
CLK_MCH_3GPLL 9
CLK_MCH_3GPLL# 9CLK_MCH_BCLK#9
CLK_MCH_BCLK9
CLK_CPU_BCLK#6
CLK_CPU_BCLK6
CLK_CPU_XDP# 6
CLK_CPU_XDP 6
CLKREQ#_10 31
H_STP_PCI# 27
CLK_PCIE_VGA#20
CLK_PCIE_VGA20
CLK_SRC11# 32
CLK_SRC11 32
CLKREQ#_9 30
CLK_DEBUG_PORT_131
+VCCP
+VCCP
+VCCP
+3VS_CK505
+1.05VS_CK505
+VCCP
+3VS
+3VS
+3VS +3VS
+3VS
+3VS_CK505
+3VS_CK505
+1.05VS_CK505
+1.05VS_CK505
+1.05VS_CK505
+3VS_CK505
+3VS_CK505
+1.05VS_CK505
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Clock Generator CK505
17 53Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
Place close to U51
CPU
NB
XDP/ITP
Card reader
100
PCI
MHz
266
SRC
MHz
CLKSEL2
33.3
0
FSC
REF
MHz
DOT_96
MHz
USB
MHz
14.318 96.0 48.0
133
1
200
166
333
Reserved
Routing the trace at least 10mil
SB, MINI PCI
1 = ITP/ITP#
PCI_CLK3
0 = SRC8/SRC8#
1 = Enable SRC0 & 27MHz(DIS)
0 = Enable DOT96 & SRC1(UMA)
ITP_EN
Vendor suggests 22pF
VGA
ICH
SATA
New Card
GLAN
3G_PLL
MiniCard_WLAN
No Debug port anymore
MiniCard_WWAN
CPU
MHz
CLKSEL1
FSB
CLKSEL0
FSA
48.0
48.0
48.0
48.0
48.0
48.0
96.0
96.0
96.0
96.0
96.0
96.0
14.318
14.318
14.318
14.318
14.318
14.318
33.3
33.3
33.3
33.3
33.3
33.3
100
100
100
100
100
100
100
400
00
00
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
V
V
VGA
Mini card debug port
24pin debug port
#SI change to 39 ohm
#SI change to 33 ohm
#PV for WWAN noise add 12P
R171
0_0402_5%
1 2
R177 33_0402_5%
1 2
R132 0_0402_5%
1 2
R130 0_0402_5%
1 2
R155 39_0402_1%
1 2
C208
0.1U_0402_16V4Z
1
2
R121
0_0805_5%
1 2
R170 0_0402_5%
1 2
R136 0_0402_5%
1 2
C209
10U_0805_10V4Z
1
2
R150
1K_0402_5%
1 2
R140 0_0402_5%
1 2
R138
0_0402_5%
1 2
C199
10U_0805_10V4Z
1
2
SLG8SP553VTR_QFN72_10x10
U3
VDD_48
19
USB_0/FS_A
20
USB_1/CLKREQ_A#
21
VSS_48
22
VDD_IO
23
SRC_0/DOT_96
24
SRC_0#/DOT_96#
25
VSS_IO
26
VDD_PLL3
27
LCDCLK/27M
28
LCDCLK#/27M_SS
29
VSS_PLL3
30
VDD_PLL3_IO
31
SRC_2
32
SRC_2#
33
VSS_SRC
34
SRC_3
35
SRC_3#
36
VDD_CPU
72
CPU_0
71
CPU_0#
70
VSS_CPU
69
CPU_1
68
CPU_1#
67
VDD_CPU_IO
66
CLKREQ_7#
65
SRC_8/CPU_ITP
64
SRC_8#/CPU_ITP#
63
VDD_SRC_IO
62
SRC_7
61
SRC_7#
60
VSS_SRC
59
CLKREQ_6#
58
SRC_6
57
SRC_6#
56
VDD_SRC
55
PCI_STOP#
54
CPU_STOP#
53
VDD_SRC_IO
52
SRC_10#
51
SRC_10
50
CLKREQ_10#
49
SRC_11
48
SRC_11#
47
CLKREQ_11#
46
SRC_9#
45
SRC_9
44
CLKREQ_9#
43
VSS_SRC
42
CLKREQ_4#
41
SRC_4#
40
SRC_4
39
VDD_SRC_IO
38
CLKREQ_3#
37
CKPWRGD/PD#
1
FS_B/TEST_MODE
2
VSS_REF
3
XTAL_OUT
4
XTAL_IN
5
VDD_REF
6
REF_0/FS_C/TEST_
7
REF_1
8
SDA
9
SCL
10
NC
11
VDD_PCI
12
PCI_1
13
PCI_2
14
PCI_3
15
PCI_4/SEL_LCDCL
16
PCIF_5/ITP_EN
17
VSS_PCI
18
CLRP1
NO SHORT PADS
12
R172 0_0402_5%
1 2
R125 0_0402_5%
1 2
R159 0_0402_5%
1 2
R174
0_0402_5%
@
12
C213
18P_0402_50V8J
1
2
R725 0_0402_5%
1 2
R176 33_0402_5%
1 2
R135 0_0402_5%
1 2
R738 475_0402_1%
1 2
T44 @
R169 39_0402_1%
1 2
R141 0_0402_5%@
1 2
R165
1K_0402_5%
1 2
R179
2.2K_0402_5%
R147 33_0402_1%
1 2
R161 33_0402_1%
1 2
R127 0_0402_5%
1 2
R181
10K_0402_5%
12
R160 0_0402_5%
1 2
R182
10K_0402_5%
@
12
C210
0.1U_0402_16V4Z
1
2
C214
18P_0402_50V8J
1
2
C202
0.1U_0402_16V4Z
1
2
R175 0_0402_5%
1 2
C201
0.1U_0402_16V4Z
1
2
R134 0_0402_5%
1 2
R167 39_0402_1%
1 2
R122
0_0805_5%
1 2
R124 0_0402_5%
1 2
R123
56_0402_5%
1 2
R126 475_0402_1%
1 2
C212
0.1U_0402_16V4Z
1
2
R146 475_0402_1%
1 2
Q3A 2N7002DW-7-F_SOT363-6
6 1
2
C211
0.1U_0402_16V4Z
1
2
R139
1K_0402_5%
@
12
R153 0_0402_5%
1 2
C206
10U_0805_10V4Z
1
2
Q3B 2N7002DW-7-F_SOT363-6
3
5
4
C216
12P_0402_50V8J
12
Y1
14.31818MHZ_16P
12
R154
0_0402_5%
1 2
C205
0.1U_0402_16V4Z
1
2
R131 0_0402_5%
1 2
C217
4.7P_0402_50V8C
@
12
R152 0_0402_5%
1 2
R157
0_0402_5%
@
12
R145 0_0402_5%
1 2
R137 0_0402_5%
1 2
C215
5P_0402_50V8C
@
12
R158 33_0402_1%
1 2
C207
0.1U_0402_16V4Z
1
2
C200
0.1U_0402_16V4Z
1
2
R156 475_0402_1%
1 2
R143
1K_0402_5%
@
1 2
C218
4.7P_0402_50V8C
@
12
C203
0.1U_0402_16V4Z
1
2
R178
2.2K_0402_5%
R173 0_0402_5%
1 2
R142 0_0402_5%@
1 2
C204
0.1U_0402_16V4Z
1
2
R128
2.2K_0402_5%
1 2
R168 0_0402_5%
1 2
R726 0_0402_5%
1 2
R129
1K_0402_5%
1 2
R163
1K_0402_5%
@
12
R133 475_0402_1%
1 2
R166 0_0402_5%
1 2
R162 475_0402_1%
1 2
R183
10K_0402_5%
@
12
R164
10K_0402_5%
1 2
R180
10K_0402_5%
12
R144 0_0402_5%
1 2
www.kythuatvitinh.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
RED_L
GREEN_L
BLUE_L
HSYNC_G_A
VSYNC_G_A D_VSYNC
D_HSYNC
CRT_VSYNC
CRT_HSYNC
D_DDCDATA
D_DDCCLK
BLUE_L
GREEN_L
RED_L
3VDDCCL
3VDDCDA
BLUE_L
GREEN_L
RED_L
CRT_HSYNC20
CRT_VSYNC20
M_RED20
M_GREEN20
M_BLUE20
D_DDCDATA 40
D_DDCCLK 40
D_HSYNC40
D_VSYNC40
3VDDCDA 21
3VDDCCL 21
RED_L40
GREEN_L40
BLUE_L40
+CRTVDD+RCRT_VCC+5VS
+5VS
+CRTVDD +CRTVDD
+5VS +5VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
CRT Connector
18 53Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
W=40mils
CRT
Connector
Place close to
JCRT
#SI Remove pull low resistor
U4
SN74AHCT1G125GW_SOT353-5
A
2
Y
4
OE#
1
G
3
P
5
R239
150_0402_1%
12
D7
DAN217T146_SC59-3
@
2
3
1
U5
SN74AHCT1G125GW_SOT353-5
A
2
Y
4
OE#
1
G
3
P
5
C228
10P_0402_50V8J
1
2
L4
HLC0603CSCCR11JT_0603
1 2
C224
5P_0402_50V8C
@
1
2
L2
HLC0603CSCCR11JT_0603
1 2
D4
RB491D_SC59-3
2 1
C220
0.1U_0402_16V4Z
1
2
R185
2.2K_0402_5%
12
JCRT1
SUYIN_070546FR015S263ZR
CONN@
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
16
17
R238
150_0402_1%
12
R189
0_0603_5%
1 2
D6
DAN217T146_SC59-3
@
2
3
1
Q5B
2N7002DW-7-F_SOT363-6
3
5
4
F1
1.1A_6VDC_FUSE
21
L3
HLC0603CSCCR11JT_0603
1 2
C230
10P_0402_50V8J
1
2
C221
0.1U_0402_16V4Z
1 2
R187
2.2K_0402_5%
12
R184
0_0603_5%
1 2
Q5A
2N7002DW-7-F_SOT363-6
<BOM Structure>
6 1
2
R188
2.2K_0402_5%
12
R237
150_0402_1%
12
C229
10P_0402_50V8J
1
2
C222
0.1U_0402_16V4Z
1 2
R186
2.2K_0402_5%
12
C223
5P_0402_50V8C
@
1
2
D5
DAN217T146_SC59-3
@
2
3
1
www.kythuatvitinh.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDC2_DATA
DDC2_CLK
INV_PWM
BKOFF#
DAC_BRIG
LVDS_A2+
LVDS_A2-
LVDS_A1+
LVDS_A1-
LVDS_A0+
LVDS_A0-
LVDS_ACLK+
LVDS_ACLK-
DMIC_DAT
DMIC_CLK
DDC2_CLK
DDC2_DATA
USB20_N4
USB20_P4
+5V_LOGO
DMIC_DAT
DMIC_CLK
DMIC_DAT
DMIC_CLK
BKOFF#
ENAVDD21
INV_PWM 38
DAC_BRIG 38
BKOFF# 38
LVDS_A2+ 20
LVDS_A2- 20
LVDS_A1+ 20
LVDS_A1- 20
LVDS_A0+ 20
LVDS_A0- 20
LVDS_ACLK+ 20
LVDS_ACLK- 20
DMIC_DAT 33
DMIC_CLK 33
DDC2_DATA 21
DDC2_CLK 21
USB20_P427
USB20_N427
GPIO2027
+5VALW+LCDVDD
+3VS+LCDVDD
+LCDVDD
+3VS
INVPWR_B++LCDVDD+3VS
USB_CAM
USB_CAM
+3VS
+5VS
+5VS+5VALW
INVPWR_B+B+
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
LCD CONN.
19 53Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
Avoid Panel display garbage after power
on.
LVDS CONN WITH Camera and Digi MIC
Limited Current < 1A
USB_VCCA is +3.9V
USB_VCCA =1.25X(1+R1091/R1093)
USB Camera Power
1106 Add SB control pin
1108 EMI request
0308_Reserve L10 and install
L11.
#SI change lib
#SI Add GPIO20 control and reserve +5VS
#SI2 for EMI
#PV reserve pull low 10K
PJP604
PAD-OPEN 2x2m
2 1
C498
680P_0402_50V7K
@
1
2
Q8B2N7002DW-7-F_SOT363-6
3
5
4
R201
2.2K_0402_5%
12
C435
680P_0402_50V7K
1
2
C434
680P_0402_50V7K
1
2
R2073 0_0402_5%
@
1 2
Q8A
2N7002DW-7-F_SOT363-6
61
2
G
D
S
Q7
SI2301BDS-T1-E3_SOT23-3
2
1 3
C238
0.047U_0402_16V7K
R2072
0_0402_5%
1 2
C234
4.7U_0805_10V4Z
1
2
C233
4.7U_0805_10V4Z
1
2
L6
FBMA-L11-201209-221LMA30T_0805
1 2
C232
0.1U_0402_16V4Z
1
2
C1392
10U_0805_6.3V6M
1
2
R1093
100K_0402_1%
12
L5 0_0805_5%
@
1 2
C235
680P_0402_50V7K
12
JLVDS1
ACES_88242-4001
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
GND
41
GND
42
R1091
215K_0603_1%
12
R198
470_0402_5%
12
R199
1M_0402_5%
1 2
C1391
10U_0805_6.3V6M
1
2
R717
10K_0402_5%
@
12
U42
G916-390T1UF_SOT23-5
IN
1
GND
2
SHDN
3
OUT
5
BYP
4
R202
2.2K_0402_5%
1 2
PJP4
PAD-OPEN 2x2m
2 1
R200
100K_0402_5%
12
R203
2.2K_0402_5%
1 2
C236
680P_0402_50V7K
1
2
C2110
220P_0402_25V8J
@
1
2
C2111
220P_0402_25V8J
@
1
2
C239
0.22U_0603_10V7K
@
1
2
C496
680P_0402_50V7K
@
1
2
C237
680P_0402_50V7K
12
R727
100_0805_5%
1 2
C231
0.1U_0402_16V4Z
1
2
www.kythuatvitinh.com
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
VDD33
PEX_REFCLKP
PEX_REFCLKN
PEX_RST#
PEX_TXP0
PEX_TXN0
PEX_TXP1
PEX_TXN1
PEX_TX10
PEX_TX10*
PEX_TX11
PEX_TX11*
PEX_TX12
PEX_TX12*
PEX_TX13
PEX_TX13*
PEX_TX14
PEX_TX14*
PEX_TXP15
PEX_TXN15
PEX_TXP2
PEX_TXN2
PEX_TXP3
PEX_TXN3
PEX_TXN4
PEX_TXP5
PEX_TXN5
PEX_TXP4
PEX_TXP6
PEX_TXN6
PEX_TXP7
PEX_TXN7
PEX_TXP8
PEX_TXN8
PEX_TX9
PEX_TX9*
PEX_PLLDVDD
IFPB_IOVDD
IFPAB_PLLVDD
DACB_VDD
DACA_VDD
DACA_VREF
IFPAB_RSET
IFPA_IOVDD
PEG_RXN211
PEG_RXN311
PEG_RXN411
PEG_RXN611
PEG_RXN711
PEG_RXN511
PEG_RXN1211
PEG_RXN1411
PEG_RXN1511
PEG_RXN1311
PEG_RXN811
PEG_RXN1011
PEG_RXN1111
PEG_RXN911
PEG_RXP411
PEG_RXP611
PEG_RXP711
PEG_RXP511
PEG_RXP011
PEG_RXP211
PEG_RXP311
PEG_RXP1211
PEG_RXP1411
PEG_RXP1511
PEG_RXP1311
PEG_RXP811
PEG_RXP1011
PEG_RXP1111
PEG_RXP911
PEG_RXP111
PEG_RXN111
PEG_RXN011
PEG_M_TXN011
PEG_M_TXN111
PEG_M_TXN211
PEG_M_TXN311
PEG_M_TXP011
PEG_M_TXP111
PEG_M_TXP311
PEG_M_TXP211
PEG_M_TXN411
PEG_M_TXN511
PEG_M_TXN711
PEG_M_TXN811
PEG_M_TXN911
PEG_M_TXN1011
PEG_M_TXN1111
PEG_M_TXN1311
PEG_M_TXN1411
PEG_M_TXN1511
PEG_M_TXP411
PEG_M_TXP511
PEG_M_TXP711
PEG_M_TXP811
PEG_M_TXP911
PEG_M_TXP1011
PEG_M_TXP1111
PEG_M_TXP1311
PEG_M_TXP1411
PEG_M_TXP1511
PEG_M_TXN1211
PEG_M_TXP1211
PEG_M_TXN611
PEG_M_TXP611
CRT_VSYNC 18
M_BLUE 18
M_GREEN 18
CRT_HSYNC 18
M_RED 18
CLK_PCIE_VGA17
CLK_PCIE_VGA#17
LVDS_A2- 19
LVDS_A2+ 19
LVDS_A0- 19
LVDS_A0+ 19
LVDS_A1+ 19
LVDS_A1- 19
LVDS_ACLK- 19
LVDS_ACLK+ 19
PLT_RST#9,25,30,31,32
+PCIE
+PCIE
+PCIE
+NVVDD
+3VS
+VDD_MEM18
+VDD_MEM18
+3VS
+NVVDD_SENSE
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
PEG & LVDS & DAC
Custom
20 53Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
1.920 Amps
120mA
600 mA
110 mA
100mA
LVDS & DAC Interface
100 mA
DAC C
150 mA
PEG Interface
22u X 3
0.47u X 7
0.1u X 7
DAC A
DAC B
CRT
TV-OUT
#SI Remove TV out
#SI Remove TV out
#SI Change to +VDDMEM18
#SI Change to +VDDMEM18
C307 0.1U_0402_16V4Z
1 2
C287
22U_0805_6.3VAM
1
2
C273
0.1U_0402_16V4Z
1
2
C306 0.1U_0402_16V4Z
1 2
C289
22U_0805_6.3VAM
1
2
C315 0.1U_0402_16V4Z
1 2
C279
4700P_0402_25V7K
1
2
C302 0.1U_0402_16V4Z
1 2
C324 0.1U_0402_16V4Z
1 2
C317
1U_0402_6.3V4Z
1
2
C447
1U_0402_6.3V4Z
1
2
B
B
A
A
CLOCK
DATA
6/13 IFPAB
U17F
NB9M-GS_BGA_533P
COMMON
V2
IFPB_IOVDD
V3
IFPA_IOVDD
AB6
IFPAB_RSET
AD5
IFPAB_PLLVDD
AB3
IFPB_TXC
AB2
IFPB_TXC
AC4
IFPA_TXC
AD4
IFPA_TXC
AB1
IFPB_TXD7
AA1
IFPB_TXD7
AA2
IFPB_TXD6
AA3
IFPB_TXD6
W3
IFPB_TXD5
W2
IFPB_TXD5
W1
IFPB_TXD4
V1
IFPB_TXD4
AB4
IFPA_TXD3
AB5
IFPA_TXD3
W4
IFPA_TXD2
Y4
IFPA_TXD2
AA5
IFPA_TXD1
AA4
IFPA_TXD1
V5
IFPA_TXD0
V4
IFPA_TXD0
C314
0.1U_0402_16V4Z
1
2
C284 0.1U_0402_16V4Z
1 2
C286
470P_0402_50V7K
1
2
C251
4.7U_0603_6.3V6K
1
2
C446
0.01U_0402_25V7K
1
2
3/13 DACA
U17C
COMMON
NB9M-GS_BGA_533P
AF1
DACA_VREF
AG2
DACA_VDD
AD3
DACA_BLUE
AE3
DACA_GREEN
AE2
DACA_RED
AD1
DACA_VSYNC
AD2
DACA_HSYNC
AE1
DACA_RSET
C303 0.1U_0402_16V4Z
1 2
C320
470P_0402_50V7K
1
2
C271 0.1U_0402_16V4Z
1 2
C321
0.1U_0402_16V4Z
1
2
C276
0.1U_0402_16V4Z
1
2
C310 0.1U_0402_16V4Z
1 2
R197
150_0402_1%
12
C281 0.1U_0402_16V4Z
1 2
C294 0.1U_0402_16V4Z
1 2
C328 0.1U_0402_16V4Z
1 2
R392 0_0402_5%
1 2
C300
470P_0402_50V7K
1
2
R210
10K_0402_5%
1 2
R195
150_0402_1%
12
1/13 PCI_EXPRESS
U17A
NB9M-GS_BGA_533P
COMMON
AE27
PEX_RX15
AF27
PEX_RX15
AE26
PEX_TX15
AE25
PEX_TX15
AG26
PEX_RX14
AG25
PEX_RX14
AD24
PEX_TX14
AD23
PEX_TX14
AF25
PEX_RX13
AG24
PEX_RX13
AD22
PEX_TX13
AC22
PEX_TX13
AF24
PEX_RX12
AE24
PEX_RX12
AB22
PEX_TX12
AB21
PEX_TX12
AE22
PEX_RX11
AF22
PEX_RX11
AC21
PEX_TX11
AD21
PEX_TX11
AG22
PEX_RX10
AG21
PEX_RX10
AD20
PEX_TX10
AD19
PEX_TX10
AF21
PEX_RX9
AE21
PEX_RX9
AB20
PEX_TX9
AB19
PEX_TX9
AE19
PEX_RX8
AF19
PEX_RX8
AB18
PEX_TX8
AC18
PEX_TX8
AG19
PEX_RX7
AG18
PEX_RX7
AD18
PEX_TX7
AD17
PEX_TX7
AF18
PEX_RX6
AE18
PEX_RX6
AD16
PEX_TX6
AC16
PEX_TX6
AE16
PEX_RX5
AF16
PEX_RX5
AB15
PEX_TX5
AB14
PEX_TX5
AG16
PEX_RX4
AG15
PEX_RX4
AC15
PEX_TX4
AD15
PEX_TX4
AF15
PEX_RX3
AE15
PEX_RX3
AD14
PEX_TX3
AD13
PEX_TX3
AE13
PEX_RX2
AF13
PEX_RX2
AB12
PEX_TX2
AB11
PEX_TX2
AG13
PEX_RX1
AG12
PEX_RX1
AC12
PEX_TX1
AD12
PEX_TX1
AF12
PEX_RX0
AE12
PEX_RX0
AD11
PEX_TX0
AD10
PEX_TX0
AC10
PEX_REFCLK
AB10
PEX_REFCLK
AD9
PEX_RST
AE9
RFU
AG10
PEX_TERMP
AG9
RFU
AE10
PEX_TSTCLK_OUT
AF10
PEX_TSTCLK_OUT
AF9
PEX_PLLVDD
F12
VDD33
E12
VDD33
D12
VDD33
C12
VDD33
B12
VDD33
A12
VDD33
W16
GND_SENSE
W15
VDD_SENSE
W9
VDD
W19
VDD
W18
VDD
W13
VDD
W12
VDD
W10
VDD
U9
VDD
U19
VDD
T9
VDD
T17
VDD
T11
VDD
R9
VDD
R17
VDD
R16
VDD
R15
VDD
R14
VDD
R13
VDD
R12
VDD
R11
VDD
P17
VDD
P16
VDD
P15
VDD
P14
VDD
P13
VDD
P12
VDD
P11
VDD
N9
VDD
N19
VDD
N17
VDD
N16
VDD
N15
VDD
N14
VDD
N13
VDD
N12
VDD
N11
VDD
M9
VDD
M17
VDD
M11
VDD
L9
VDD
J9
VDD
J13
VDD
J12
VDD
J10
VDD
AG6
PEX_IOVDDQ
AF6
PEX_IOVDDQ
AE6
PEX_IOVDDQ
AD6
PEX_IOVDDQ
AC7
PEX_IOVDDQ
AC13
PEX_IOVDDQ
AB9
PEX_IOVDDQ
AB8
PEX_IOVDDQ
AB7
PEX_IOVDDQ
AB17
PEX_IOVDDQ
AB16
PEX_IOVDDQ
AB13
PEX_IOVDDQ
AG7
PEX_IOVDD
AF7
PEX_IOVDD
AE7
PEX_IOVDD
AD8
PEX_IOVDD
AD7
PEX_IOVDD
AC9
PEX_IOVDD
C327
0.1U_0402_16V4Z
1
2
C301 0.1U_0402_16V4Z
1 2
C267
470P_0402_50V7K
1
2
C244
0.1U_0402_16V4Z
1
2
C266
4700P_0402_25V7K
1
2
C331 0.1U_0402_16V4Z
1 2
C291 0.1U_0402_16V4Z
1 2
R196
150_0402_1%
12
R209
2.49K_0402_1%
1 2
C329 0.1U_0402_16V4Z
1 2
C268 0.1U_0402_16V4Z
1 2
C316 0.1U_0402_16V4Z
1 2
C252
0.1U_0402_16V4Z
1
2
C1476
0.1U_0402_16V4Z
1
2
C248
470P_0402_50V7K
1
2
C258
0.1U_0402_16V4Z
1
2
4/13 DACB
U17E
NB9M-GS_BGA_533P
COMMON
G6
DACB_VREF
D7
DACB_VDD
E6
DACB_BLUE
E7
DACB_GREEN
F7
DACB_RED
D6
DACB_CSYNC
F8
DACB_RSET
C282 0.1U_0402_16V4Z
1 2
5/13 DACC
U17D
NB9M-GS_BGA_533P
COMMON
R6
DACC_VREF
W5
DACC_VDD
R4
DACC_BLUE
T4
DACC_GREEN
T5
DACC_RED
U4
DACC_VSYNC
U6
DACC_HSYNC
V6
DACC_RSET
C305 0.1U_0402_16V4Z
1 2
C297
470P_0402_50V7K
1
2
C326 0.1U_0402_16V4Z
1 2
C295
470P_0402_50V7K
1
2
L8
BLM18PG181SN1D_0603
12
C293 0.1U_0402_16V4Z
1 2
L9
BLM18PG181SN1D_0603
12
C323 0.1U_0402_16V4Z
1 2
C296
470P_0402_50V7K
1
2
C292 0.1U_0402_16V4Z
1 2
R207
124_0402_1%
12
C283 0.1U_0402_16V4Z
1 2
C277
0.1U_0402_16V4Z
1
2
L7
BLM18PG181SN1D_0603
12
C298
470P_0402_50V7K
1
2
C330 0.1U_0402_16V4Z
1 2
R208 200_0402_1%
1 2
L10
BLM18PG181SN1D_0603
12
R205
1K_0402_1%
@
12
C246
4.7U_0603_6.3V6K
1
2
C249
470P_0402_50V7K
1
2
C247
4700P_0402_25V7K
1
2
C255
10U_0805_6.3V6M
1
2
C280
470P_0402_50V7K
1
2
C325
4.7U_0603_6.3V6M
1
2
C264
10U_0805_6.3V6M
1
2
R206
10K_0402_5%
1 2
C265 0.1U_0402_16V4Z
1 2
C308 0.1U_0402_16V4Z
1 2
C275
0.1U_0402_16V4Z
1
2
C288
22U_0805_6.3VAM
1
2
C257
4.7U_0603_6.3V6K
1
2
C263
4.7U_0603_6.3V6K
1
2
C274
0.1U_0402_16V4Z
1
2
C270 0.1U_0402_16V4Z
1 2
R204
0_0402_5%
1 2
C285
0.1U_0402_16V4Z
1
2
C262
1U_0603_10V4Z
1
2
C304 0.1U_0402_16V4Z
1 2
C278
0.1U_0402_16V4Z
1
2
C309 0.1U_0402_16V4Z
1 2
C322 0.1U_0402_16V4Z
1 2
C319
4700P_0402_25V7K
1
2
C254
4.7U_0603_6.3V6K
1
2
C311
1U_0603_10V4Z
1
2
C259
1U_0603_10V4Z
1
2
C253
1U_0603_10V4Z
1
2
C299
470P_0402_50V7K
1
2
www.kythuatvitinh.com
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GPU_PLLVDD
ROM_SCLK
ROM_SI
STRAP0
ROM_SO
STRAP2
STRAP1
VGA_THERMDA
VGA_THERMDC
THERM#_VGA
VGA_SM_CLK
VGA_SM_DA
THERM_SCI#
XTALIN XTALOUT
XTALIN
HDCP_WP
HDCP_WP
HDCP_SCL
HDCP_SDA
HDCP_SCL
STRAP2
STRAP1
STRAP0
HDCP_SDA
HDCP_SCL
ROM_SO
ROM_SCLK
ROM_SI
ROM_CS#
SPDIF_IN
IFPC_IOVDD
IFPC_PLLVDD
IFPC_RSET
I2CE_SDA
I2CE_SCL
I2CB_SCL
I2CB_SDA
THERMAL ALERT
SINN_GPIO9
VGA_THERMDA
THERM#_VGA
VGA_THERMDC
JTAG_TRST
JTAG_TCK
JTAG_TMS
JTAG_TDO
JTAG_TDI
VGA_SM_CLK
ENVDD
VGA_SM_DA
DDC2_DATA
DDC2_CLK
THERM_SCI#
VGA_SM_CLK
VGA_SM_DA
HDMI_C_CLK-
HDMI_C_CLK+
HDMI_C_TX0+
HDMI_C_TX0-
HDMI_C_TX1+
HDMI_C_TX1-
HDMI_C_TX2+
HDMI_C_TX2-
I2CE_SDA
I2CE_SCL
HDA_SDIN2_R
I2CB_SDA
I2CB_SCL
HDMI_CLK-
HDMI_CLK+
HDMI_TX0+
HDMI_TX0-
HDMI_TX2+
HDMI_TX2-
HDMI_TX1+
HDMI_TX1-
THERM_SCI# 27,38
27M_SSC17
27M_CLK17
SPDIF_OUT033
ENBKL 38
HDMI_DETECT 42
ENAVDD 19
3VDDCDA 18
3VDDCCL 18
ICH_SMBCLK17,27,31,37
ICH_SMBDATA17,27,31,37
DDC2_CLK 19
DDC2_DATA 19
SMB_EC_DA2 6,38
SMB_EC_CK2 6,38
HDA_SDOUT_VGA 26
HDA_BITCLK_VGA 26
HDA_SDIN2 26
HDA_SYNC_VGA 26
HDA_RST#_VGA 26
HDMI_CLK+ 42
HDMI_CLK- 42
HDMI_TX0+ 42
HDMI_TX0- 42
HDMI_TX1- 42
HDMI_TX1+ 42
HDMI_TX2- 42
HDMI_TX2+ 42
GPU_VID0 47
GPU_VID1 47
HDMICLK_VGA 42
HDMIDAT_VGA 42
+PCIE
+3VS
+3VS
+3VS
+3VS +3VS
+3VS
+3VS
+3VS
+3VS
+VDD_MEM18
+PCIE
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
Straps & HDMI
Custom
21 53Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
36 mA
HDCP
ROM
45 Kohms
16MX16 Hynix
ValueDDR2
Straps
MULTI LEVEL STRAPS
Resistor
30 Kohms
10 Kohms
20 Kohms
VGA Thermal Sensor
ADM1032ARMZ
Closed to VGA
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
Primary DVI Hot-plug
Panel Back-Light PWM
Panel Power Enable
Panel Back-Light Enable
NVVDD VID0
NVVDD VID1
FBVDD VID0
Thermal Alert
FAN PWM
FBVref Select
SLI SYNCO
AC Detect
PS Control or HDMI_CEC
PS Control
N/A
N/A
H
H
H
N/A
N/A
N/A
L
L
N/A
N/A
N/A
L
H
2nd DVI Hot-plug
GPIO I/O ACTIVE USAGE
160 mA
385 mA
LVDS
CRT
HD AUDIO
SPDIF
9/21 R329 near GPU
9/21 R237, R238, R240, R241 near ICH
9/21 follow 17"
16MX16 Samsung
32MX16 Hynix
32MX16 Samsung
R248Locating
GPU_VID1 GPU_VID0 +NVVDD
0
0
1
0
1
0
0.9V
1.09V
unused
HDMI
#SI Change to +VDDMEM18
#SI Add GPU_VID1
#SI2 add 2N7002 to GND
#SI2 change to pull hi
T50
@
R967
499_0402_1%
12
R965
499_0402_1%
12
R211
10K_0402_5%
12
C347
470P_0402_50V7K
1
2
L13
BLM18PG181SN1D_0603
12
R235
10K_0402_5%
@
12
R21510K_0402_5%
12
C1469 0.1U_0402_16V4Z
1 2
L14
BLM18PG181SN1D_0603
12
9/13 I2C_GPIO_THERM_JTAG
U17M
NB9M-GS_BGA_533P
COMMON
T2
I2CS_SDA
T1
I2CS_SCL
AG3
JTAG_TRST
AE4
JTAG_TDO
AG4
JTAG_TDI
AF4
JTAG_TMS
AF3
JTAG_TCK
D9
THERMDP
D8
THERMDN
F2
GPIO19
F1
GPIO18
G2
GPIO17
G3
GPIO16
F3
GPIO15
K1
GPIO14
J1
GPIO13
J3
GPIO12
D1
GPIO11
D2
GPIO10
M1
GPIO9
C2
GPIO8
J2
GPIO7
K2
GPIO6
K3
GPIO5
M3
GPIO4
M2
GPIO3
C1
GPIO2
G1
GPIO1
N1
GPIO0
W6
I2CE_SDA
Y6
I2CE_SCL
N3
I2CD_SDA
N2
I2CD_SCL
B1
I2CC_SDA
A2
I2CC_SCL
R3
I2CB_SDA
R2
I2CB_SCL
T3
I2CA_SDA
R1
I2CA_SCL
R2260_0402_5%
@
12
R3960_0402_5%
1 2
R966
499_0402_1%
12
R2312K_0402_5%
1 2
R243
45.3K_0402_1%
1 2
T51
@
R250
5.1K_0402_5%
@
1 2
C340
4700P_0402_25V7K
1
2
R220
10K_0402_5%
@
12
C349
0.01U_0402_25V7K
1 2
R246
5.1K_0402_5%
@
1 2
R2322K_0402_5%
1 2
R244
10K_0402_1%
1 2
T49
@
R221
10K_0402_5%
@
12
T48
@
C343
4.7U_0603_6.3V6K
1
2
R249
5.1K_0402_5%
@
1 2
C1468 0.1U_0402_16V4Z
1 2
R223
10K_0402_5%
12
R962
499_0402_1%
12
C351
0.1U_0402_16V4Z
1
2
R229
10K_0402_5%
@
12
C1473 0.1U_0402_16V4Z
1 2
C342
4.7U_0603_6.3V6K
1
2
R1129 0_0402_5%
12
C337
4.7U_0603_6.3V6K
1
2
R3950_0402_5%
1 2
C341
470P_0402_50V7K
1
2
C
MXM DVI DP
7/13 IFPC
TXC
TXC
TXD2
TXD1
TXD2
TXD1
TXD0
TXD0
TXC
TXC
TXD1
TXD2
TXD2
TXD1
TXD0
TXD0
U17H
NB9M-GS_BGA_533P
COMMON
J6
IFPC_IOVDD
R5
IFPC_RSET
P6
IFPC_PLLVDD
P4
IFPC_L0
N4
IFPC_L0
M5
IFPC_L1
M4
IFPC_L1
L4
IFPC_L2
K4
IFPC_L2
H4
IFPC_L3
J4
IFPC_L3
G4
IFPC_AUX
G5
IFPC_AUX
R234
10K_0402_5%
12
11/13 MISC
U17L
NB9M-GS_BGA_533P
COMMON
D15
RFU
C15
RFU
F9
SPDIF
F10
STRAP_REF_MIOB
F11
STRAP_REF_3V3
A9
STRAP2
B9
STRAP1
C7
STRAP0
AC6
RFU_GND
AD25
TESTMODE
F6
RFU
J5
RFU
N5
BUFRST
A4
I2CH_SDA
A3
I2CH_SCL
C9
ROM_SCLK
C10
ROM_SO
A10
ROM_SI
B10
ROM_CS
R1130 0_0402_5%
12
R21310K_0402_5%
1 2
R961
499_0402_1%
<BOM Structure>
12
R2302K_0402_5%
1 2
C1472 0.1U_0402_16V4Z
1 2
C1474 0.1U_0402_16V4Z
1 2
R228
10K_0402_5%
@
12
R242
5.1K_0402_5%
@
1 2
R224
10K_0402_5%
@
12
C350
2200P_0402_50V7K
@
1 2
R2250_0402_5% @
12
R245
5.1K_0402_5%
@
1 2
U7
AT88SC0808
A0
1
A1
2
SDA
5
SCL
6
VCC
8
A2
3
GND
4
WP
7
T47
@
R247
5.1K_0402_5%
1 2
C356
18P_0402_50V8J
@
1
2
R964
499_0402_1%
12
R233 0_0402_5%
1 2
C1470 0.1U_0402_16V4Z
1 2
R252
15K_0402_5%
1 2
C353
1U_0402_6.3V4Z
1
2
C338
4.7U_0603_6.3V6K
1
2
R212
1K_0402_1%
12
C346
4700P_0402_25V7K
1
2
C354
0.1U_0402_16V4Z
1
2
C352
1U_0402_6.3V4Z
1
2
12/13 XTAL_PLL
U17K
NB9M-GS_BGA_533P
COMMON
D11
XTAL_SSIN
L6
SP_PLLVDD
K6
VID_PLLVDD
K5
PLLVDD
E10
XTAL_OUT
E9
XTAL_OUTBUFF
D10
XTAL_IN
R253
5.1K_0402_5%
@
1 2
G
D
S
Q74
2N7002_SOT23-3
2
13
R963
499_0402_1%
12
R2272K_0402_5%
1 2
C357
18P_0402_50V8J
@
1
2
C348
0.1U_0402_16V4Z
@
1
2
R216
40.2K_0402_1%
1 2
C1475 0.1U_0402_16V4Z
1 2
R214
40.2K_0402_1%
1 2
R248
45.3K_0402_1%
1
10/13 HDAUDIO
U17I
NB9M-GS_BGA_533P
COMMON
B6
HDA_SDO
A6
HDA_SDI
B7
HDA_SYNC
A7
HDA_BCLK
C6
HDA_RST
C497
1U_0402_6.3V4Z
1
2
L12
BLM18PG181SN1D_0603
12
C355
0.1U_0402_16V4Z
1
2
R960
499_0402_1%
12
C1471 0.1U_0402_16V4Z
1 2
R218
10K_0402_5%
12
R251
5.1K_0402_5%
1 2
R217
10K_0402_5%
@
12
R222
10K_0402_5%@
1 2
U6
ADM1032ARMZ REEL_MSOP8@
VDD
1
ALERT#
6
THERM#
4
GND
5
D+
2
D-
3
SCLK
8
SDATA
7
R219
10K_0402_5%
@
1 2
DP
8/13 IFPE
DVIMXM
E
TXC
TXC
TXD2
TXD1
TXD2
TXD1
TXD0
TXD0
TXC
TXC
TXD1
TXD2
TXD2
TXD1
TXD0
TXD0
U17G
NB9M-GS_BGA_533P
COMMON
H6
IFPE_IOVDD
M6
IFPE_RSET
N6
IFPE_PLLVDD
F5
IFPE_L0
F4
IFPE_L0
E4
IFPE_L1
D5
IFPE_L1
C3
IFPE_L2
C4
IFPE_L2
B3
IFPE_L3
B4
IFPE_L3
D3
IFPE_AUX
D4
IFPE_AUX
R399 33_0402_5%
1 2
R236
10K_0402_5%
12
www.kythuatvitinh.com
A
A
1 1
QSA3
QSA2
QSA#0
QSA#1
QSA1
QSA#3
QSA#2
QSA0
QSA4
QSA5
QSA6
QSA7
QSA#4
QSA#5
QSA#6
QSA#7
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
MDA[63 48]
MDA[15 0]
MDA56
MDA62
MDA63
MDA59
MDA61
MDA58
MDA60
MDA45
MDA57
MDA44
MDA40
MDA47
MDA41
MDA46
MDA42
MDA33
MDA35
MDA43
MDA28
MDA38
MDA37
MDA34
MDA39
MDA36
MDA20
MDA23
MDA30
MDA31
MDA32
MDA21
MDA25
MDA22
MDA26
MDA24
MDA29
MDA2
MDA15
MDA13
MDA27
MDA0
MDA18
MDA9
MDA8
MDA12
MDA1
MDA3
MDA16
MDA11
MDA10
MDA5
MDA7
MDA14
MDA19
MDA6
MDA17
MDA4
MDA50
MDA54
MDA55
MDA48
MDA49
MDA52
MDA53
MDA51
MDA[31 16]
MDA[47 32]
CMDA15
CMDA2
CMDA9
CMDA22
CMDA16
CMDA3
CMDA28
CMDA10
CMDA23
CMDA17
CMDA4
CMDA11
CMDA24
CMDA29
CMDA5
CMDA18
CMDA0
CMDA12
CMDA25
CMDA6
CMDA19
CMDA30
CMDA13
CMDA26
CMDA7
CMDA20
CMDA14
CMDA1
CMDA27
CMDA8
CMDA21
CMDA11
CMDA12
FB_PLLAVDD
CLKA0 23
CLKA0# 23
CLKA1 24
CLKA1# 24
QSA#[3 0]23
QSA[3 0]23
QSA#[7 4]24
QSA[7 4]24
DQMA[3 0]23
DQMA[7 4]24
MDA[15 0]23
MDA[63 48]24
MDA[47 32]24
MDA[31 16]23
CMDA[30 0] 23,24
+VDD_MEM18
+VDD_MEM18
+VDD_MEM18
+VDD_MEM18
+PCIE
+VDD_MEM18 +1.8VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-4102P Blade discrete
0.4
VRAM / GND
Custom
22 53Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
VRAM Interface
Rt
Rb
9/18 add R for nvidia
#SI2 change to short pad
2/13 FRAME_BUFFER
U17B
NB9M-GS_BGA_533P
COMMON
A16
FB_VREF
AA27
FBA_DQS_RN7
Y24
FBA_DQS_RN6
R27
FBA_DQS_RN5
R22
FBA_DQS_RN4
A18
FBA_DQS_RN3
E18
FBA_DQS_RN2
D25
FBA_DQS_RN1
B24
FBA_DQS_RN0
AA26
FBA_DQS_WP7
AA24
FBA_DQS_WP6
T27
FBA_DQS_WP5
T22
FBA_DQS_WP4
A19
FBA_DQS_WP3
E19
FBA_DQS_WP2
C25
FBA_DQS_WP1
A24
FBA_DQS_WP0
AB27
FBA_DQM7
AA23
FBA_DQM6
T26
FBA_DQM5
T24
FBA_DQM4
B19
FBA_DQM3
D19
FBA_DQM2
C26
FBA_DQM1
D23
FBA_DQM0
AD27
FBA_D63
AD26
FBA_D62
AB26
FBA_D61
AB25
FBA_D60
AA25
FBA_D59
W27
FBA_D58
W26
FBA_D57
W25
FBA_D56
AC24
FBA_D55
AB24
FBA_D54
AB23
FBA_D53
AA22
FBA_D52
W24
FBA_D51
W23
FBA_D50
W22
FBA_D49
V22
FBA_D48
V27
FBA_D47
V25
FBA_D46
V26
FBA_D45
T25
FBA_D44
R26
FBA_D43
R25
FBA_D42
N26
FBA_D41
N25
FBA_D40
V24
FBA_D39
V23
FBA_D38
U24
FBA_D37
T23
FBA_D36
R24
FBA_D35
R23
FBA_D34
P24
FBA_D33
P22
FBA_D32
A21
FBA_D31
B21
FBA_D30
C21
FBA_D29
C19
FBA_D28
D18
FBA_D27
C18
FBA_D26
B18
FBA_D25
C16
FBA_D24
F21
FBA_D23
E21
FBA_D22
F20
FBA_D21
D20
FBA_D20
F18
FBA_D19
D17
FBA_D18
E16
FBA_D17
D16
FBA_D16
B27
FBA_D15
C27
FBA_D14
D27
FBA_D13
D26
FBA_D12
D24
FBA_D11
E24
FBA_D10
E22
FBA_D9
D22
FBA_D8
A26
FBA_D7
A25
FBA_D6
B25
FBA_D5
C24
FBA_D4
A22
FBA_D3
B22
FBA_D2
C22
FBA_D1
D21
FBA_D0
T19
FB_DLLAVDD
R19
FB_PLLAVDD
M22
FBA_DEBUG
B16
FB_CAL_TERM_GND
A15
FB_CAL_PU_GND
B15
FB_CAL_PD_VDDQ
N23
FBA_CLK1
N24
FBA_CLK1
F23
FBA_CLK0
F24
FBA_CLK0
L22
RFU
J22
RFU
K22
FBA_CMD28
M24
FBA_CMD27
G27
FBA_CMD26
G24
FBA_CMD25
J26
FBA_CMD24
F27
FBA_CMD23
H24
FBA_CMD22
M26
FBA_CMD21
H22
FBA_CMD20
K25
FBA_CMD19
G22
FBA_CMD18
K24
FBA_CMD17
K23
FBA_CMD16
L24
FBA_CMD15
G25
FBA_CMD14
K27
FBA_CMD13
M25
FBA_CMD12
J23
FBA_CMD11
G26
FBA_CMD10
G23
FBA_CMD9
J27
FBA_CMD8
J25
FBA_CMD7
K26
FBA_CMD6
M27
FBA_CMD5
N27
FBA_CMD4
M23
FBA_CMD3
F25
FBA_CMD2
J24
FBA_CMD1
F26
FBA_CMD0
Y22
FBVDDQ
U22
FBVDDQ
N22
FBVDDQ
M19
FBVDDQ
L26
FBVDDQ
L23
FBVDDQ
L19
FBVDDQ
J19
FBVDDQ
J18
FBVDDQ
J16
FBVDDQ
J15
FBVDDQ
H26
FBVDDQ
H23
FBVDDQ
F22
FBVDDQ
F19
FBVDDQ
F17
FBVDDQ
F16
FBVDDQ
F15
FBVDDQ
F14
FBVDDQ
F13
FBVDDQ
E13
FBVDDQ
D14
FBVDDQ
D13
FBVDDQ
C13
FBVDDQ
B13
FBVDDQ
A13
FBVDDQ
C371
4700P_0402_25V7K
1
2
R258
1K_0402_1%
@
12
C372
0.1U_0402_16V4Z
<BOM Structure>
1
2
C365
0.1U_0402_16V4Z
1
2
C373
1U_0402_6.3V4Z
1
2
C380
1U_0402_6.3V4Z
1
2
C360
0.1U_0402_16V4Z
1
2
R257
10K_0402_5% @
1 2
L15
BLM18PG181SN1D_0603
12
C362
4700P_0402_25V7K
1
2
R259
1K_0402_1%
@
12
PJP605
PAD-OPEN 3x3m
1 2
C369
4700P_0402_25V7K
1
2
C366
0.022U_0402_16V7K
1
2
C376
0.1U_0402_16V4Z
1
2
C375
0.022U_0402_16V7K
1
2
C379
0.01U_0402_25V7K
1
2
R255 30_0402_1%
1 2
C358
0.022U_0402_16V7K
1
2
R394 10K_0402_5%
1 2
C361
4700P_0402_25V7K
1
2
C359
0.022U_0402_16V7K
1
2
C370
4700P_0402_25V7K
1
2
13/13 GND_NC
U17J
NB9M-GS_BGA_533P
COMMON
Y5
GND
Y26
GND
Y23
GND
Y2
GND
W17
GND
W14
GND
W11
GND
V9
GND
V19
GND
U5
GND
U26
GND
U23
GND
U2
GND
U17
GND
U16
GND
U15
GND
U14
GND
U13
GND
U12
GND
U11
GND
T16
GND
T15
GND
T14
GND
T13
GND
T12
GND
P9
GND
P5
GND
P26
GND
P23
GND
P2
GND
P19
GND
M16
GND
M15
GND
M14
GND
M13
GND
M12
GND
L5
GND
L2
GND
L17
GND
L16
GND
L15
GND
L14
GND
L13
GND
L12
GND
L11
GND
K9
GND
K19
GND
J17
GND
J14
GND
J11
GND
H5
GND
H2
GND
E8
GND
E5
GND
E26
GND
E23
GND
E20
GND
E2
GND
E17
GND
E14
GND
E11
GND
B8
GND
B5
GND
B26
GND
B23
GND
B20
GND
B2
GND
B17
GND
B14
GND
B11
GND
AF8
GND
AF5
GND
AF26
GND
AF23
GND
AF20
GND
AF2
GND
AF17
GND
AF14
GND
AF11
GND
AC8
GND
AC5
GND
AC26
GND
AC23
GND
AC20
GND
AC2
GND
AC17
GND
AC14
GND
AC11
GND
T6
NC
E15
NC
AC19
NC
AA6
NC
R1131 10K_0402_5%
1 2
R256 40.2_0402_1%@
1 2
C378
0.1U_0402_16V4Z
@
1
2
C364
0.1U_0402_16V4Z
1
2
C363
0.022U_0402_16V7K
1
2
C368
4.7U_0603_6.3V6K
1
2
C374
1U_0402_6.3V4Z
1
2
C377
1U_0402_6.3V4Z
1
2
R254 30_0402_1%
1 2
C367
4.7U_0603_6.3V6K
1
2
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MDA[63 0]
DQMA[7 0]
DQMA3
QSA#1
CLKA0
CLKA0#
QSA[7 0]
QSA3
QSA1
QSA#[7 0]
DQMA1
MDA30
MDA29
MDA12
MDA15
MDA31
MDA8
MDA13
MDA25
MDA24
MDA26
MDA27
MDA11
MDA28
MDA14
MDA9
MDA10
QSA#3
CMDA[30 0]
MEM_VREF0
CMDA16
CMDA17
CMDA14
CMDA2
CMDA3
CMDA1
CMDA0
CMDA24
CMDA22
CMDA19
CMDA23
CMDA20
CMDA18
CMDA10
CMDA21
CMDA8
CMDA25
CMDA9
CMDA15
CMDA11
CMDA12
QSA#0
MDA18
CMDA11
CMDA23
CMDA20
MDA19
CMDA1
MDA5
CMDA21
CMDA19
MDA0
CMDA9
CMDA2
CMDA3
MDA22
MDA17
MDA16
MDA1
QSA0
CMDA22 MDA20
MDA6
DQMA0
DQMA2
MDA7
CMDA14
CMDA25
CMDA12
MEM_VREF0
CMDA10
MDA21
MDA23
MDA2
QSA#2
CMDA16
MDA4
CMDA0
CMDA24
CLKA0
QSA2
CMDA8
CMDA15
CMDA17
CMDA18
CLKA0#
CLKA0#
CLKA0
MDA3
CMDA27 CMDA27
QSA[7 0]22,24
QSA#[7 0]22,24
CLKA022
CLKA0#22
DQMA[7 0]22,24
MDA[63 0]22,24
CMDA[30 0]22,24
+VDD_MEM18
+VDD_MEM18+VDD_MEM18
+VDD_MEM18
+VDD_MEM18
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Monday, February 25, 2008
2008/02/25 2008/02/25
Compal Electronics, Inc.
7
DDR BGA MEMORY
LS-2821 ATI_M56-P VGA Board
0.1
16
CHANNEL A EXT. 256M_1
VRAM DDR2 chips (256MB & 512MB)
32Mx16 DDR2 400MHz *4==>256MB
64Mx16 DDR2 400MHz*4==>512MB
CMD22
CMD23 A7
A5
A6
A9
A8
BA1
A10
A11
RAS#
A6
A7
A9
A8
BA1
BA2
A13
CAS#
A10
A11
CMD30
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
RAS#
BA2
A13
CAS#
CMD15
A4
DATA Bus
Address
A12
32 63
A3
A0
A2
0 31
A1
CS#
WE#
BA0
A0
CMD0
CKE
A1
CMD1
ODT
CMD2
CMD3
A12
A3
A4
CMD4
CMD5
CMD6
CMD7
A5
CS#CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
WE#
BA0
CKE
ODT
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21
(SSTL-1.8) VREF = .5*VDDQ
DDR2 BGA MEMORY
#PV reserve CMD27 to suport 64M x 16
C389
0.1U_0402_16V4Z
1
2
C392
0.01U_0402_16V7K
1
2
C397
0.01U_0402_16V7K
1
2
C393
0.01U_0402_16V7K
1
2
U9
HY5PS561621F-25
VREF
J2
LDM
F3
UDM
B3
DQ14
B1
DQ13
D9
DQ12
D1
DQ11
D3
DQ10
D7
DQ9
C2
DQ8
C8
DQ7
F9
DQ6
F1
DQ5
H9
DQ4
H1
DQ3
H3
DQ2
H7
DQ1
G2
DQ0
G8
BA1
L3
BA0
L2
A11
P7
A10/AP
M2
A9
P3
A8
P8
A7
P2
A6
N7
A5
N3
A4
N8
A3
N2
A0
M8
A1
M3
A2
M7
RAS
K7
CKE
K2
ODT
K9
CS
L8
CAS
L7
CK
J8
CK
K8
WE
K3
VDDQ10
G9
VDDQ1
A9
VDDQ2
C1
VDDQ3
C3
VDDQ4
C7
VDDQ5
C9
VDDQ6
E9
VDDQ7
G1
VSSQ1
A7
VSSQ2
B2
VSSQ3
B8
VSSQ4
D2
VSSQ5
D8
VSSQ6
E7
VSSQ7
F2
VSSQ8
F8
VSSQ9
H2
VSSQ10
H8
VSS1
A3
VSS2
E3
VSS3
J3
VSS4
N1
VSS5
P9
UDQS
A8
UDQS
B7
LDQS
E8
LDQS
F7
VDDQ8
G3
VDDQ9
G7
VDD1
A1
VDD2
E1
VDD3
J9
VDD4
M9
VDD5
R1
A12
R2
DQ15
B9
VDDL
J1
VSSDL
J7
NC#R8
R8
NC#A2
A2
NC#L1
L1
NC#R3
R3
NC#R7
R7
NC#E2
E2
C400
0.1U_0402_16V4Z
1
2
C402
0.01U_0402_16V7K
1
2
R261
475_0402_1%
12
C395
1000P_0402_50V7K
1
2
C391
0.1U_0402_16V4Z
1
2
C381
0.1U_0402_16V4Z
1
2
C396
0.01U_0402_16V7K
1
2
C384
4.7U_0805_6.3V6K
1
2
C401
0.1U_0402_16V4Z
1
2
C383
0.1U_0402_16V4Z
1
2
R260
1K_0402_1%
12
C382
4.7U_0805_6.3V6K
1
2
C390
4.7U_0805_6.3V6K
1
2
R262
1K_0402_1%
12
U8
HY5PS561621F-25
VREF
J2
LDM
F3
UDM
B3
DQ14
B1
DQ13
D9
DQ12
D1
DQ11
D3
DQ10
D7
DQ9
C2
DQ8
C8
DQ7
F9
DQ6
F1
DQ5
H9
DQ4
H1
DQ3
H3
DQ2
H7
DQ1
G2
DQ0
G8
BA1
L3
BA0
L2
A11
P7
A10/AP
M2
A9
P3
A8
P8
A7
P2
A6
N7
A5
N3
A4
N8
A3
N2
A0
M8
A1
M3
A2
M7
RAS
K7
CKE
K2
ODT
K9
CS
L8
CAS
L7
CK
J8
CK
K8
WE
K3
VDDQ10
G9
VDDQ1
A9
VDDQ2
C1
VDDQ3
C3
VDDQ4
C7
VDDQ5
C9
VDDQ6
E9
VDDQ7
G1
VSSQ1
A7
VSSQ2
B2
VSSQ3
B8
VSSQ4
D2
VSSQ5
D8
VSSQ6
E7
VSSQ7
F2
VSSQ8
F8
VSSQ9
H2
VSSQ10
H8
VSS1
A3
VSS2
E3
VSS3
J3
VSS4
N1
VSS5
P9
UDQS
A8
UDQS
B7
LDQS
E8
LDQS
F7
VDDQ8
G3
VDDQ9
G7
VDD1
A1
VDD2
E1
VDD3
J9
VDD4
M9
VDD5
R1
A12
R2
DQ15
B9
VDDL
J1
VSSDL
J7
NC#R8
R8
NC#A2
A2
NC#L1
L1
NC#R3
R3
NC#R7
R7
NC#E2
E2
C388
0.01U_0402_16V7K
1
2
C385
0.1U_0402_16V4Z
1
2
C387
0.01U_0402_16V7K
1
2
C386
1000P_0402_50V7K
1
2
C398
0.1U_0402_16V4Z
1
2
C399
4.7U_0805_6.3V6K
1
2
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