Điện Tử - Cơ Sở Thiết Kế Mạch - Design Trên Máy Tính (Phân 2) part 7 pdf

Trang
vi
dl,l
nay, tin hi¢u S duqe
e~p
nh~t
10
Ian trong
vang
l(tp.
Hanh
vi
n~ty
se khong duqe
b(>
mo phung
th~
hi¢n. Tuy nhien, cae ket 4u;i tue thoi
co the
dUQ'C
hi~n
thi lrang qua Idnh
!TI6
phung
ke't
qua tdng hqp
mi leh.
7.
Call
I~nh
next

L¢nh
next
chi
dung
trong
cae
vong
l~p.
L¢nh
nay
co
tae
d~ng
lo"~1
bo
vi~c
thl!e hi¢n
uk
c;.tU
lc;nh
nam
giUa
eau
l~nh
next
va
cuoi
vong
h)p khi
dieu

ki¢n
lrong
can
l¢nh
duqc
nghi¢m
dung
(
tuang
tl.r
l¢nh
continue
trong
ngon
ngfr C
).
L¢nh
next
co
eftU
truc
cu
phap
nhu
Si.lU,
next
[<
nhiin _w)ng_/(lp >][
when
< di/I1_ ki¢n > L

Trang
twang
hqp
co
dc
Yang
l~p
lOng
nhau
thl vi¢c th!!c
hi~n
l¢nh
next
sc
duqc
xac
d~nh
mQt
cach
tuong
rninh htmg < nhilll_\"(Jng_'{/jJ >.
Neu
khong
c6
nhLin
vlmg
1~IP
trong
c<tU
l¢nh. lc;nh

next
se
lac
dy.ng len
vong
I~p
trong
cling
chua
l¢nh
next.
Vf
dl!,
L I : while I <
10
loup
L2: while
J <
10
loop
next
Ll
when I =
.I;
end
loop L2;
end
loop L1;
8.
Cau

I~nh
exit
Cau l¢nh exit
co
tht
duqc dung ben trang cae \'oog
"JP.
CflU
J¢nh nay e6
t[le
dl,lng b6 4ua cae l¢nh
con
!i li
cua vong
l(tp
va th!!c
hi~n
ngay J¢nh tiep
sau vong
I~p
vua ket thuc. L¢nh exit e6
clu
true
Cll
phap
nhu
sau,
exit [< J/J/(JI1_l'img_l(ip >][
when
<

Ji["u_
ki(;/1
>];
9.
Call
I~nh
wait
L¢nh wait dieu khien
bl)
1116
phong ngilng vi¢e tlwc hi¢n cae
qUi.i
trlnh
hO(lc
cae chuffilg
I["lnh
con
eho
16i
khi dicu
ki~n
ben trang cau
l~nh
duCjc
184
nghi~rn
dung.
Ta
co
the noi dlng dieu

ki~n
trong
diu
l~nh
wait
chi
co
the
duqc
nghi~rn
dung
khi
XU[lt
hi~n
cae sl!
ki~n
tren dl1ang tin
hi~tl.
Nhu
\'~y.
Ulc doi tl1qng
di11i~u
tham gia trong trung dieu ki¢n phui
HI
cae tin hicu. etc
dieu
kiGI1
de
ti~p
wc

qua trinh bt dung
co
the duqc bicu thj duai ba
d' mg
sau
day
trung
ngon
ngQ
VHDL:
wait
[on
<
{(ill
{/II
111('/1
> \' <
{ell
fill
IIh'JI
> \ J
- - . - - .
l until < hilill tM(c fo,<ic >]
- - <
[for
<
bi/lI_flufc_tllrfi_MiulI
>1;
Gill
l¢nh

wait
on:
chi cho
chung
1a
danh
stich
dc
duang
tin hi¢u
ma
b(l
mo
phong sc
cila
sl!
ki~n
( sl! lhay d6i
tr~ng
thai
cae
lill
hi¢u ). Vi
dl.l,
doi voi cau l¢nh
wait
on A.B;
qua
trinh rna ph6ng
sc

dUng
l<;li
eho
den
khi
c6
xuat
hi~n
sl!
ki~n
tren
dUOng
tin
hi~u
A,
hO(lc
B.
Sau
do
b(l
rna
ph6ng
se tiep
Il,lC
thl!c hi¢n C[IU l¢nh dung sau \¢nh
wait.
Cfm
l~nh
wait
until sc dil'tlg vi¢c thl!c hi¢n qu,i

tdnh
cho
tai
khi
bi~u
th(~c
logic
nh~n
gill
trj
truc.
GIU
I~nh
wait
Im.li
nay se
t~lO
ra
mQt
danh
saeh ng,im dinh
dc
tin
hi9U
lac
dOng trong
bitu
lh(rc
logic.
Moi kili

co
h[it ky
mQt
Sl!
ki~n
xu[i't
hi¢n tren
duang
tin
hi¢u trong
danh
sach
n~ly,
bieu
lillIe
16gic se
dm.K
tlnh.
Trong
twang
hgp l¢nh
wait
until khong
chua
bieu thuc l6gic,
chung
ta
hieu
rtlllg
cau

l~nh
se
la
wait
until
truc.
Vi
dl,l
Slr
dl,lllg l¢nh
wait
until,
wait
until x < 10;
qua
t["lnll
tlwc hi¢n se
dung
l~i
cho tai khi x < 10.
Cau l¢nh
wait
for
se dung
vi~c
rn6
ph6ng
qUit
trlnh m()t thai gian
bAng

gia tri thai gi,m duqc chi
djnh
ben trong
dieu
ki~n.
Sau
khoang thai giun duqc chi dinh,
h9
rno
phong
thl!c hi¢n I¢nh tic'p
theo sau l¢nh
wait.
Neu
bitu
thue thai gian khong co, chung ta
hitu
ding l¢nh wait
c6
y
nghia
nhu
sau:
wait
for
time'high;
185
dieu nay
co
nghIa

HI.
chung ta kh6ng
co
chi dinh
wang
minh ve
thoi
gian eho,
Vi
dl,l
ve
Slr
dl,lng cau I¢nh
wait
for,
wait
for
IOns;
Cac hla chQn tren
co
th6
duqc
Slr
dyng dong
thai.
nhu
tcong vi dy
duui day:
wait
on

A, B
until
( x < 10 )
for
10
ns;
diell nay
co
nghIa la b¢
m6
phong
se
eho
khi
c6
thay doi tin hi¢ll
A
hO(lC
B va
se
tiep tyc chi
khi
( x < 10 )
t(!.i
thoi
di~m
xufit hi¢n
sy'
ki¢n,
ho<!.c

eho
toi khi 10 ns da troi qua.
Trong qua tclnh
m6
hinh hoa
Im,lch,
l¢nh
wait
co
tht' dtrqc dung
t1e
thief
J(tp
dong ho cho
che
d¢
dong
b(>,
Trong
cac
rna
hinh thiet k6 bang
ngan
ngfr
VHDL.
J¢oh
wait
ogling
qua
tdnh

thl!C
hi~n
cho
lui xuat hi¢n
suiYn
dutmg
ho~c
suiJn
am
lren duemg tin hi¢u.
Vi
dy, khi
rna
hinh
hoa
phan tir
triga
D
lam
vi¢c
trang
che
d¢
dong b¢
thea
suan
duong, chung ta
co
the'
nh(tn thrqc

dm,lI1
chuong
tdnh
VHDL
nhu
sau.
entity
D_FF
is
port
(eLK:
in BIT;
D:
in BIT; Q: bulTer
BIT);
end
D_FF;
architecture
Behavior
of
D_FF is
begin
process
wait
until
CLK'evcnt
and
CLK
= ' 1
';

Q<~D;
end
process;
end
Behavior;
10.
Phcp
gl)i
chuang
trinh
con
va
I~nh
return
Trong
ngan
ngiJ
VHDL
co
hai
d~ng
chuang
trinh con:
186
Thu
tl,lc:
procedure
co
th~
tni.l:;ti

nhieu gia trj:
Ha111:
function chi
tnt
l~i
mQt
gia trj va co th6 tham gia vao cae
bi{;u
thue.
Cau l¢nh
return
dung de ket thlic
hO<;l.1
dQng
eua cae clllrtmg
tdnh
can
va
chi duqe
Slr
dl.mg
trang
h~un
hO~IC
thu
tL,lc.
D6i voj ham,
Sl.1
co
m,~t

eua
l~nh
return
la
bal bu()e con trong thu
tL,lC
thl khong bat huge. L¢nh
return
co
diu
truc eu
phap
Bhu sau:
§6.6.
Cac
call
true
song song
Trong ngon
ngu
VHDL,
1119t
kicn true c6 the ehua m¢t
ha~c
nhieu ci.k
eau true
song song. Moi eau trlie song song xae dinh
Jl1~)t
Jon
vi

tinh toan
baa
gom
cae
thaa
tae JQe tin hi¢u,
thl,l'e
hi¢tl eae tinh tmin
\r~n
cae
gia
tr~
tin
hi~u
va gan nhung gia
Iri
tlnh
dLIqc
eho
tin
hi~u
ra. Cac cau true song song
xae
dinh
cae thanh philn va cae qua
tdoh
lien ket nhung thilnh phan
d6
bttng
nhilng cau true va hanh vi

eua
cae
thl;Ic
the.
Cie
diu
true song song se duqe
thl;Ie
hi~n
dong thai trong qua trlnh mo phong khong
pJW
thU(lC
VtlO
Ir(l\
II!
xuat hi¢n eua chung Irong kien true.
Trong ngon
ngu
YHDL
e6 cae eau true song song sau:
Qua
trlnh process;
Cae phcp
grin
tin hi¢u song song;
Phcp gan tin hi¢u eo dieu
ki~n;
Phcp gan tin hi¢u eo
Jl!a
eh(:m;

Khoi;
Phep
gQi
chuang
tdnh
con song song.
1.
Cac
qua
trinh
process
Qua
trlnh tinh loan process duqe
1<).0
thanh tll
m()1
li!-p
hqp cae cuu l¢nh
tufin
II!.
Tal d cae qua trlnh process
Iml1g
111(H
Ihicl
ke
duqe
Illlfc
hi¢n
m91
each song song. Tuy

v~y,
t;:ti
1119t
thai
diem
xae djnh chi co
111¢1
cau I¢nh
187
tuAn tt!
dUQ"c
tlwc hi¢n
trong
moi
qua
trlnh
process.
M<.)I
quit tflnh
process
lien kct voi phan
eon
h.ll
eua
thlet ke'
thong
qua
cae
thao tac
dc:)C

ciie giil trj tit
dc
tin hi¢u d:iu \'iI0,
cUc
c6ng
dU"9"e
khai
bao
ngoili
qUii
lrlnh
ho(1C
ghi gia tri
vito eac tin hi¢u,
cong
06.
M¢t
qua
trlnh t[nh
toan
process
dUQ"c
rn6
Iii theo
quy
tac
cu phiip sau:
[<
11/1(/11
>:]

proccss
[«
donI! sdch ctic tin
hi~;11
{(Ie
J()J/g >))
1<
pll(lllJlwi_lhlo > I
bq!;in
1<
/11111
_tllclll_/l/ > J
end
process
[<
I1hiln
>];
< pll(ln
Jlwi
_btio
>
oinh
nghia
cac
doi
tlIQ"ng
ton
{<.Ii
el,le
b6

Hung
process
ban
gom:
- Cac khai
ban
bien, khai
baa
hang,
khai
baa
kitu,
kieu
eon;
-
Than
chvang
trlnh
can,
khai
baa
cae
bi~t
danh.
lu~t
use.
Neu
qua
trinh
chua

<
d(JII"_s(irll_c6c_lfl1_hi~;/{_tdc_J(Jl1g
> thi
ILk
06
qua
trinh nay se
tuang
ttf
nhv
qua
trinh
kh6ng
chua
danh
sueh
tin hi¢u
tac
d¢ng
nhung
li;li
chua
l¢nh wait a
v~
tri cau I¢nh
cuoi
cling
trong
qua
trlnh:

wait on < dal1it _"'rlch _ c(/c_till_hi¢ll_t(lc_d()/lg
>;
Nhung
qua
trinh
d6
kh6ng
can
c6
sl!
xuat
hi¢n
tuang
minh
eua
I¢nh
wait.
Vi¢c thvc hi¢n
mqt
qua
trlnh
proccss
baa
g6m
vi¢c thtfc hi¢n
l~p
h.ll
dc
c[iu true
wan

ttf eilIIa
ben
trang
than
qua
trinh. Sau khi c,lu l¢nh tu,1n ttf
cu6i
cling
dugc
tht!c
hi~n,
\'i¢c
md
ph6ng
qua
trlnh
se
dUQ'c
bAt
dau
I\li
tll C[IU l¢nh
twin
tl,f
dau
tien
eua
qua
trlnh.
Dieu

nay
lam
cha
vi~e
1116
ph6ng
hm.it
d(mg
cua
qua
trlnh
giong
nhll Ill')t
vong
Iij.p
vo
hi 1ll
baa
g()m tat d cac
du
l¢nh
tWIn
tV
bcn
trong
qua
trinh. Vi¢e thtfc
hi~n
m6
phong

qua
trinh
process
e6
the
bi
dung
Ii.li
bang Cil.U l¢nh wait
va
co
th6 dl1gc kich ho;;tlI;;ti khi xu[it hi¢n
sl! ki¢n
trcn
cac
duang
tin
hi~u
trong
danh
such tIn hi¢u hic
o¢ng.
Chung
ta
hay
xet
vi
dl,l
mb
r,lnh hoa b')

ma
hoa
8~3.
Qua
trlnh bi6u
oien
b¢
ma
hoa
nay se
c6
danh
sach
tin
hi~u
tac
d¢ng
g6m
cae
tin hi¢u y I, y2, y3, y4, y5,
y6, y7,
Dicu
nay
eGng lUang
duang
voi
m<.)t
qua
trl11h
khong

c6
oanh
sach
tfn
hi~u
tac
d¢llg
nhung
chua
cau
l¢nh:
188
wait
on
y I. y2, )'3, y4, yS. y6, y7;
t<.li
V!
trl cftu I¢nh cuoi cimg trang
4U;'\'
trlnh.
BQ
ma
haa
8
->
3
duqc
111(1
t,'l
bang

dm.1l1
ehu'ong trlnh
VHDL
duai
day:
entity
Encoder is
port
(yl.
y2, y3. y4, yS, y6, y7: in BIT;
Vec:
out
BI1''-VECTOR ( 2
downto
0));
('nd
Encoder;
architecture
Behavior
of
Encoder is
hq!;in
process(
y
I,
y2, y3, y4. y5. y6. )'7)
begin
if(
y7
~

'1')
then
Vee
<~
"III";
clsif"( y6
~'I'
)
then
Vee
<~
"110":
elsif ( y5 = '1' )
then
V cc
<=
"
JO
1
";
elsif ( y4 =
'1'
)
then
Vee <= "100";
elsif(
y3
=
'1')
then

Vec <=
"all
";
elsif(
y2 =
'I')
then
Vee <= "010";
elsif(
)'"1
=
'I')
then
Vee
<=
"001";
else Vee <= "000";
end
if;
end
prol'css;
end
Bcha\'ior;
Chung
ta xct
111Qt
VI
d~
ve
51!

tuang
tac
giua
hai qua trinh. d
dfly
chung ta
co
Il1Qt
qua trtnh
gt'ri
thong
tin va
qm!.
tr"inh
thu
hai nh(lll thong tin.
Qm\.
trlnh glfi
thdng
lin
co
danh
soiell
tin hi¢u tae dQng
g6m
hai tin hi¢u
CLK
\,~l
Ack. Qu.i
trlnh

nh(Ul
e6
hai tin hi¢u trong
danh
sach
tin hi¢u
lac
dC)ng
eLK
V~l
Ready.
Hai qua
trinh
nilY
dong
b(l
hoa
ho~t
dQng
cua
chung
bAng
l¢nh
Ack
vit
Ready.
DOi.~n
chlIang trlnh
VHDL
dlIai day

m6
ts.
hm.H
dQng ella hal
qua
Irlnh n6i tren.
11-)9
190
entity
HandShake is
port(
eLK
: in
IllT:
DIn : in integer;
DOue
out
inte~cr
);
end
IlandShakc;
Data·
in
Process
A
-
Ready
Data
Process
out

-
•
B
ACK
-

HLnh
6.12.
},if)
hlnh
tLrOng
tac
gWa
hai
qua tdnh proc('ss.
architecture
Protocol
uf
HandShake is
signal Ready.
Ack:
nIT;
signal Data: integer;
begin
Send: process
begin
Ready
<;::::'
I';
Data

<:::::
DIn;
wait until CLK'cvent
and
CLK
:::::
'I'
and
Ack
:::::
'1';
Readv
<==
'0'·
. .
w'lit
until
CLK'event
and
CLK
==
'1'
mul
Ack
==
'0';
end
process Send;
Receive:
prucess

begin
Ack
<~
'0';
wait until CLK'evcnt
and
CLK
==
'\'
and
Re:'ldy
==
'\
';
DOut
<=
Data;
Ack<=='J';
wait
until
eLK'event
and
CLK
==
'I'
and
Ready = '0';
end
process Receive;
end

Protocol;