Điện Tử - Cơ Sở Thiết Kế Mạch - Design Trên Máy Tính (Phân 2) part 9 ppsx

begin
{< l¢nh_tl/(ll1_W
>}
end
[< ten JhJ((/!1ti_fn'llhJol1
>1;
Vi
dy
sau day eho fa thay
ma
tti
ella
th,1n
chuang trlnh con. Chu y rang. khi
g9i ham function, phcp gqi ham
se
b!
ng.it khi thl!c
hi~n
den
cflu
l~nh
return.
Cau
l~nh
return
xac
dinh gia
tfi
tra
l<;ti

cho phep g9i chuang
Trinh
can. Vi
ely,
Funtion lncrementer ( Count: integer)
return
integer
is
variable
Temp:
intcger
;
bcgin
if ( Count
>=
255 )
then
Temp
:=0;
else
Temp := Count + 1 ;
end
ir;
return
( Tcmp
);
end
Incrementer;
Khi
g9i

chuang
Trinh
can, cac doi luqng thl!c
te
wang
u-ng
voi tham so
hlnh thue lop
variable
pMi
la eac hien; wang
u-ng
voi lop
constant
phai la
hang so
ho~c
bieu thuc
va
tu{mg
ung voi
lOp
signal phai
Iil
tin
hi~u.
Ok
hang so va bien duq'c
truy~n
thea gia tr!, con tin

hi~u
duq'c
truy~n
thea dja
chi. Do do doi voi
lOp
doi tlIq'ng tin
hi~u
thl
mQi
tae d¢ng len tham so truyen
vao than
chuang
Trinh
can cling chinh
Iii
tac d¢ng
(fI!C
tiep len tin
hi~u
dUQ'c
truyen vao. Chung ta hay xet
vi
d1,l
chuang
Trinh
con sau:
198
Vi
d~l,

procedure
Send ( signal CLK: BIT ; Data: integer;
begin
signal
Ack: BIT; signal Ready:
out
BIT;
signal Wire:
out
integer)
is
wait
until
( CLK'event
and
CLK = '1'
and
Ack =
'1"
);
wire
<= Data;
Ready
<=
'1
';
wait
until
(elK'evcnt
and

eLK
=
'I'
and
Ack
~'l'
):
Ready <= '0';
cnd
Send;
2.
Cae
ham
quyet
d~nh
Cluing ta bittt d.ng, moi
tIn
hit?u
deu
XUilt
piull ttl
mt)1
n,gu(lIl.
,'\l6i
each
kiuic la moi
lill
hj~u
c6
mc)t

di~u
khi~n.
Trong
nhi~u
truang
ILl/p.
VI
dl,!
nlm
khi
cae
duang
tIn hi¢u
bi
ch(lp
l~L
tin hi¢u
eli
ra
kh6i nut
ch~lp
~C
du'<,1c
H~ng
hqp ttl cae tin hi¢u
di
V~IO
nut theo
m(H
iu~t

xac dinh. Trang trliang hqp
nilY,
chung la noi rang
1111
hi¢u
di
fa
khoi
nUt
eh~p
co
nhi~u
ditu
khi6n.
Ng.6n
I1gfr
YHDL cho
plH~p
chung ta c6
th~
xic
dinh
ca.c
lin
hi~u
xuii! phat
Ill'
nhieu
nguon neu
su-

dl,log
nhung ham quyel djnh. Nhung ham quyct dinh
nilY
dung
de
xic
dinh gia
tI"!
cua
duo-ng
tin hi¢u tll nhilng gia trj
nh~n
duqc
III
nhi~u
nguon dicu khi6n. Y i
dl,!,
Qua trinh i
Tin hieu
Ham quyet
dinh
Tin
hll3U
(
Q""ieh
k

Qua
trinh j
Tin hieu

Tin hi$u
lIinh
6.13.
Sd
do hallh
vi
clla
cae
qua trlnh sinh ra tin hieu co nhicu dieu khie'n.
Trong vi
dy.
nay,
d.
hai
qua
trlnh process i
va
prol·l:.~.
j cung
di~u
khi~n
mt)t tin hi¢u, do
do
chung ta can c6 ham quyet dinh
dt
xae djnh
giri
tr!
cho
tfn

hi¢u
nhi.~n
dlI,!C.
Doi voi qua Idnh mo phong, cae ham guyet dinh
(.;0.)
the ,,'
mQi
ham bao
gum cae cbuang trlnh viel tren ngon ngil YHDL. Trang
nhLrng
m~ch
thtJc.
ket qua
el\a cae ham quyet
d~nh
la lien ket cae tin hi¢u
va
cung cho qua
lTI¢t
phan tu logic
d~c
bi¢t c6 m¢t dau
Ca.
Trang
ky
thu~t:
chi co m¢t so
gi{ji
hqn
199

cae Trong cae phall
eUng
chi c6
mQt
vai
ki~u
thl,Ic
hi¢n cae ham quyct
r.1jnh
nhl1
lien ket
d~ng
Or, lien ket
d,-~ng
And
ho~e
lien ket
d~ng
ba
tr~ng
thii
( hinh 6.14).
Lien ket
d~ng
Or
Lien ket
d,~mg
And
Sa
tr~ng

thai
Uinh 6.14. Cac bieu (lien phan
tung
Clla
de
hinn quyct d!nh: harn quyc't dinh
d,!-ng
Or.
dang
And
viI
ba
trang
IIia1.
Cac tin hi¢u dugc cac ham quyet dinh
t<~o
ra
neu khai bao cua tin
hi~u
chua d cac ham quyet dinh
ho<!-c
khai bao
ki~u
can eua tin
hi~u
chua
h~l.In
quyet djnh. Vi dy,
signal NODE: WIRE_AND
BIT:

subtype
RESOLVED_STD
is
WIRE_OR STD_ULOGIC:
Trang vi dy nay, khai bao thu nh[\t cho chung ta lhay tin hi¢u NODE la tin
hi~u
dugc xae dinh \'6i ham quyct dinh la WIRE_AND. Moi khi xual
hi~n
sl,I
ki~n
tren duang tin hi¢u NODE, ham WIRE_AND duqc
gQi
va
tnt li.li gia
II"!
ki~u
BIT -
l.1
gia trj cua
t[n
hi¢u NODE. Khai baa thu hai xae djnh
kit!u
con duqc quyet dinh RESOLVED_STD.
C<ic
tin hi¢u
dW1C
khai bao
thuQc
ki~u
RESOLVED_STD

Itt
nhung tin hi¢u
dU'qc
quyet dinh. Duai day chung
ta thay each de
x<ic
dinh
va
sir
dl:mg
dc
tin hi¢u duqc quyet djnh:
- Xac dtnh
ki~u
tin
hi¢u
( neu can thiet
):
- Xac djnh ham quyet dinh. Ham nay sc
nh~n
cac lin
hiGu
vao
va
tra
I'!.i
tin hi¢u
thuQe
kieu
dii

dUQ'e
xae dinh;
- Khai baa kieu con cua
ki~u
tin
hi~u
kern v6i ham quyet djnh;
- Khai bio
va
Slr
dt:lI1g
cac tin hi¢u dugc quyct djnh.
Trong vi
dt,l
dttai day. chung ta thay tin
hi~u
Z
dttCJe
khai bao
Itt
thuQc
ki~u
dttqc quyet d!nh WIREOR_STD, trong d6
h~l.ln
quyct d!nh cua
kitu
tin hi¢u
la WIRE_OR.
Trong kien true, chung ta co
hai

phep gan tin hi¢u dong thoi.
Cii
hai phep gan deu gan gia trj cho tin hi¢u
Z.
Nhtt
v~y
tin hi9u Z
se
nMn
200
gia tr\
dl1qc
x<ic
d,nh
qua
phep
lOan
or
giil:a
hai dau vao
cua
ham
quyet
djnh:
(
[j
and
12
)
vii

(
13
xor
14
).
Vi
dl,l.
architecture
Resolved
ArchofWOR
is
begin
runction
WIRE_OR( Din: in
STD_UU1GIC
VECroR
)
return
STD_ULOGIC
is
begin
return(
Din( 0 )
or
Din( 1
»;
end
WIRLOR;
subtype
WIREOR_STD

is
WIRE_OR STD_ULOGIC;
signal
II,
12, 13,
14:
STD_ULOGlC;
signal
Z:
WlREOR_STD;
Z
<=
II
and
12;
7.
<=
13
xor
14;
end
WOR;
Cac goi
chuang
trlnh STD_LOGIC_1164
cua
tim
vi~n
IEEE
chua

cae
kieu
dl1
li¢u duqc quyct
o,nh
la
SID_LOGIC
va STD_LOGIC_
VECIOR.
D<~ng
quyc"t
d(nh
cua
kitu
STD_LOGTC lit
d<;lng
quyet ujnh
thea
ba
tn~ng
thai. Cae tin hi¢u
co
nhieu nguon uleu
khitn
se
duC}c
gan
eho
tin hi¢u -kitu
STD

_LOGIC
V~l
gia tri
duqc
quyct d(nh boi
cae
ham
ba
tr<;tng
thai.
3.
Cac
g6i
ChUling
trinh
Cac
kitu
dil:
li¢u, hang
s6
va
chuang
trlnh
can
co
the:
duqc khai hao ben
~ck~~o~~~~t~_c~ck~~.Qc~
baa
nay

ta
cl,lc
b~
nang
nhil:ng kien truc
wong
ung
va thlfc
thc'
kluic
kh6ng
the
truy
e~p
t6i nhung doi tuqng do. Tuy nhlen
traog
nhi~u
truong
hqp
nhung
kie"o
truc khac nhau
cung
co
the phai chia
sf:
nhung
doi
tuqng
chung

nao
do.
Gic
goi
chuong
trlnh ( Package,> )
trang
ngoo
ngu
VHDL
eho
phep
cluing ta thl!c
hi~ll
cae
khai
baa
chung
:ho
nhicu thlfc
tM
khac
nhau. MQt
goi
chuong
trinh
eua
ngon
ngu
VHDL

dugc
biofu
uien thanh hai phan:
ph~n
khai
baa
goi va than
cua
goi.
201
Phan khai hao goi m6 ta cae giao
di-<?n
cua goi va co cau true eu
ph{Lp
nhl1
sau,
package
< /('IlJ/la_g/ji > is
{< cdc_ khm _ h(l()
_lltl/O(
WJ/
> I
end
[< lell_g6i
>J;
Cae khai b,lo
ti1U¢e
g6i co
th~
la

cae :
Khai
bao
ki~u,
kitu
con, tin hi¢u, h,ing, bi¢t
Janh:
Khai bao thanh phan, chuang trlnh
can;
Lu(tt use:
Va
c6
the
ehCra
d
de
package khae.
Otc kiwi bao tin
hi~u
trong g6i
t~o
ntn
m<)t
so
van
d~
trang qua trinh
tong
hqp
m~lCh

b6i
\'1
Ill¢t tin
hi~u
kh6ng
th~
philn phoi
giO'a
hai
thl!C
the.
Cl.ch giai quyet thong d\lng van de nay
la
tin hi¢u
sf:
dL!(l'C
khai baa
nhu
l11<)t
tin hi¢u cuc h9. Noi each kh,ic, neu hai
thl!C
the
SLr
dl;!ng
cung
m<)t
tin
hi~u
lrong gol, moi
thl!C

the sc
nh~n
duqc
mOt
phicn
bun
sao chep CLIa tin
hi~u
nay.
Vi
dl;!
\'6 khai bao goi:
library
IEEE
use IEEE.NUMERIC_IJITaU;
package
Watch_Pkg
is
subtype
Mouth_type is
interger
range
0
to
12;
subtype
Date_type is
intergcr
range
0

to
3
!:
subtype
BCD4_type is
unsigned
( 3
down
to
0
);
subtype
BCDS_type is
unsigned
( 4
downto
0
);
constant
BCDS_I: BCDS_lype
:~
B"O_OOOI
";
constant
BCDS_7: RCDS_lype
:~
B"O_OOOI
";
function
.BCD_Inc ( L : in

BCD4_type)
return
BCD.'i_type:
end
Watch_Pkg:
Than clla
l11¢t
g6i xac djnh
dc
h~ll1h
vi
cua g6i. Than cua
mQt
g6i iu6n
ph,ij
cung
len voi khai
h,}o
goi. Phan than g6i duqc hat
d,lU
b6i
Ill:
khoa
package
body.
Cae
thong tin trong trong
thin
cua goi kh6ng
th~

nhin th,iy
202
<luqe
tu
cae thiet
ke'
ho~e
tlwe the sir
dl;lng
goi do.
Nhu
v~y
IU
cac thiet
ke
va
eae thvc the chung
la
chi co the truy
c~p
tai cac d6i lUang trong g6i thong
qua cae giao di¢n duqc
xUc
<l!nh
trang philn khai bao g6i
ma
khong
the'
can
thi¢p trvc tiep vao ben trung goi. Noi

mQt
dch
kh;k goi
hi.
mQt
hQp
den
vai
cae
giao di¢n
<luqc
dUa
ra trung phan khai bao. Than
cua
goi duqc
1116
tii
thea
quy
tic
cu phap nhu sau:
package
body
< len
nla
g/n > is
{ <
cacJhm
_/)(10
_tl

ollg_t}uln
grJ/
>}
end
[<
thl_CJ/(lj;6i
>J;
Trang
phan
khai bao trong than goi co
th~
chua eac:
Khai ban kieu, kie'u con,
h~ng;
- Than ehuOllg t lnh can;
-
~u~t
usc.
Vi
dl,!
<luai
day
cho
chung
la
thay
vi~c
m6
tii
than cua goi trang ngon

ngu
VHDL:
package
body
W A
TCH]KG
is
function BCD_INC ( L: in BCD4_
TYPE)
return
RCDS_ TYPE is
variable
VI,
V2,
V:
BCDS_TYPE:
begin
V I
:=
L + BCD5 - I :
V2
:=
L + BCD5 - 7 ,
case
V2(
4 )
is
when
'0'
=>

V:=
VI;
when 'J' => V := V2;
end
case;
return
( V
);
end
BCD_INC,
end
WATCH_PKG,
Cae phdn
tu
duqc m6 ta trang
pha.n
khai bao g6i
kh6ng
the nhln
IhAy
duqc
mQt
each
tv
dQllg
tu
cac thu
\'i~n
khac.
Lu~t

usc dung
tmae
mQI
dan
\"!
chuang
tdnh
se lam cho lal
ca
cac pl,3n
tu
trang
phil.Il
khai
hi.lO
goi
e6
the'
dUQ'c
lruy
Ci)p
tu
dan
vj
chuang trlnh d6. Vi
dl,!,
gi;i thiet rang, goi chuong
20]
ldnh
WATCH_PKG neu tren

dUCK
bien dich va dua vao thu vi9n
MY_LIBRARY.
De:
co
the:
si'r
dl,lng
cac khai bao trong goi WATCH_PKG,
chung
ta can dua chung vao thu vi¢n
chuang
tdnh
hi~n
Ihai
SLr
dl,lng
dot~n
l~nh
sau:
library
MY_LIBRARY;
lISC
MY_LIBRARY.
WATCH]KG.all;
HQi
dong
ChLl<1n
hoa IEEE xac djnh hai
thu

vi¢n
cho
ngon ngi1
VHDL
ia
STD va
IEEE. Moi thu vi¢n chua
rnQt
so
goi nhu:
STANDARD
va TEXTIO doi vai
thL(
vi¢n STD. Goi
STANDARD xac
djnh cac kieu
du
li~u
quan tn?ng
nhu
integer,
boolean, BIT

STD_LOGICI164, NUMERIC_BIT,
NUMERICSTD
doi
,oi
Ihu vi¢n IEEE. Cac goi nay chua cac
kie:u
va nhfrng

haITI
quan
tr",ng
eha
qua trinh tcing
hqp
va rnb phong bang ngbn ngiJ
VHDL
Trong
chuang
nay c1lling ta
d1t
khao sat nhung
d~c
die:m
co
ban eua ngbn
ngu
VHDL
-
lTI¢t
ngon
ngu
rno
ta
ph<1n
cling dien hloh. Ngon
ngu-
nay
dUQ'c

dung
de:
1110
hinh hoa
m~ch
trong cbng ngh¢ thiet
ke,
ehe
h.\O
l11<;lch
voi
d¢
tich h0P eao va sieu cuo. Nhilng
Ihinh
phan chfnh
eua
ngon ngil
nhu
cac
l¢nh
tu.}n
IL!,
cae l¢nh song song,
cUc
chuang
tdnh
con, cac
phu"Cing
pluip
1116

tA
thL!C
the va phuong phap
lu~n
bicu dien
l11<;tch
theo cau chue, hanh
vi
hO~lC
theo dong dfr li¢u
drr
dUQ'C
de
c~p
t6i. Trong chuang tiep theo chung ta
<;Lr
d'-:lng
ngbn ngil VHDL de Xi)Y
d~rng
dc
mb
hinh nhilng
In' lch
logic
cel
ban. '
204