Design and Implementation of VLSI Systems_Lecture 07: Sequential Circuit Sign potx

Design and Implementation
of VLSI Systems
Lecture 07
Thuan Nguyen
Faculty of Electronics and Telecommunications,
University of Science, VNU HCMUS
Spring 2011
1
LECTURE 07: SEQUENTIAL CIRCUIT
DESIGN
Introduction
1
Circuit Design of Latches and Flip-flops
2
Sequencing Static Circuits
3
2
Static Sequencing Element Methodology
4
Synchronizer
5
LECTURE 07: SEQUENTIAL CIRCUIT
DESIGN
Sequencing
1
Sequencing Element Design
2
Sequencing Methods
3
3
Introduction

1
Circuit Design of Latches and Flip-flops
2
Sequencing Static Circuits
3
Static Sequencing Element Methodology
4
Synchronizer
5
SEQUENCING
 Combinational logic
 Output depends on current inputs
 Sequential logic
 Output depends on current and previous inputs
 Requires separating previous, current, future
 Called state or tokens
 Ex: FSM, pipeline
CL
clk
in out
clk clk clk
CL CL
PipelineFinite State Machine
4
SEQUENCING (CONT.)
 If tokens moved through pipeline at constant
speed, no sequencing elements would be
necessary
 Ex: fiber-optic cable
 Light pulses (tokens) are sent down cable

 Next pulse sent before first reaches end of cable
 No need for hardware to separate pulses
 But dispersion sets min time between pulses
 This is called wave pipelining in circuits
 In most circuits, dispersion is high
 Delay fast tokens so they don’t catch slow ones.
5
SEQUENCING OVERHEAD
 Use flip-flops to delay fast tokens so they move
through exactly one stage each cycle.
 Inevitably adds some delay to the slow tokens
 Makes circuit slower than just the logic delay
 Called sequencing overhead
 Some people call this clocking overhead
 But it applies to asynchronous circuits too
 Inevitable side effect of maintaining sequence
6
LECTURE 07: SEQUENTIAL CIRCUIT
DESIGN
Sequencing
1
Sequencing Element Design
2
Sequencing Methods
3
7
Introduction
1
Circuit Design of Latches and Flip-flops
2

Sequencing Static Circuits
3
Static Sequencing Element Methodology
4
Synchronizer
5
SEQUENCING ELEMENTS
 Latch: Level sensitive
 a.k.a. transparent latch, D latch
 Flip-flop: edge triggered
 A.k.a. master-slave flip-flop, D flip-flop, D register
 Timing Diagrams
 Transparent
 Opaque
 Edge-trigger
D
Flop
Latch
Q
clk clk
D Q
clk
D
Q (latch)
Q (flop)
D
Flop
Latch
Q
clk clk

D Q
clk
D
Q (latch)
Q (flop)
8
LATCH DESIGN
 Pass Transistor Latch
 Pros
+ Tiny
+ Low clock load
 Cons
 V
t
drop
 nonrestoring
 backdriving
 output noise sensitivity
 dynamic
 diffusion input
D Q

Used in 1970’s
9
LATCH DESIGN
 Transmission gate
+ No V
t
drop
- Requires inverted clock

D Q


10
LATCH DESIGN
 Inverting buffer
+ Restoring
+ No backdriving
+ Fixes either
 Output noise sensitivity
 Or diffusion input
 Inverted output
D


X
Q
D Q


11
LATCH DESIGN
 Tristate feedback
+ Static
 Backdriving risk

 Static latches are now essential
because of leakage





QD
X
12
LATCH DESIGN
 Buffered input
+ Fixes diffusion input
+ Noninverting


QD
X


13
LATCH DESIGN
 Buffered output
+ No backdriving


 Widely used in standard cells
+ Very robust (most important)
- Rather large
- Rather slow (1.5 – 2 FO4 delays)
- High clock loading


Q
D

X


14
LATCH DESIGN
 Datapath latch
+ smaller
+ faster
- unbuffered input




Q
D
X
15
FLIP-FLOP DESIGN
 Flip-flop is built as pair of back-to-back latches
D Q




X
D





X
Q
Q




16
PULSE GENERATOR
17
ENABLE
 Enable: ignore clock when en = 0
 Mux: increase latch D-Q delay
 Clock Gating: increase en setup time, skew
D Q
Latch
D Q
en
en


Latch
D
Q

0
1
en
Latch
D Q

 en
D
Q

0
1
en
D Q
 en
Flop
Flop
Flop
Symbol Multiplexer Design Clock Gating Design
18
RESET
 Force output low when reset asserted
 Synchronous vs. asynchronous
D




Q
Q




reset
D







Q


D
reset


Q


D
reset
reset


reset
Synchronous Reset Asynchronous ResetSymbol
Flop
D Q
Latch
D Q
reset reset
 



Q
reset
19
SET/RESET

 Set forces output high when enabled
 Flip-flop with asynchronous set and reset
D






Q


reset
set
reset
set
20
LECTURE 07: SEQUENTIAL CIRCUIT
DESIGN
Sequencing
1
Sequencing Element Design
2
Sequencing Methods

3
21
Introduction
1
Circuit Design of Latches and Flip-flops
2
Sequencing Static Circuits
3
Static Sequencing Element Methodology
4
Synchronizer
5
SEQUENCING METHODS
 Flip-flops
 2-Phase Latches
 Pulsed Latches
Flip-Flops
Flop
Latch
Flop
clk

1

2

p
clk clk
Latch
Latch


p

p

1

1

2
2-Phase Transparent Latches Pulsed Latches
Combinational Logic
Combinational
Logic
Combinational
Logic
Combinational Logic
Latch
Latch
T
c
T
c
/2
t
nonoverlap
t
nonoverlap
t
pw

Half-Cycle 1 Half-Cycle 1
22
TIMING DIAGRAMS
t
pd
Logic Prop. Delay
t
cd
Logic Cont. Delay
t
pcq
Latch/Flop Clk->Q Prop. Delay
t
ccq
Latch/Flop Clk->Q Cont. Delay
t
pdq
Latch D->Q Prop. Delay
t
cdq
Latch D->Q Cont. Delay
t
setup
Latch/Flop Setup Time
t
hold
Latch/Flop Hold Time
Contamination and Propagation Delays
23
Aperture = t

setup
+ t
hold

TIMING DIAGRAMS (CONT.)
24
Flop
A
Y
t
pd
Combinational
Logic
A Y
D Q
clk
clk
D
Q
Latch
D Q
clk
clk
D
Q
t
cd
t
setup
t

hold
t
ccq
t
pcq
t
ccq
t
setup
t
hold
t
pcq
t
pdq
t
cdq
MAX-DELAY: FLIP-FLOPS
F1
F2
clk
clk clk
Combinational Logic
T
c
Q1 D2
Q1
D2
t
pd

t
setup
t
pcq
 
setup
sequencing overhead
pd c pcq
t T t t  
25