Design and Implementation of VLSI Systems_Lecture 06: Circuit characterization and performance estimation ppt

Design and Implementation
of VLSI Systems
Lecture 06
Thuan Nguyen
Faculty of Electronics and Telecommunications,
University of Science, VNU HCMUS
Spring 2011
1
INTRODUCTION
 The delay of a logic gate:
C: load capacitance
t ∝
𝐶
𝐼
∆𝑉 I: output current
∆𝑉: output voltage swing
2
 nMOS provides more current than pMOS for the same size
and capacitance
 Static CMOS requires both nMOS and pMOS on each
input.
 All the node voltages in static CMOS must transition
between 0 and V
DD
 propagation delay + power
consumption.

 Circuit families
LECTURE 06: CIRCUIT CHARACTERIZATION &
PERFORMANCE ESTIMATION
Static CMOS

1
Ratioed Circuits
2
Dynamic Circuits
3
Pass-transistor Circuits
4
3
LECTURE 06: CIRCUIT CHARACTERIZATION &
PERFORMANCE ESTIMATION
Static CMOS
1
Ratioed Circuits
2
Dynamic Circuits
3
Pass-transistor Circuits
4
4
OUTLINE
 Bubble Pushing
 Compound Gates
 Logical Effort Example
 Input Ordering
 Asymmetric Gates
 Skewed Gates
 Best P/N ratio
5
EXAMPLE 1
module mux(input s, d0, d1,

output y);

assign y = s ? d1 : d0;
endmodule

1) Sketch a design using AND, OR, and NOT gates.
D0
S
D1
S
Y
6
EXAMPLE 2
Y
D0
S
D1
S
7
module mux(input s, d0, d1,
output y);

assign y = s ? d1 : d0;
endmodule

2) Sketch a design using NAND, NOR, and NOT
gates. Assume ~S is available.
BUBBLE PUSHING
 Start with network of AND / OR gates
 Convert to NAND / NOR + inverters

 Push bubbles around to simplify logic
 Remember DeMorgan’s Law
Y Y
Y
D
Y
(a) (b)
(c) (d)
8
EXAMPLE 3
module mux(input s, d0, d1,
output y);

assign y = s ? d1 : d0;
Endmodule

3) Sketch a design using one compound gate and one
NOT gate. Assume ~S is available.
Y
D0
S
D1
S
9
COMPOUND GATES
 Logical Effort of compound gates
A
B
C
D

Y
A
B
C
Y
A
B
C
C
A B
A
B
C
D
A
C
B
D
2
2
1
4
44
2
2 2
2
4
4 4
4
g

A
= 6/3
g
B
= 6/3
g
C
= 5/3
p = 7/3
g
A
= 6/3
g
B
= 6/3
g
C
= 6/3
p = 12/3
g
D
= 6/3
YA
A Y
g
A
= 3/3
p = 3/3
2
1

YY
unit inverter AOI21 AOI22
A
C
D
E
Y
B
Y
B C
A
D
E
A
B
C
D E
g
A
= 5/3
g
B
= 8/3
g
C
= 8/3
g
D
= 8/3
2

2 2
22
6
6
6 6
3
p = 16/3
g
E
= 8/3
Complex AOI
Y A B C
Y A B C D
 
Y A B C D E  
YA
10
EXAMPLE 4
 The multiplexer has a maximum input capacitance
of 16 units on each input. It must drive a load of
160 units. Estimate the delay of the two designs.
2 2 4
(4/3) (4/3) 16/9
160/9
ˆ
4.2
ˆ
12.4
N
P

G
F GBH
fF
D Nf P

  



  
Y
D0
S
D1
S
Y
D0
S
D1
S
H = 160 / 16 = 10 B = 1 N = 2
4 1 5
(6/3) (1) 2
20
ˆ
4.5
ˆ
14
N
P

G
F GBH
fF
D Nf P

  



  
11
6
6 6
6
10
10
Y
24
12
10
10
8
8
88
8
8
88
25
25
2525

Y
16
16160 * (4/3) / 4.2 = 50 160 * 1 / 4.5 = 36
EXAMPLE 5
 Annotate your designs with transistor sizes that
achieve this delay.
Y
8
8
88
8
8
88
25
25
2525
Y
16
160 * (4/3) / 4.2 = 50
YY
12
INPUT ORDER
 Our parasitic delay model was too simple
 Calculate parasitic delay for Y falling
 If A arrives latest? 2
 If B arrives latest? 2.33
6C
2C
2
2

2
2
B
A
x
Y
13
INNER & OUTER INPUTS
 Inner input is closest to output (A)
 Outer input is closest to rail (B)

 If input arrival time is known
 Connect latest input to inner terminal
2
2
2
2
A
B
Y
14
ASYMMETRIC GATES
 Asymmetric gates favor one input over another
 Ex: suppose input A of a NAND gate is most critical
 Use smaller transistor on A (less capacitance)
 Boost size of noncritical input
 So total resistance is same
 g
A
= 10/9

 g
B
= 2
 g
total
= g
A
+ g
B
= 28/9

 Asymmetric gate approaches g = 1 on critical input
 But total logical effort goes up
A
reset
Y
4
4/3
2
2
reset
A
Y
15
SYMMETRIC GATES
 Inputs can be made perfectly symmetric
A
B
Y
2

1
1
2
1
1
16
SKEWED INVERTER
Transfer characteristics of
skewed inverter
17
o
𝛽
𝑛
𝛽
𝑝
= 1: un-skewed inv
o
𝛽
𝑛
𝛽
𝑝
> 1: HI-skewed inv
o
𝛽
𝑛
𝛽
𝑝
< 1: LO-skewed inv

SKEWED GATES
 Skewed gates favor one edge over another
 Ex: suppose rising output of inverter is most
critical
 Downsize noncritical nMOS transistor




 Calculate logical effort by comparing to
unskewed inverter with same effective resistance
on that edge.
 g
u
= 2.5 / 3 = 5/6
 g
d
= 2.5 / 1.5 = 5/3
1/2
2
A Y
1
2
A Y
1/2
1
A Y
HI-skew
inverter
unskewed inverter

(equal rise resistance)
unskewed inverter
(equal fall resistance)
18
HI- AND LO-SKEW
 Def: Logical effort of a skewed gate for a
particular transition is the ratio of the input
capacitance of that gate to the input capacitance
of an un-skewed inverter delivering the same
output current for the same transition.

 Skewed gates reduce size of noncritical
transistors
 HI-skew gates favor rising output (small nMOS)
 LO-skew gates favor falling output (small pMOS)
 Logical effort is smaller for favored direction
 But larger for the other direction
19
1/2
2
A Y
Inverter
1
1
2
2
B
A
Y
B

A
NAND2 NOR2
1/21/2
4
4
HI-skew
LO-skew
1
1
A Y
2
2
1
1
B
A
Y
B
A
11
2
2
g
u
= 5/6
g
d
= 5/3
g
avg

= 5/4
g
u
= 4/3
g
d
= 2/3
g
avg
= 1
g
u
= 1
g
d
= 2
g
avg
= 3/2
g
u
= 2
g
d
= 1
g
avg
= 3/2
g
u

= 3/2
g
d
= 3
g
avg
= 9/4
g
u
= 2
g
d
= 1
g
avg
= 3/2
Y
Y
1
2
A Y
2
2
2
2
B
A
Y
B
A

11
4
4
unskewed
g
u
= 1
g
d
= 1
g
avg
= 1
g
u
= 4/3
g
d
= 4/3
g
avg
= 4/3
g
u
= 5/3
g
d
= 5/3
g
avg

= 5/3
Y
CATALOG OF SKEWED GATES
20
21
ASYMMETRIC SKEW
 Combine asymmetric and skewed gates
 Downsize noncritical transistor on unimportant input
 Reduces parasitic delay for critical input
A
reset
Y
4
4/3
2
1
reset
A
Y
22
BEST P/N RATIO
 We have selected P/N ratio for unit rise and fall
resistance (m = 2-3 for an inverter).
 Alternative: choose ratio for least average delay
 Ex: inverter
 Delay driving identical inverter
 t
pdf
= (P+1)
 t

pdr
= (P+1)(m/P)
 t
pd
= (P+1)(1+m/P)/2 = (P + 1 + m + m/P)/2
 dt
pd
/ dP = (1- m/P
2
)/2 = 0
 Least delay for P =
m
23
Inverter NAND2 NOR2
1
1.414
A Y
2
2
2
2
B
A
Y
B
A
11
2
2
fastest

P/N ratio
g
u
= 1.15
g
d
= 0.81
g
avg
= 0.98
g
u
= 4/3
g
d
= 4/3
g
avg
= 4/3
g
u
= 2
g
d
= 1
g
avg
= 3/2
Y
Inverter NAND2 NOR2

1
1.414
A Y
2
2
2
2
B
A
Y
B
A
11
2
2
fastest
P/N ratio
g
u
=
g
d
=
g
avg
=
g
u
=
g

d
=
g
avg
=
g
u
=
g
d
=
g
avg
=
Y
P/N RATIOS
 In general, best P/N ratio is sqrt of equal delay
ratio.
 Only improves average delay slightly for inverters
 But significantly decreases area and power
24
OBSERVATIONS
 For speed:
 NAND vs. NOR
 Many simple stages vs. fewer high fan-in stages
 Latest-arriving input
 For area and power:
 Many simple stages vs. fewer high fan-in stages
STATIC CMOS CIRCUIT (REVIEW)
 At every point in time (except during the switching

transients) each gate output is connected to
either V
DD
or V
SS
via a low-resistive path.
 The outputs of the gates assume at all times the
value of the Boolean function, implemented by
the circuit (ignoring, once again, the transient effects
during switching periods).
 This is in contrast to the dynamic circuit class,
which relies on temporary storage of signal values on
the capacitance of high impedance circuit nodes.
25