Design and Implementation of VLSI Systems_Lecture 04: Mos transistor Theory pdf

Design and Implementation of
VLSI Systems
Lecture 04
Thuan Nguyen
Faculty of Electronics and Telecommunications,
University of Science, VNU HCMUS
Spring 2011
1
LECTURE 04: MOS TRANSISTOR THEORY
2
Ideal (Shockley) Model
1
Non-ideal Model
2
DC Transfer Characteristics
3
LECTURE 04: MOS TRANSISTOR THEORY
3
Ideal (Shockley) Model
1
Non-ideal Model
2
DC Transfer Characteristics
3
IDEAL (SHOCKLEY) MODEL
 A silicon p–n junction with no applied voltage.
4
Review: p-n junction
 A p–n junction in thermal equilibrium
with zero bias voltage applied
5

 A p–n junction in
thermal
equilibrium with
zero bias voltage
applied. Under the
junction, plots for
the charge density,
the electric field
and the voltage are
reported.
6
GATE-OXIDE-BODY SANDWICH = CAPACITOR
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
V
g
< 0
(b)
+
-
0 < V
g
< V
t
depletion region
(c)

+
-
V
g
> V
t
depletion region
inversion region
7
Operating modes
• Accumulation
• Depletion
• Inversion
•The charge
accumulated is
proportional to the
excess gate-channel
voltage (V
gc
-V
t
)
NMOS CUTOFF
 No channel
 I
ds
≈ 0
+
-
V

gs
= 0
n+ n+
+
-
V
gd
p-type body
b
g
s
d
8
NMOS LINEAR
 Channel forms
 Current flows from d
to s
 e
-
from s to d
 I
ds
increases with V
ds
 Similar to linear
resistor
+
-
V
gs

> V
t
n+ n+
+
-
V
gd
= V
gs
+
-
V
gs
> V
t
n+ n+
+
-
V
gs
> V
gd
> V
t
V
ds
= 0
0 < V
ds
< V

gs
-V
t
p-type body
p-type body
b
g
s
d
b
g
s
d
I
ds
9
NMOS SATURATION
 Channel pinches off
 I
ds
independent of V
ds
 We say current saturates
 Similar to current source
+
-
V
gs
> V
t

n+ n+
+
-
V
gd
< V
t
V
ds
> V
gs
-V
t
p-type body
b
g
s
d
I
ds
10
THE MOS TRANSISTOR HAS THREE REGIONS
OF OPERATION
 Cut off
V
gs
< V
t
11
o Linear (resistor)

V
gs
> V
t
& V
ds
< V
SAT
= V
gs
-V
t


Current prop to
V
ds
o Saturation
V
gs
> V
t
and V
ds
≥ V
SAT
= V
gs
-V
t

Current is independent
of V
ds
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD
= 2.5V, VT = 0.4V
HOW TO CALCULATE THE CURRENT VALUE?
 MOS structure looks like parallel plate
capacitor while operating in inversion
 Gate – oxide – channel
 Q
channel
= CV
 C = ε
ox
WL/t
ox
= C
ox
WL (where C
ox
=ε
ox
/t
ox
)
 V = V
gc
– V
t

= (V
gs
– V
ds
/2) – V
t
12
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d

C
g
CARRIER VELOCITY IS A FACTOR IN
DETERMINING THE CURRENT
 Charge is carried by electrons
 Carrier velocity v proportional to lateral E-
field between source and drain
 v = μE μ called mobility
 E = V
ds
/L
 Time for carrier to cross channel:
t = L / v
13
I=Q/T
 Now we know
 How much charge Q
channel
is in the channel
 How much time t each carrier takes to cross
14
channel
ox
2
2
ds
ds
gs t ds
ds
gs t ds

Q
I
t
W
V
C V V V
L
V
V V V




  



  


IN LINEAR MODE (V
GS
> V
T
& V
DS
< V
GS
-V
T

)
channel
ox
2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W
V
C V V V
L
V
V V V




  



  



15
Can be ignored for small V
ds
 For a given V
gs
, I
ds
is proportional (linear) to V
ds

IN SATURATION MODE (V
GS
> V
T
AND V
DS
≥
V
GS
-V
T
)
channel
ox
2
2
ds
ds
gs t ds
ds

gs t ds
Q
I
t
W
V
C V V V
L
V
V V V




  



  


16
 
2
2
2
dsat
ds gs t dsat
gs t
V

I V V V
VV



  



 Now drain voltage no longer increases current
pinched off
OPERATION MODES SUMMARY
 
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
VV
V
I V V V V V
V V V V









   








17
β: transconductance parameter of transistor
CURRENT-VOLTAGE RELATIONS

β: transconductance parameter of transistor
W/L: width-to-length ratio

 As W increases, more carriers available to
conduct current.
 As L increases, V
ds
diminishes in effect (more
voltage drop)  takes longer to push carriers
across the transistor  reducing current flow.

18
TRANSISTOR CAPACITANCE
19
 Gate capacitance: to body + to drain + to source
 Diffusion capacitance: source-body and drain-body
capacitances
GATE CAPACITANCE AS A FUNCTION OF VGS
20
QuickTime™ and a
decompressor
are needed to see this picture.
SOURCE/DRAIN DIFFUSION CAPACITANCE
 C
sb
, C
db
 Undesirable, called parasitic
capacitance
 Capacitance depends on area and
perimeter
 Use small diffusion nodes
 Comparable to C
g

 Varies with process
21
Bottom
Side wall
Side wall
Channel

Source
N
D
Channel-stop implant
N
A
1
Substrate N
A
W
x
j
L
S
SUMMARY OF SHOCKLEY MODEL
22
 
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
VV

V
I V V V V V
V V V V








   








for nMOS
for pMOS
n+ n+
p-type body
W
L
t
ox
SiO
2

gate oxide
(good insulator, 
ox
= 3.9)
polysilicon
gate
Covered ideal (long channel) operation (Shockley model) of transistor
LECTURE 04: MOS TRANSISTOR THEORY
23
Ideal (Shockley) Model
1
Non-ideal Model
2
DC Transfer Characteristics
3
IDEAL VS. NON-IDEAL
24
ideal Non-ideal
 Saturation current does not increase quadratically with Vgs
 Saturation current lightly increases with increase in Vds
25
 There is leakage current when the transistor is in cut off
 Ids depends on the temperature