Digital logic testing and simulation phần 5 potx

SEQUENTIAL TEST METHODS
257
conflict. For purposes of illustration we select Y
σ
2
. It requires a D from input V and a
0 from input U.
Table 5.6 is used to justify the D. The column with header D reveals that a D
occurs at the input to Y if V is true while at rest, A, or if it is presently true but toggles
false, T, at the next time frame. Since no cubes exist in Table 5.7 with a T on the out-
put of V, we check entries from Table 5.6 with A and find, by going across to the left,
that they result from intersection with either an A or t on the output of V. From the
D-cubes for V in Table 5.7, V
σ
4
is selected. Finally, in similar fashion, a 0 is justified
on U by means of cube U
α
.
Four cubes have now been identified that extend a sensitized path back from out-
put Z to primary inputs and other elements. Before continuing, we point out that the
sensitized path extends through both logic and time, since the cubes impose switch-
ing conditions as well as logic values. As a result, intersections are more complex
and require attention to more detail than is the case with the D-algorithm. Some
cubes must be intersected in the same time frame, and others, linked by synchronous
switching conditions, are used to satisfy conditions required in the preceding time
frame.
Consider the first D-cube selected, Z
σ
1
. It creates a t on the output of Z by assign-

ing a 1 and a d to the inputs of the AND gate. The 1 is satisfied by assigning a 1 to
input F. The d, which is an asynchronous D, must be justified in the present time
frame. This is accomplished by intersecting Z
σ
1
with the second cube previously
selected, Y
σ
2
. Performing the intersection according to the rules in Table 5.6, we
obtain the following:
The resultant cube applies a 0 to the Set input of flip-flop Y. The fourth cube pre-
viously selected, U
α
, which was chosen to justify the 0 on the Set input, is asyn-
chronously coupled to Y via the unclocked Set input. Therefore, according to the
intersection rules, it must be intersected with the previous result.
The remaining cube, V
σ
4
, was selected to justify a D on the input to Y. Since the
input is synchronized to the clock, the cube V
σ
4
becomes part of the preceding time
frame. Values on Z, U, V, and Y for this resultant cube are interpreted by using the
legends at the bottom of Table 5.6. Super blocks Z, U and Y have both a final value
t XX d X XX X X 1 Z
σ
1

X0Dt XXXX1/0XY
σ
2
t 0Dt XXXX1/01
t
0Dt X X X X 1/0 1
XA
XX0 0 X X X X U
α
t A Dt 0 0 X X 1/0 1
258
SEQUENTIAL LOGIC TEST
and a switching action specified. During an exercising sequence the t denotes a
transition on the outputs of Z and Y from a present state of 0 to a final state of 1. The
A on U denotes a super flip-flop that is false at rest; that is, its final value is false and,
furthermore, it did not change. Therefore, the Set input to Y is inactive. Super flip-
flop V has a D, which is an input value; therefore no final value is specified for that
super flip-flop.
The interpretation, then, of the resultant cube is that there is an output of 1,
0, X, 1 at time n + 1 from the four super blocks. At time n the circuit requires
values 0, 0, 1, 0 on the outputs of the super blocks and values A, B, C, D, E,
F = (0, 0, X, X, 1/0, 1) on the primary inputs. Note that the clock value is spec-
ified as 1/0 and is regarded as a single stimulus, although in fact it requires two
time images.
The values (Z, U, V, Y) = (0, 0, 1, 0) required on the super blocks at time n must
now be justified. The original third cube, V
σ
4
, which was selected to justify a D at
the input to V, puts a t on the output of V and requires a 0 on the input driven by U.

Its combinational logic inputs require a 0 on input C and a D on the input from super
flip-flop Y. The t represents a true final state on V and therefore satisfies the require-
ment imposed by the previously created pattern. However, we still need 0s on the
other super flip-flops. We must justify these values without conflicting with values
of the cube V
σ
4
.
There is already an apparent conflict. The cube requires a D on Y, and the pre-
viously created cube requires a 0 on Y. However, the D is an input to the super
flip-flop at time n − 1 as specified by the cube V
σ
4
. The 0 is an output require-
ment at time n and the cube V
σ
4
specifies that flip-flop V is to perform a toggle.
The apparent problem is caused by the fact that a loop exists. We attempt to jus-
tify the 0 required on U. The cube U
ρ
will justify the 0. We then select Z
ρ
1
to get
a 0 on Z, and we select Y
ρ
to get a 0 on Y. The intersection of these cubes yields
the following:
All columns except column 4, corresponding to super flip-flop Y, follow directly

from the intersection table. As mentioned, the fourth column requires a d output
from Y and a D input. In addition, the cube Y
σ
2
requires a 1/0 toggle. Therefore,
we intersect a D and t to get T and then intersect T with d to again get a T. The
exercising sequence is now complete. The values t, A, T, T satisfy the require-
ments for 0, 0, 1, 0 that we set out to obtain, but they in turn impose initial
conditions of 1, 0, 0, 1. We therefore must create an initialization sequence by
continuing to justify backward in time until we eventually reach a point in which
tXXdXXXX X 1 Z
ρ
1
X0Dt X X X X 1/0 X Y
σ
2
XtXX0dXXX X U
ρ
X0 tD X X 0 X 1/0 X V
σ
4
tAT T 0 d 0 X 1/0 1
SEQUENTIAL LOGIC TEST COMPLEXITY
259
all of the super blocks have X states. To satisfy the assignments 1, 0, 0, 1, we
intersect the following:
During creation of the initialization sequence, we are aided by an additional
observation. The t, which implied a true final state and a false start state while build-
ing the exercising sequence, still implies a true final state but implies an x state while
constructing the initializing sequence. Therefore the values t, A, T, t on the super

blocks satisfy the 1,0,0,1 requirement and also imply a previous state of X, 0, 1, X
on the super block outputs. Thus, two of the super blocks can be ignored.
To get the previous state in which U = 0 and V = 1, we intersect:
Again, the t satisfies the requirement for V = 1 and specifies a previous don’t care
state. Since we are constructing an initializing sequence at this point, rather than an
exercising sequence, the D is ignored; that is, it is treated as a logic 1. A 0 is now
required on the output of super flip-flop U. The D-cube U
ρ
is used, which puts a t on
the output of the flip-flop, hence a 0 preceded by a don’t care state. The inputs for that
cube are 0 and d. The d is again treated as a 1 because this is the initializing sequence.
The task is done; we now go back and reconstruct the entire sequence. We get:
5.4 SEQUENTIAL LOGIC TEST COMPLEXITY
A general solution to the test problem for sequential logic has proven elusive. Recall
that several algorithms exist that can find a test for any fault in a combinational circuit,
t
XX dXXXX X 1Z
σ
1
XtXX0dXXXXU
ρ
X0 t XXX1D1/0 X V
ρ
1
X0D tX X X X 1/0 X Y
σ
2
t A Tt0d1D1/0 1
XAXX0 0 XX X X U
α

X0 t X X X 1 D 1/0 X V
σ
2
XA t X 0 0 1 D 1/0 X
nZUVYABCDEF
1 XXXX 0 1 XX X X
2 X0XX 00111/0X
3 X01X 01101/01
4 1001 010X1/01
5 0010 00XX1/01
6 10X1
260
SEQUENTIAL LOGIC TEST
if a test exists, given only a list of the logic elements used in the circuit and their inter-
connections. No comparable theoretical basis for sequential circuits exists under the
same set of conditions.
5.4.1 Acyclic Sequential Circuits
The analysis of sequential circuits begins with the circuit of Figure 5.8. Although it
is sequential, it is loop-free, or acyclic. There is no feedback, apart from that which
exists inside the flip-flops. In fact, the memory devices need not be flip-flops, the
circuit could be implemented with delays or buffers to obtain the required delay.
The circuit would not behave exactly the same as a circuit with clocked flip-flops,
since flip-flops can hold a value for an indefinite period if the clock is halted,
whereas signals propagate unimpeded through delay lines. However, with delay
lines equalling the clock period, it would be impossible for an observer strobing the
outputs to determine if the circuit were implemented with delay lines or clocked
flip-flops.
If the circuit is made up of delay lines, then for many of the faults the circuit
could be considered to be purely combinational logic. The signal at the output fluc-
tuates for a while but eventually stabilizes and remains constant as long as the inputs

are held constant. If a tester connected to the output samples the response at a suffi-
ciently late time relative to the total propagation time through the circuit, the delay
lines would have no more effect than wires with zero delay and could therefore be
completely ignored.
If the delays are flip-flops, how much does the analysis change? Suppose the goal
is to create a test for an SA1 fault on the top input to gate B
4
. A test for the SA1 fault
can be obtained by setting I
1
= 0, FF
2
= X and FF
3
= 1. If FF
4
represents time image
n, then a 1 is required on primary input I
6
in time image n − 1 in order to justify the
1 on FF
3
in time image n. Propagation through FF
5
in time image n + 1 is achieved
by requiring FF
7
= 1. That can be justified by setting I
5
= 1 in time image n and

I
4
= 1 in time image n − 1. The entire sequence becomes
Figure 5.8 An acyclic sequential circuit.
FF
5
FF
4
B
5
I
6
B
4
B
3
FF
2
FF
3
FF
7
B
2
FF
1
B
6
B
1

FF
6
I
1
I
2
I
3
I
4
I
5
Out
SEQUENTIAL LOGIC TEST COMPLEXITY
261
Figure 5.9 The acyclic rank-ordered circuit.
To summarize, a fault is sensitized in time image n, and assignments are justified
backward in time to image n − 1 and are propagated forward in time to image n + 1.
The result finally appears at an observable output in time image n + 2. Of interest here
is the fact that the test pattern could almost as easily have been generated by a combi-
national ATPG. The circuit has been redrawn as an S-graph in Figure 5.9, where the
nodes in the graph are the original flip-flops. The logic gates have been left out but the
connections between the nodes represent paths through the original combinational
logic. The nodes have been rank-ordered in time, with the time images indicated at the
top of Figure 5.9. Because FF
7
fans out, it appears twice, as does its source FF
6
.
In order to test the same fault in the redrawn circuit, the flip-flops can be ignored

while computing input stimuli and the rank-ordered circuit can be used to determine
the time images in which stimuli must occur. For test purposes, the complexity of
this circuit is comparable to that of a combinational circuit. Since the number of test
patterns for a combinational circuit with n inputs is upper bounded by 2
n
, the num-
ber of test patterns for this pseudo-combinational circuit is upper-bounded by
k · 2
n
, where k is circuit depth; that is, k is the maximum number of flip-flops in any
path between any input and any output.
Example A test will be created for the bottom input of B
4
SA1. The input stimuli are
Time I
1
I
2
I
3
I
4
I
5
I
6
Out
n − 1 XXX1X1 X
n 0 XXX1X X
n + 1 X X X X X X X

n + 2 D
I
1
I
2
I
3
I
4
I
5
I
6
1 1 1 1/1 1/1 0
FF
5
FF
4
I
6
FF
2
FF
3
FF
7
FF
6
I
4

I
5
I
5
I
4
FF
6
I
3
I
2
I
1
Out
n
n + 1 n + 2 n + 3 n + 4 n + 5
FF
1
FF
7
262
SEQUENTIAL LOGIC TEST
The double assignments for I
4
and I
5
represent values at different times due to fanout.
If destination flip-flops exist in different time images, we can permit what would nor-
mally be conflicting assignments. If the fanout is to two or more destination flip-flops,

all of which exist in the same time image, then the assignments must not conflict.
From the rank-ordered circuit it is evident that the values must occur in the following
time images:
The previously generated test sequence can be shifted three units forward in time
and merged with the second test sequence to give

5.4.2 The Balanced Acyclic Circuit
The concept of using a combinational ATPG for the circuit of Figure 5.8 breaks
down for some of the faults. For example, an SA0 on the top input to B
6
, driven by
FF
6
, cannot be tested in this way because the fault requires a 0 for sensitization and
a 1 for propagation. The circuit is said to be unbalanced because there are two fanout
paths from FF
7
to the output and there are a different number of flip-flops in each of
the fanout paths.
When every path between any two nodes in an acyclic sequential circuit has the
same number of flip-flops, it is called a balanced acyclic sequential circuit. The
sequential depth d
max
of the balanced circuit is the number of nodes or vertices on
the longest path in the S-graph. Given a balanced circuit, the sequential elements in
Out I
1
I
2
I

3
I
4
I
5
I
6
Time
XXXX1XX n
XXXXX1Xn + 1
XXX1XXXn + 2
XX1X1X0n + 3
X1XXX1Xn + 4
XXXXXXXn + 5
D n + 6
Out I
1
I
2
I
3
I
4
I
5
I
6
Time
X XXX1XX n
X XXXX 1 X n + 1

X XX1 1X 1 n + 2
X 01X11 1 n + 3
X 1XXX1 X n + 4
D
XXXXXX n + 5
D
n + 6

SEQUENTIAL LOGIC TEST COMPLEXITY
263
Figure 5.10 A strongly balanced circuit.
the model can be replaced by wires or buffers. Vectors can then be generated for
faults in the resulting circuit model using a combinational ATPG. The vector thus
generated is applied to the circuit for a duration of d
max
+ 1 clock cycles.
8
An internally balanced acyclic sequential circuit is one in which all node pairs
except those involving primary inputs are balanced.
9
Like the balanced sequential
circuit, the internally balanced circuit can be converted to combinational form by
replacing all flip-flops with wires or buffers. However, one additional modification
to the circuit model is required: The primary inputs that are unbalanced are split
and represented by additional primary inputs so that the resulting circuit is bal-
anced. Then, the combinational ATPG can be used to create a test pattern. Each test
pattern is replicated d
max
+ 1 times. The logic bits on the replicated counterpart I
j

' to
the original input I
j
must be inserted into the bitstream for input I
j
at the appropriate
time.
Another distinction can be made with respect to balanced circuits. A strongly
balanced acyclic circuit is balanced and, in addition, all paths from any given node
in the circuit to the primary inputs driving its cone have the same sequential depth.
10
This is illustrated in Figure 5.10. A backtrace from Out to any primary input
encounters three flip-flops. For test purposes, the model can be altered such that the
flip-flops are converted to buffers. Then, test vectors for individual faults can be
generated by a combinational ATPG. These are then stacked and clocked through
the actual circuit on successive clock periods. The last vector, applied to the inputs
at time n, will cause a response at Out during time n + 3.
A hierarchy of circuit types, based on sequential constraints, is represented in
Figure 5.11 (combinational circuits are most constrained). A general sequential
circuit can be converted to acyclic sequential by means of scan flip-flops (cf.
Chapter 8). The flip-flops to be scanned can be chosen using a variant of the loop-
cutting algorithm described in Section 5.3.2. Given an acyclic circuit, it has been
shown that a balanced model of the circuit can be created for ATPG purposes. Each
FF
8
FF
6
B
5
I

4
B
4
B
2
FF
2
FF
3
FF
7
B
1
FF
1
B
3
FF
4
I
1
I
2
I
3
I
5
I
6
FF

5
Out
264
SEQUENTIAL LOGIC TEST
Figure 5.11 Classification based on sequential constraints.
vector created by the combinational ATPG is then transformed into a test sequence
for the actual circuit.
11
It is reported that this approach reduces the ATPG time by an
order of magnitude while producing vector lengths comparable to those obtained by
sequential ATPGs.
5.4.3 The General Sequential Circuit
Consider what happens when we make one alteration to the circuit in Figure 5.8.
Input I
5
is eliminated and a connection is added from the output of B
5
to the input of
B
6
. With this one slight change the entire nature of the problem has changed and the
complexity of the problem that we are trying to solve has been compounded by
orders of magnitude. In the original circuit the output was never dependent on inputs
beyond six time frames. Furthermore, no flip-flop was ever dependent on a previous
state generated in part by that same flip-flop.
That has changed. The four flip-flops FF
1
, FF
2
, FF

4
, and FF
7
constitute a state
machine of 16 states in which the present state may be dependent on inputs that
occurred at any arbitrary time in the past. This can be better illustrated with the state
transition graph of Figure 5.12. If we start in state S
1
the sequence 1011111 takes
Figure 5.12 State transition graph.
Sequential
Acyclic Sequential
Internally Balanced
Balanced
Strongly
Balanced
Combinational
Most constrained
Least constrained
S
1
S
7
S
5
S
6
S
4
S

2
S
8
S
3
0/0
1/0
0/0
1/0
1/0
0/00/0
1/1
1/0
1/1
0/0
0/0
0/1
1/1 1/1
0/0
SEQUENTIAL LOGIC TEST COMPLEXITY
265
us to S
2
{S
7
, S
8
, S
5
, S

6
}*, where the braces and asterisk denote an arbitrary number
of repetitions of the four states in braces. From the almost identical sequence
11011111 , we get the state sequence S
2
, S
3
{S
3
,S
4
,S
1
,S
2
}*. The corresponding
output sequences are 0,0{0,0,0,1}* and 0,1,0{1,1,0,1}*, a significant difference
in output response that will continue as long as the input consists of a string of
1s. In a circuit with no feedback external to the flip-flops the output sequences
will coincide within k time images where k again represents the depth of the
circuit.
How much effect does that feedback line have on the testability of the circuit? We
will compute an upper bound on the number of test patterns required to test a state
machine in which the present state is dependent on an input sequence of indetermi-
nate length—that is, one in which present state of the memory cells is functionally
dependent upon a previous state of those same memory cells.
Given a state machine with n inputs and M states, 2
m−1
< M < 2
m

, and its corre-
sponding state table with M rows, one for each state, and 2
n
columns, one for each
input combination, there could be as many as 2
n
unique transitions out of each
state. Hence, there could be as many as M · 2
n
, or approximately 2
m+n
, transitions
that must be verified. Given that we are presently in state S
i
, and we want to verify
a transition from state S
j
to state S
k
, it may require M − 1 transitions to get from S
i
to S
j
before we can even attempt to verify the transition S
j
→ S
k
. Thus, the number
of test vectors required to test the state machine is upper bounded by 2
2m+n

, and
that assumes we can observe the present state without requiring any further state
transitions.
The argument was derived from a state table, but is there a physical realization
requiring such a large number of tests? A realization can, in fact, be constructed
directly from the state table. The circuit is implemented with m flip-flops, the out-
puts of which are used to control m multiplexers, one for each flip-flop. Each mul-
tiplexer has M inputs, one for each row of the state table. Each multiplexer input is
connected to the output of another multiplexer that has 2
n
inputs, one correspond-
ing to each column of the state table. The inputs to this previous bank of multi-
plexers are fixed at 1 and 0 and are binary m-tuples corresponding to the state
assignments and the next states in the state table. In effecting state transitions, the
multiplexers connected directly to the flip-flops select the row of the state table
and the preceding set of multiplexers, under control of the input signal, select the
column of the state table, thus the next state is selected by this configuration of
multiplexers.
In this implementation M · 2
n
m-tuples must be verified, one for each entry in the
state table. From the structure it can be seen that checking a given path could
require as many as M − 1 transitions of the state machine to get the correct selection
on the first bank of multiplexers. Consequently, the number of test patterns required
to test this implementation is upper bounded by 2
2m+n
. This is not a practical way to
design a state machine, but it is necessary to consider worst-case examples when
establishing bounds. Of more significance, the implementation serves to illustrate
the dramatic change in the nature of the problem caused by the presence of feed-

back lines.
266
SEQUENTIAL LOGIC TEST
Figure 5.13 Canonical implementation of state table.
Example Consider the machine specified by the following state table and flip-flop
state assignments:
This machine can be implemented in the canonical form of Figure 5.13. 
5.5 EXPERIMENTS WITH SEQUENTIAL MACHINES
Early efforts at testing state machines consisted of experiments aimed at determin-
ing the properties or behavior of a state machine from its state table.
12
Such experi-
ments consist of applying sequences of inputs to the machine and observing the
output response. The input sequences are derived from analysis of the state table and
may or may not also be conditional upon observation of the machine’s response to
previous inputs. Sequences in which the next input is selected using both the state
table and the machine’s response to previous inputs are called adaptive experiments.
I
01 Q
1
Q
1
S
0
S
0
S
2
S
2

00
S
1
S
3
S
2
S
1
01
S
2
S
1
S
0
S
2
10
S
3
S
2
S
3
S
3
11
DQ
1

0
1
1
1
0
0
1
1
AB
AB
D
Q
0
0
0
1
0
1
0
0
1
MUX
MUX
I
Clock
EXPERIMENTS WITH SEQUENTIAL MACHINES
267
The selection of inputs may be independent of observations at the outputs. Those in
which an entire input sequence is constructed from information contained in the
state table, without observing machine response to previous inputs, are called preset

experiments.
A sequence may be constructed for one of several purposes. It may be used to
identify the initial or final state of a machine or it may be used to drive the machine
into a particular state. Sequences that identify the initial state are called distinguish-
ing sequences, those that identify the final state are called homing sequences. A
sequence that is designed to force a machine into a unique final state independent of
the initial state is called a synchronizing sequence (the definitions here are taken
from Hennie
13
).
The creation of input sequences can be accomplished through the use of trees in
which the nodes correspond to sets of states. The number of states in a particular set
is termed its ambiguity. The root will usually correspond to maximum ambiguity,
that is, the set of all states.
Example Consider the state machine whose transitions are described by the state
table of Figure 5.14. Can the initial state of this machine be determined by means of
a preset experiment?
The object is to find an input sequence that can uniquely identify the initial state
when we start with total ambiguity and can do no more than apply a precomputed set
of stimuli and observe output response. From the state table we notice that if we apply
a 0, states A and D both respond with a 1 and both go to state A. Clearly, if an input
sequence starts with a 0, it will never be possible to determine from the response
whether the machine started in state A or D. If the sequence begins with a 1, a 0
response indicates a next state of B or E and a 1 response indicates a next state of A,
B, or C. Therefore, a logic 1 partitions the set of states into two subsets that can be
distinguished by observing the output response of the machine.
Applying a second 1 further refines our knowledge because state B produces a 1
and state E produces a 0. Hence an input sequence of (1,1) enables us, by working
backwards, to determine the initial state if the output response begins with a 0. The
0 response indicates that the initial state was a C or E. If a second 0 follows, then the

machine must have been in state E after the first input, which indicates that it must
originally have been in state C. If the second response is a 1, then the machine is in
Figure 5.14 State table.
A
B
C
D
E
A/1
C/0
D/0
A/1
B/0
C/1
A/1
E/0
B/1
B/0
01
I
268
SEQUENTIAL LOGIC TEST
Figure 5.15 Preset experiment.
state B, indicating that it was originally in state E. But what if the initial response
was 1? Rather than repeat this analysis, we resort to the use of a tree, as illustrated in
Figure 5.15, in which we start with maximum ambiguity at the root and form
branches corresponding to the inputs I = 0 and I = 1. We create subsets comprised of
the next states with set membership based on whether the output corresponding to
that state is a 1 or 0.
When a 0 is applied to the set with maximum ambiguity, the path is immediately

terminated because states A and D merged; that is, they produced the same output and
went to the same next state, hence there was no reason to continue the path. When a
1 is applied, two subsets are obtained with no state mergers in either subset. From this
branch of the tree, if the second input is a 1, then a third input of either a 0 or 1 leads
to a leaf on the tree in which all sets are singletons. If the second input is a 0, then
following that with a 1 leads to a leaf in which all sets are singletons. We conclude,
therefore, that there are three preset distinguishing sequences of length three, namely,
(1, 1, 0), (1, 1, 1), and (1, 0, 1). If the sequence (1, 1, 0) is applied to the machine in
each of the five starting states, we get

From the output response the start state can be uniquely identified. It must be
noted that a state machine need not have a distinguishing sequence. In the example
just cited, if a 1 is applied while in state E and the machine responds with a 1, then
another merger would result and hence no distinguishing sequence exists. Another
terminating rule, although it did not happen in this example, is as follows: Any leaf
that is identical to a previously occurring leaf is terminated. There is obviously no
new information to be gained by continuing along that path.
Start State Output Response Final State
A 1 0 0 B
B 1 1 0 D
C 0 0 0 C
D 1 1 1 A
E 0 1 1 A
(ABCDE)
01
(AA)(BCD)
(ABC)(BE)
0
1
(A)(CD)(BC)(AC)(E)(A)(B)

(E)(C)(B)(C)(B)(A)(D)(E)(A)(B)(A)(A)(D)(CD)(C)(C)(B)(B)(E)
01 0 1
X

EXPERIMENTS WITH SEQUENTIAL MACHINES
269
Because the distinguishing sequence identifies the initial state, it also uniquely
identifies the final state; hence the distinguishing sequence is a homing sequence.
However, the homing sequence is not necessarily a distinguishing sequence. Con-
sider again the machine defined by the state table in Figure 5.14. We wish to find one
or more input sequences that can uniquely identify the final state while observing
only the output symbols. Therefore, we start again at the source node and apply a 0
or 1. However, the path resulting from initial application of a 0 is not discarded
because we are now interested in the final state rather than initial state; therefore
state mergers do not cause loss of needed information.
Example We use the same state machine, but only pursue the branch that was pre-
viously deleted, since the paths previously obtained are known to be homing
sequences. This yields the tree in Figure 5.16.
From this continuation of the original tree we get several additional sequences of
outputs that contain enough information to determine the final state. However,
because of the mergers these sequences cannot identify the initial state and therefore
cannot be classified as distinguishing sequences. 
The synchronizing sequence forces the machine into a known final state indepen-
dent of the start state. We again use the state machine of Figure 5.14 to illustrate the
computation of the synchronizing sequence. As before, we start with the tree in which
the root is the set with total ambiguity. The computations are illustrated in Figure 5.17.
Starting with the total ambiguity set, we apply 0 and 1 and look at the set of a 1
possible resulting states. With a 0 the set of successor states is (ABCD), and with a 1
the set of successor states is (ABCE). We then consider the set of all possible succes-
sor states that can result from these successor states. From the set of successor states

(ABCD) and an input of 0 the set of successor states is the set (ACD). We continue
until we either arrive at a singleton state or all leaves of the tree are terminated. A
leaf will be terminated if it matches a previously occurring subset of states or if it
properly contains another leaf that was previously terminated. In the example just
given, we arrive at the state A upon application of the sequence (0, 0, 0, 0). Other
sequences exist; we leave it to the reader to find them.
Figure 5.16 Determining final state.
(ABCDE)
01
(AA)(BCD)(ABC)(BE)
(A)(A)(CD)(C)(E)(AB)
(A)(A)(A)(D)(A)(A)(B)(E)
01
(D)(B)(A)(C)(E)(A)(AC)
(B)(A)(A)(D)(B)(C)(C)(E)
01
01
270
SEQUENTIAL LOGIC TEST
Figure 5.17 Synchronizing sequence.
The same state machine will now be used to describe how to create an adaptive
homing sequence. Recall that adaptive experiments make use of whatever informa-
tion can be deduced from observation of output response. From the state table it is
known that if a 0 is applied and the machine responds with a 1, then it is in state A
and we can stop. If it responds with a 0, then it must be in B, C, or D. Either a 0 or 1
can be chosen as the second input. If a 0 is chosen, we find that with an output
response of 1 the machine must again be in state A and with a response of 0 it must
be in state C or D. Finally, with a third input there is enough information to uniquely
identify the state of the machine. Adaptive experiments frequently permit faster con-
vergence to a solution by virtue of their ability to use the additional information pro-

vided by the output response.
The distinguishing sequence permits identification of initial state by observation
of output response. This is possible because the machine responds uniquely to the
distinguishing sequence from each starting state. The existence of a distinguishing
sequence can therefore permit a relatively straightforward construction of a checking
sequence for a state machine. The checking sequence is intended to confirm that the
state table correctly describes the behavior of the machine. It is required that the
machine being evaluated not have more states than the state table that describes its
behavior. The checking sequence consists of three parts:
1. Put the machine into a known starting state by means of a homing or synchro-
nizing sequence.
2. Apply a sequence that verifies the response of each state to the distinguishing
sequence.
3. Apply a sequence that verifies state transitions not checked in step 2.
The state machine in Figure 5.14 will be used to illustrate this. The machine is
first placed in state A by applying a synchronizing sequence. For the second step, it
is necessary to verify the response of the five states in the state table to the distin-
guishing sequence since that response will subsequently be used to verify state
(ABCDE)
(ABCD)(ABCE)
01
(ACD)
(ABCE)
(ABCD)(ABCE)
(AD)
(A)(BC)
(BCE)
(BCD)(ABE)
001 1
01

01
01
XX X
EXPERIMENTS WITH SEQUENTIAL MACHINES
271
transitions. To do so, a sequence is constructed by appending the distinguishing
sequence (1, 1, 0) to the synchronizing sequence. If the machine is in state A, it
responds to the distinguishing sequence with the output response (1, 1, 0). Further-
more, the machine will end up in state B. From there, state B can be verified by
again applying the distinguishing sequence.
This time the output response will be (1, 1, 0) and the machine will reach state D.
A third repetition verifies state D and leaves the machine in state A, which has
already been verified. Therefore, from state A a 1 is applied to put the machine into
state C where the distinguishing sequence is again applied to verify state C. Since
the machine ends up in state C, a 1 is applied to cause a transition to state E. Then
the distinguishing sequence is applied one more time to verify E. At this point the
distinguishing sequence has been applied while the machine was in each of the five
states. Assuming correct response by the machine to the distinguishing sequence
when starting from each of the five states, the input sequence and resulting output
sequence at this point are as follows:
The synchronizing sequence is denoted by s.s., and the distinguishing sequence is
denoted by d.s. The dashes (—) denote points in the sequence where inputs were
inserted to effect transitions to states that had not yet been verified. The output val-
ues for the synchronizing sequence are unknown; hence they are omitted.
If the machine responds as indicated above, it must have at least five states
because the sequence of inputs (1, 1, 0) occurred five times and produced five differ-
ent output responses. Since we stipulated that it must not have more than five states,
we assume that it has the same number of states as the state table. Now it is neces-
sary to verify state transitions. Two transitions in step 2 have already been verified,
namely, the transition from A to C and the transition from C to E; therefore eight

state transitions remain to be verified.
Since the distinguishing sequence applied when in state E leaves the machine in
state A, we start by verifying the transition from A to A in response to an input of 0.
We apply the 0 and follow that with the distinguishing sequence to verify that the
machine made a transition back to state A. The response to the distinguishing
sequence puts the machine in state B and so we arbitrarily select the transition from
B to C by applying a 0. Again it is necessary to apply the distinguishing sequence
after the 0 to verify that the machine reached state C from state B. The sequence now
appears as follows:
s.s d.s. d.s. d.s. — d.s. — d.s.
input 0 0 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 1 0
output 1 0 0 1 1 0 1 1 1 1 0 0 0 0 0 1 1
s.s d.s. d.s. d.s. — d.s. — d.s. — d.s.
input 0 0 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 1 0 0 1 1 0
output 1 0 0 1 1 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0
272
SEQUENTIAL LOGIC TEST
We continue in this fashion until all state transitions have been confirmed. At this
point six transitions have not yet been verified; we leave it as an exercise for the
reader to complete the sequence.
5.6 A THEORETICAL LIMIT ON SEQUENTIAL TESTABILITY
The D-algorithm described by Paul Roth
14
is known to be an algorithm in the strict-
est sense. It can generate tests for combinational circuits, given no more than a struc-
tural description of the circuit, including the primitives that make up the circuit and
their interconnections. In this section it is shown that such a claim cannot be made
for general sequential circuits under the same set of conditions.
The pulse generator of Figure 5.18 demonstrates that this is not true for asynchro-
nous sequential circuits. In normal operation, if it comes up in the 0 state when

power is applied, it remains in that state. If it comes up in the 1 state, that value
reaches the reset input and resets it to 0 (assuming an active high reset). Since it is
known what stable state the circuit assumes shortly after powering up, it can be
tested for all testable faults. Simply apply power and check for the 0 state on the out-
put. Then clock it and monitor the output for a positive going pulse that returns to 0.
A simulator that operates on a structural model begins by initializing all the nets
in the circuit to the indeterminate X state. The X at the Q output of the self-resetting
flip-flop could be a 1 or a 0. If a simulator tries to clock in a 1, both possible states of
X at the reset input must be considered. If the X represents a 1, it holds the circuit to
a 0. If the X represents 0, it is inactive and the clock pulse drives the output to 1.
This ambiguity forces the simulator to leave an X on the Q output. So, despite the
fact that the circuit is testable, with only a gate-level description to work with, the
simulator cannot drive it out of the unknown state.
For the class of synchronous sequential machines, the Delay flip-flop in which the
Q output is connected to the Data input, essentially an autonomous machine, is an
example of a testable structure that cannot be tested by an ATPG, given only structural
information. We know that there should be one transition on the output for every two
transitions on the clock input. But, again, when all nets are initially set to the indeter-
minate state, we preclude any possibility of predicting the behavior of the circuit.
It is possible to define the self-resetting flip-flop as a primitive and specify its
behavior as being normally at 0, with a pulse of some specified duration occurring at
the output in response to a clock input. That, in fact, is frequently how the circuit is
handled. The monostable, or single shot, is available from IC manufacturers as a sin-
gle package and can be defined as a primitive.
Figure 5.18 Self-resetting flip-flop.
DELAY
DQ
R
Clock
A THEORETICAL LIMIT ON SEQUENTIAL TESTABILITY

273
Figure 5.19 State transition graphs.
If the self-resetting flip-flop is modeled as a primitive and if the autonomous
machine is excluded, can it be shown that synchronous sequential machines are test-
able under the same set of conditions defined for the D-algorithm? To address this
question, we examine the state transition graphs of Figure 5.19. One of them can be
tested by a gate-level ATPG, using only structural information; the other cannot,
even though both of them are testable.
The state tables for the machines of Figure 5.19(a) and 5.19(b) are shown in
Figures 5.20(a) and 5.20(b), respectively. For machine A the synchronizing
sequence I = (0, 1, 0, 1, 0) will put the machine in state S
1
. For machine B the syn-
chronizing sequence I = (0, 0) will put the machine in state S
3
. The length and nature
of the synchronizing sequence plays a key role in determining whether the machine
can be tested by a gate-level ATPG. Consider the machine shown in Figure 5.21; it is
an implementation of the machine in Figure 5.19(a). Assign an initial value of (X,X)
to the flip-flops labeled Q
1
, Q
0
. Because a synchronizing sequence of length 5 exists,
we know that after the application of 5 bits the machine can be forced into state S
1
.
However, upon application of any single stimulus, whether a 0 or 1, machine A has
an ambiguity of at best 3 and possibly 4. Because the ambiguity is greater than 2,
two bits are required to represent the complete set of successor states, hence simula-

tion of any binary input value must leave both output bits, Q
1
and Q
0
, uncertain; that
is, both Q
1
and Q
0
could possibly be in a 0 state or a 1 state, hence, both Q
1
and Q
0
remain in the X state.
Figure 5.20 State tables.
S
0
S
1
S
2
S
3
0
1
0
1
01
1
0

0
(a)
S
0
S
1
S
2
S
3
0
1
1
01
1
0
(b)
S
0
S
1
S
2
S
3
S
1
S
3
S

1
S
0
S
1
S
2
S
3
S
0
01 01
Data
S
0
S
1
S
2
S
3
S
1
S
3
S
1
S
3
S

1
S
2
S
3
S
0
Data
274
SEQUENTIAL LOGIC TEST
Figure 5.21 Implementation of the state machine.
In general, if a synchronizing sequence exists for an M-state machine, 2
m−1
< M ≤
2
m
, implemented with m flip-flops, the machine is testable. It is testable because the
synchronizing sequence will drive it to a known state from which inputs can be
applied that will reveal the presence of structural defects. A synchronizing sequence
can be thought of as an extended reset; conversely, a reset can be viewed as a syn-
chronizing sequence of length 1. However, if no single vector exists that can reduce
ambiguity to 2
m−1
or less, then all flip-flops are capable of assuming either binary
state. Put another way, no flip-flop is capable of getting out of the indeterminate
state.
Given a vector that can reduce ambiguity enough to cause one flip-flop to assume
a known value, after some number of additional inputs are applied the ambiguity
must again decrease if one or more additional flip-flops are to assume a known state.
For an M-state machine implemented with m flip-flops, 2

m−1
< M ≤ 2
m
, the ambigu-
ity must not exceed 2
m−2
. What is the maximum number of input vectors that can be
applied before that level of ambiguity must be attained?
Consider the situation after one input has been applied and exactly one flip-
flop is in a known state. Ambiguity is then 2
m−1
. From this ambiguity set it is pos-
sible to make a transition to a state set wherein ambiguity is further reduced, that
is, additional flip-flops reach a known value, or the machine may revert back to a
state in which all flip-flops are in an unknown state, or the machine may make a
transition to another state set in which exactly one flip-flop is in a known state.
(In practice, the set of successor states cannot contain more states than its prede-
cessor set.) For a machine with m flip-flops, there are at most 2m transitions such
that a single flip-flop can remain in a known state, 0 or 1. After 2m transitions, it
can be concluded that, if the ambiguity is not further resolved, it will not be
resolved because the machine will at that time be repeating a state set that it pre-
viously visited.
Q
1
D
Clock
Q
0
D
Q

1
Q
0
Data
A THEORETICAL LIMIT ON SEQUENTIAL TESTABILITY
275
Given that i flip-flops are in a known state, how many state sets exist with ambi-
guity 2
m
−
i
? Or, put another way, how many distinct state sets with i flip-flops in a
known state can the machine transition through before ambiguity is further
reduced or the machine repeats a previous state set? To compute this number, con-
sider a single selection of i positions from an m-bit binary number. There are
ways these i bits can be selected from m positions and 2
i
unique values these i
positions can assume. Therefore, the number of state sets with ambiguity 2
m
−
i
, and
thus the number of unique transitions before either repeating a state set or reduc-
ing ambiguity, is . Hence, the synchronizing sequence is upper bounded by
From the preceding we have the following:
Theorem Let M be a synchronous, sequential M-state machine, 2
m−1
< M ≤ 2
m

,
implemented with m binary flip-flops. A necessary condition for M to be testable by
a gate-level ATPG using only structural data is that a synchronizing sequence exist
having the property that, with i flip-flops in a known state, the sequence reduces the
ambiguity to 2
m
−
i−1
within input stimuli.
15
Corollary The maximum length for a synchronizing sequence that satisfies the
theorem is 3
m
− 2
m
− 1.
The theorem states that a synchronizing sequence of length ≤ 3
m
− 2
m
− 1 permits
design of an ATPG-testable state machine. It does not tell us how to accomplish the
design. In order to design the machine so that it is ATPG-testable, it is necessary that
state assignments be made such that if ambiguity at a given point in the synchroniz-
ing sequence is 2
m−i
, then state assignments must be made such that the 2
i
states in
each state set with ambiguity equal to i all have the same values on the 2

m−i
flip-
flops with known values.
Example The state machine described in the following table has a synchronizing
sequence of length 4. The synchronizing sequence is I = (0, 1, 1, 0).
The state sets that result from the synchronizing sequence are
{S
0
, S
1
} → {S
2
, S
3
} → {S
0
, S
2
} → {S
0
}
01
S
0
S
0
S
2
S
1

S
1
S
3
S
2
S
0
S
0
S
3
S
1
S
2
m
i


2
i
m
i


⋅
2
i
i 1=

m 1–
∑
m
i


⋅ 3
m
2
m
– 1–=
2
i
m
i


⋅
276
SEQUENTIAL LOGIC TEST
Figure 5.22 Machine with length 4 synchronizing sequence.
If we assign flip-flop Q
1
= 0 for states S
0
and S
1
, Q
1
= 1 for states S

2
and S
3
, and
Q
0
= 0 for states S
0
and S
2
, then simulation of the machine, as implemented in
Figure 5.22, causes the machine to go into a completely specified state at the end of
the synchronizing sequence. 
The importance of the proper state assignment is seen from the following
assignments.
From the synchronizing sequence we know that the value 0 puts us in either state
S
0
or S
1
. However, with this set of state assignments, Q
1
may come up as a 0 or 1;
the same applies to Q
0
. Hence, the synchronizing sequence is not a sufficient
condition.
We showed the existence of a state machine with synchronizing sequence that
could not be tested by an ATPG when constrained to operate solely on structural
information. It remains to show that there are infinitely many such machines.

The family in Figure 5.23 has an infinite number of members, each member of
which has a synchronizing sequence but, when implemented with binary flip-
flops, cannot be driven from the unknown to a known state because the ATPG,
starting with all flip-flops at X, cannot get even a single flip-flop into a known
state.
Q
1
Q
2
S
0
— 01
S
1
— 10
S
2
— 11
S
3
— 00
Q
1
D
Clock
Q
0
D
Q
1

Data
SUMMARY
277
Figure 5.23 Family of state machines.
5.7 SUMMARY
The presence of memory adds an entirely new dimension to the ATPG problem. A
successful test now requires a sequence of inputs, applied in the correct order, to a
circuit in which some or all of the storage elements may initially be in an unknown
state. New types of faults must be considered. We must now be concerned not only
with logic faults, but also with parametric faults, because proper behavior of a
sequential circuit depends on storage elements being updated with correct values
that arrive at the right time and in the correct order.
Several methods for sequential test pattern generation were examined, including
critical path, which was examined in the previous chapter. Seshu’s heuristics are pri-
marily of historical interest although the concept of using multiple methods, usually
a random method followed by a deterministic approach, continues to be used. The
iterative test generator permits application of the D-algorithm to sequential logic.
The 9-value ITG can minimize computations for developing a test where a circuit
has fanout. Extended backtrace discards the forward trace and aligns sequential
requirements by working back from the output, once a topological path has been
identified. Sequential path sensitizer extends the D-algorithm to sequential circuits
and defines rules for chaining the extended symbols across vector boundaries.
Other methods for sequential test pattern generation exist that were not covered
here. In one very early system, called the SALT (Sequential Automated Logic
Test)
16
system, latches were modeled at the gate level. Loops were identified and
state tables created, where possible, for latches made up of the loops. An extension
of Boolean Algebra to sequential logic is another early system not discussed here.
17

More recent sequential ATPG systems have been reported in the literature but have
had very little impact on the industry.
Despite numerous attempts to create ATPG programs capable of testing sequen-
tial logic, the problem has remained intractable. While some sequential circuits are
reasonably simple to test, others are quite difficult and some simply cannot be tested
by pure gate-level ATPGs. State machines, counters, and other sequential devices
01
I
S
0
S
1
.
.
.
S
n− 1
S
n
S
1
S
2
.
.
.
S
n
S
0

S
0
S
0
.
.
.
S
n− 2
S
n− 1
278
SEQUENTIAL LOGIC TEST
interacting with complex handshaking protocols make it extremely difficult to
unravel the behavior in the proper time sequence. In addition to complexity, another
part of the problem is the frequent need for long and costly sequences to drive state
machines and counters into a state required to sensitize or propagate faults.
The sequential test problem was also examined from a complexity viewpoint.
Synchronizing sequences can be used to show that entire classes of testable sequen-
tial circuits exist that cannot be tested within the same set of groundrules specified
by the D-algorithm. However, more importantly, designers must understand test-
ability problems and design circuits for which tests can be created with existing
tools. In other words, they must design testable circuits. We will have more to say
concerning the issue of design-for-testability (DFT) in Chapter 8. Then, in
Chapter 12 we will examine behavioral ATPG, which uses models described at
higher levels of abstraction.
PROBLEMS
5.1 Using the method described in Section 5.3.2, cut the loops in the D flip-flop
circuit of Figure 2.7. Convert it into a pseudo-combinational circuit by
creating pseudo-inputs and pseudo-outputs.

5.2 Using the pseudo-combinational DFF from the previous problem, use the
ITG and D-algorithm to find tests for the following faults:
Bottom input to gate N1 SA1
Bottom input to gate N4 SA1
Top input to gate N5 SA1
5.3 Attempt to create a test for a SA1 on input 3 of gate 3 of the D flip-flop in
Figure 2.7. What is the purpose of that input?
5.4 Find a test for each of the four input SA1 faults on the cross-coupled NAND
latch of Figure 2.3. Merge these tests to find the shortest sequence that can
detect all four faults.
5.5 Section 4.3.5 defines an intersection table for the values {0, 1, D, D
, X}.
Create an equivalent table for the 9-value ITG. Show all possible intersections
of each of the nine values with all the others. Indicate unresolvable conflicts
with a dash.
5.6 Redesign the circuit in Figure 5.1 by replacing the DFF with the gated latch
of Figure 2.4(b). Cut all loops and use the 9-value ITG to find a test for the
fault indicated in Figure 5.1.
5.7 Create a table for the exclusive-OR similar to Tables 5.2 and 5.3.
5.8 Use the critical path method of Section 5.3.4 to find a test for a SA1 fault on
the Data input of the D flip-flop in Figure 2.7. Show your work.
PROBLEMS
279
5.9 Use EBT to find a test for the indicated fault in the circuit of Figure 5.6. For
the state machine, use the circuit in Figure 5.12. Identify the TP, and show
your work.
5.10 Substitute a D flip-flop for the JK flip-flop in the circuit of Figure 5.7. Assume
the existence of a set input. Duplicate the calculations for the path exercised
in the text, using this D flip-flop.
5.11 Show that a SA1 on the top input to B

6
in Figure 5.8 cannot be tested using a
combinational ATPG.
5.12 In the circuit of Figure 5.8, replace FF
7
by a primary input. The resulting
circuit is now internally balanced. Describe how you would use a
combinational ATPG to detect a fault on the bottom input of gate B
2
.
5.13 A flip-flop can be made into a scan flip-flop if it has a means whereby it can
be serially loaded independent of its normal operation. In such a mode, the
output of the circuit acts as an additional input to the circuit, and the input to
the flip-flop acts as an additional output (see Chapter 8). The circuit of
Figure 5.8 can be made into an internally balanced circuit if one flip-flop is
converted to a scan flip-flop. Which one is it? What is the sequential depth of
the resulting circuit?
5.14 Using the circuit in Figure 5.24, create state machines for the fault-free and
faulty circuits. From the state machines, create a sequence that can detect the
SA1 fault.
5.15 Complete the checking sequence for the example that was started in
Section 5.5.
5.16 Find a synchronizing sequence for the following state machine:
5.17 Describe an algorithm for finding a preset distinguishing sequence.
5.18 The machine (a) below has synchronizing sequence 101. If it starts in state
C, and the machine (b) starts in state A, then the input sequence 101 causes
01
S
0
S

0
S
4
S
1
S
1
S
5
S
2
S
2
S
6
S
3
S
3
S
7
S
4
S
0
S
2
S
5
S

1
S
3
S
6
S
0
S
0
S
7
S
0
S
1
280
SEQUENTIAL LOGIC TEST
Figure 5.24 Johnson Counter.
identical responses from the two machines. Assuming the application of the
sequence 101 to the two machines under the conditions just stated, find a
sequence that exercises each state transition in machine (a) at least once,
without verification, and causes an identical output response from (b); that is,
show that step 2 of the checking sequence is necessary.
REFERENCES
1. Seshu, S., On an Improved Diagnosis Program, IEEE Trans. Electron. Comput.,
Vol. EC-14, No. 2, February 1965, pp. 76–79.
2. Putzolu, G., and J. P. Roth, A Heuristic Algorithm for the Testing of Asynchronous
Circuits, IEEE Trans. Comput., Vol. C20, No. 6, June 1971, pp. 639–647.
3. Bouricius, W. G. et al., Algorithms for Detection of Faults in Logic Circuits, IEEE Trans.
Comput., Vol. C-20, No. 11, November 1971, pp. 1258–1264.

4. Muth, P., A Nine-Valued Circuit Model for Test Generation, IEEE Trans. Comput.,
Vol. C-25, No. 6, June 1976, pp. 630–636.
5. Marlett, Ralph, EBT: A Comprehensive Test Generation Technique for Highly Sequential
Circuits, Proc. 15th Des. Autom. Conf., June 1978, pp. 332–339.
6. Kriz, T. A., A Path Sensitizing Algorithm for Diagnosis of Binary Sequential Logic, Proc.
9th Symposium on Switching and Automata Theory, 1970, pp. 250–259.
7. Kriz, T. A., Machine Identification Concepts of Path Sensitizing Fault Diagnosis, Proc.
10th Symposium on Switching and Automata Theory, Waterloo, Canada, October 1969,
pp. 174–181.
01 01
AC/0 B/0 A A/0 B/0
BA/0 B/1 BC/1 C/0
CB/1 C/1 CB/0 A/1
(a) (b)
U3 U2 U1
U5
U4
Z
CLK
Clear
REFERENCES
281
8. Gupta, R. et al., The BALLAST Methodology for Structured Partial Scan Design, IEEE
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