Tài liệu tham khảo điện tử LM 555

S E M I C O N D U C T O R

CA555, CA555C,
LM555, LM555C, NE555
Timers for Timing Delays and Oscillator Application
in Commercial, Industrial and Military Equipment

May 1997

Features

Description

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The CA555 and CA555C are highly stable timers for use in
precision timing and oscillator applications. As timers, these
monolithic integrated circuits are capable of producing accurate time delays for periods ranging from microseconds
through hours. These devices are also useful for astable
oscillator operation and can maintain an accurately controlled free running frequency and duty cycle with only two
external resistors and one capacitor.

Accurate Timing From Microseconds Through Hours
Astable and Monostable Operation

Adjustable Duty Cycle
Output Capable of Sourcing or Sinking up to 200mA
Output Capable of Driving TTL Devices
Normally ON and OFF Outputs
High Temperature Stability . . . . . . . . . . . . . . 0.005%/oC
Directly Interchangeable with SE555, NE555, MC1555,
and MC1455

Applications
• Precision Timing
• Sequential Timing
• Time Delay Generation

• Pulse Generation
• Pulse Detector
• Pulse Width and Position
Modulation

Ordering Information
PART NUMBER
TEMP.
(BRAND)
RANGE (oC)
CA0555E
-55 to 125
CA0555M (555)
-55 to 125
CA0555M96 (555)
-55 to 125
CA0555T

-55 to 125
CA0555CE
0 to 70
CA0555CM (555C)
0 to 70
CA0555CM96 (555C)
0 to 70
CA0555CT
0 to 70
LM555N
-55 to 125
LM555CN
0 to 70
NE555N
0 to 70
NOTE: † Denotes Tape and Reel

PACKAGE
8 Ld PDIP
8 Ld SOIC
8 Ld SOIC †
8 Pin Metal Can
8 Ld PDIP
8 Ld SOIC
8 Ld SOIC †
8 Pin Metal Can
8 Ld PDIP
8 Ld PDIP
8 Ld PDIP

Pinouts

PKG.
NO.
E8.3
M8.15
M8.15
T8.C
E8.3
M8.15
M8.15
T8.C
E8.3
E8.3
E8.3

The circuits of the CA555 and CA555C may be triggered by
the falling edge of the waveform signal, and the output of
these circuits can source or sink up to a 200mA current or
drive TTL circuits.
These types are direct replacements for industry types in
packages with similar terminal arrangements e.g. SE555
and NE555, MC1555 and MC1455, respectively. The CA555
type circuits are intended for applications requiring premium
electrical performance. The CA555C type circuits are
intended for applications requiring less stringent electrical
characteristics.

Functional Block Diagram
CA555, CA555C (PDIP, SOIC)

LM555, LM555C, NE555 (PDIP)
TOP VIEW

8

TRIGGER
CONTROL
VOLTAGE 5 2

7 DISCHARGE

OUTPUT 3

6 THRESHOLD

RESET 4

5 CONTROL
VOLTAGE

CA555, CA555C (METAL CAN)
TOP VIEW
TAB

8
GND 1

7 DISCHARGE

TRIGGER 2

6 THRESHOLD
5

OUTPUT 3
4

3

6
OUTPUT
THRESHOLD
COMPAR
7

RESET

V+

TRIGGER
COMPAR

FLIP-FLOP

4

DISCHARGE

TRIGGER 2

OUTPUT

8 V+

THRESHOLD

GND 1

V+

1
GND

CONTROL
VOLTAGE

RESET

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

8-3

File Number

834.4

CA555, CA555C, LM555, LM555C, NE555
Absolute Maximum Ratings

Thermal Information

DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V

Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
Metal Can Package . . . . . . . . . . . . . . .
170
85
PDIP Package . . . . . . . . . . . . . . . . . . .
100
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
160
N/A
Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)

Operating Conditions
Temperature Range
CA555, LM555 . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CA555C, LM555C, NE555 . . . . . . . . . . . . . . . . . . . . .0oC to 70oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

TA = 25oC, V+ = 5V to 15V Unless Otherwise Specified
CA555, LM555

PARAMETER

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

4.5

-

18

4.5

-

16

V

V+ = 5V, RL = ∞

-

3

5

-

3

6

mA

V+ = 15V, RL = ∞

-

10

12

-

10

15

mA

-

(2/3)V+

-

-

(2/3)V+

-

V

V+ = 5V

1.45

1.67

1.9

-

1.67

-

V

V+ = 15V

4.8

5

5.2

-

5

-

V

-

0.5

-

-

0.5

-

µA

-

0.1

0.25

-

0.1

0.25

µA

Reset Voltage

0.4

0.7

1.0

0.4

0.7

1.0

V

Reset Current

-

0.1

-

-

0.1

-

mA

V+ = 5V

2.9

3.33

3.8

2.6

3.33

4

V

V+ = 15V

9.6

10

10.4

9

10

11

V

V+ = 5V, ISINK = 5mA

-

-

-

-

0.25

0.35

V

ISINK = 8mA

-

0.1

0.25

-

-

-

V

V+ = 15V, ISINK = 10mA

-

0.1

0.15

-

0.1

0.25

V

ISINK = 50mA

-

0.4

0.5

-

0.4

0.75

V

ISINK = 100mA

-

2.0

2.2

-

2.0

2.5

V

ISINK = 200mA

-

2.5

-

-

2.5

-

V

3.0

3.3

-

2.75

3.3

-

V

V+ = 15V, ISOURCE = 100mA 13.0

13.3

-

12.75

13.3

-

V

ISOURCE = 200mA

-

12.5

-

-

12.5

-

V

R1, R2 = 1kΩ to 100kΩ,
C = 0.1µF
Tested at V+ = 5V, V+ = 15V

-

0.5

2

-

1

-

%

-

30

100

-

50

-

ppm/oC

-

0.05

0.2

-

0.1

-

%/V

DC Supply Voltage
DC Supply Current (Low State),
(Note 2)
Threshold Voltage

SYMBOL

TEST CONDITIONS

CA555C, LM555C, NE555

V+
I+

VTH

Trigger Voltage

Trigger Current
Threshold Current (Note 3)

ITH

Control Voltage Level

Output Voltage

VOL

Low State

Output Voltage
High State

Timing Error (Monostable)
Frequency Drift with Temperature

VOH

V+ = 5V, ISOURCE = 100mA

Drift with Supply Voltage

8-4


CA555, CA555C, LM555, LM555C, NE555
TA = 25oC, V+ = 5V to 15V Unless Otherwise Specified (Continued)

Electrical Specifications

CA555, LM555
PARAMETER

SYMBOL

TEST CONDITIONS

CA555C, LM555C, NE555

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Output Rise Time

tR

-

100

-

-

100

-

ns

Output Fall Time

tF

-

100

-

-

100

-

ns

NOTES:
2. When the output is in a high state, the DC supply current is typically 1mA less than the low state value.
3. The threshold current will determine the sum of the values of R1 and R2 to be used in Figure 4 (astable operation); the maximum total
R1 + R2 = 20MΩ.

Schematic Diagram
THRESHOLD
COMPARATOR

V+

TRIGGER
COMPARATOR

FLIP-FLOP

OUTPUT

8
4.7K

830

4.7K

1K

5K

6.8K

D2

D1

Q16

Q10
Q3

Q19

Q4

Q20

6

3.9K

7K

THRESHOLD
Q1

OUTPUT
3

Q7
Q2

Q5

4.7K

D3

D4

5K
10K
Q18

Q11 Q12

CONTROL
VOLTAGE
5

220

Q15

5K

2
TRIGGER

4.7K

Q14

RESET
4

Q21

Q17

Q13

Q9

100K

Q8

RESET
7
DISCHARGE
1

Q6
DISCHARGE

100

V-

NOTE: Resistance values are in ohms.

Typical Applications
Reset Timer (Monostable Operation)
Figure 1 shows the CA555 connected as a reset timer. In this

mode of operation capacitor CT is initially held discharged by
a transistor on the integrated circuit. Upon closing the “start”
switch, or applying a negative trigger pulse to terminal 2, the
integral timer flip-flop is “set” and releases the short circuit
across CT which drives the output voltage “high” (relay ener-

gized). The action allows the voltage across the capacitor to
increase exponentially with the constant t = R1CT. When the
voltage across the capacitor equals 2/3 V+, the comparator
resets the flip-flop which in turn discharges the capacitor rapidly and drives the output to its low state.

8-5


CA555, CA555C, LM555, LM555C, NE555
V+

RESET
R1

680
4

TA = 25oC
V+ = 5V

8

EO
3

CA555
6

CAPACITANCE (µF)

10

7

1N4001
5

1

10K

2
CT

100

5V

4.7K
0.01µF

680

RELAY

COIL

R1 = 1kΩ

1

10kΩ
100kΩ
1MΩ

0.1

10MΩ
0.01

S1
START

0.001
10-5

10-4

10-3

10-2

10-1

1

10

TIME DELAY(s)

NOTE: All resistance values are in ohms.
FIGURE 3. TIME DELAY vs RESISTANCE AND CAPACITANCE

FIGURE 1. RESET TIMER (MONOSTABLE OPERATION)

Since the charge rate and threshold level of the comparator
are both directly proportional to V+, the timing interval is relatively independent of supply voltage variations. Typically,
the timing varies only 0.05% for a 1V change in V+.

Repeat Cycle Timer (Astable Operation)
Figure 4 shows the CA555 connected as a repeat cycle
timer. In this mode of operation, the total period is a function
of both R1 and R2.

Applying a negative pulse simultaneously to the reset terminal (4) and the trigger terminal (2) during the timing cycle
discharges CT and causes the timing cycle to restart.
Momentarily closing only the reset switch during the timing
interval discharges CT, but the timing cycle does not restart.

V+
5V
R1

4
7

Figure 2 shows the typical waveforms generated during this
mode of operation, and Figure 3 gives the family of time
delay curves with variations in R1 and CT.

R2

8
CA555

6

EO
3
RELAY
COIL

5
1
2

SWITCH S1 “OPEN”
3V
INPUT
VOLTAGE (TERMINAL 2)
SWITCH S1 “CLOSED”
0

CT

3.3V
CAPACITOR
VOLTAGE (TERMINALS 6, 7)
0

0.01µF

FIGURE 4. REPEAT CYCLE TIMER (ASTABLE OPERATION)

T = 0.693 (R1 + 2R2) CT = t1 + t2

tD

where t1 = 0.693 (R1 + R2) CT

5V
OUTPUT
VOLTAGE
(TERMINAL 3)

and t2 = 0.693 (R2) CT
the duty cycle is:
t1
R1 + R2
---------------- = -----------------------t 1 + t 2 R 1 + 2R 2

0

FIGURE 2. TYPICAL WAVEFORMS FOR RESET TIMER

Typical waveforms generated during this mode of operation
are shown in Figure 5. Figure 6 gives the family of curves of
free running frequency with variations in the value of
(R1 + 2R2) and CT .

8-6


CA555, CA555C, LM555, LM555C, NE555
t1

t2

100

TA = 25oC, V+ = 5V

5V

CAPACITANCE (µF)

10

0
3.3V

R1 + 2R2 = 1kΩ
10kΩ

1

100kΩ
1MΩ
10MΩ

0.1

0.01
1.7V
0.001
10-1

0

1

102

10

103

104

105

FREQUENCY (Hz)

Top Trace: Output voltage (2V/Div. and 0.5ms/Div.)
Bottom Trace: Capacitor voltage (1V/Div. and 0.5ms/Div.)
FIGURE 5. TYPICAL WAVEFORMS FOR REPEAT CYCLE TIMER

FIGURE 6. FREE RUNNING FREQUENCY OF REPEAT CYCLE
TIMER WITH VARIATION IN CAPACITANCE AND
RESISTANCE

150
10
SUPPLY CURRENT (mA)

MINIMUM PULSE WIDTH (ns)

Typical Performance Curves

TA = -55oC

100

0oC
25oC
70oC

50
125oC

TA = 125oC

9
8

25oC

7
6

50oC

5
4
3
2
1

0

0.1

0.2

0.3

0.4
0

MINIMUM TRIGGER (PULSE) VOLTAGE (x V+) (NOTE)

2.5

FIGURE 7. MINIMUM PULSE WIDTH vs MINIMUM TRIGGER
VOLTAGE

7.5

10

12.5

15

FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE

2.0

10.0
TA = -55oC

1.6

OUTPUT VOLTAGE - LOW STATE (V)

SUPPLY VOLTAGE - OUTPUT VOLTAGE (V)

5

SUPPLY VOLTAGE (V)

NOTE: Where x is the decimal multiplier of the supply voltage.

25oC

1.2

125oC

0.8

0.4
5V ≤ V+ ≤ 15V
0

V+ = 5V
TA = -55oC
25oC

1.0

125oC

0.1

0.01
1

10

1

100

SOURCE CURRENT (mA)

10
SINK CURRENT (mA)

FIGURE 9. OUTPUT VOLTAGE DROP (HIGH STATE) vs
SOURCE CURRENT

FIGURE 10. OUTPUT VOLTAGE LOW STATE vs SINK
CURRENT

8-7

100


CA555, CA555C, LM555, LM555C, NE555
Typical Performance Curves

(Continued)
10.0

V+ = 10V
TA = -55oC
1.0

25oC

125oC

125oC

V+ = 15V

OUTPUT VOLTAGE - LOW STATE (V)

OUTPUT VOLTAGE - LOW STATE (V)

10.0

25oC
0.1

-55oC

1.0
125oC
25oC
TA = -55oC

0.1

0.01

0.01
1

10

1

100

10

SINK CURRENT (mA)

100

SINK CURRENT (mA)

FIGURE 11. OUTPUT VOLTAGE LOW STATE vs SINK
CURRENT

FIGURE 12. OUTPUT VOLTAGE LOW STATE vs SINK
CURRENT

1.100

NORMALIZED DELAY TIME

1.000

0.990

0.980
0

2.5

5

7.5

10

12.5

15

17.5

1.005

0.995

0.985
-75

-50

-25

0

FIGURE 13. DELAY TIME vs SUPPLY VOLTAGE

250
TA = -55oC

150
0 oC

100

25oC
70oC

50

125oC
0

50

75

100

FIGURE 14. DELAY TIME vs TEMPERATURE

300

200

25

TEMPERATURE (oC)

SUPPLY VOLTAGE (V)

PROPAGATION DELAY TIME (ns)

NORMALIZED DELAY TIME

TA = 25oC

0.1
0.2
0.3
0.4
MINIMUM TRIGGER (PULSE) VOLTAGE (x V+) (NOTE)

NOTE: Where x is the decimal multiplier of the supply voltage.
FIGURE 15. PROPAGATION DELAY TIME vs TRIGGER VOLTAGE

8-8

125