VLSI Physical Design Automation

VLSI Physical Design Automation
Misc. Topics and Conclusion

Prof. David Pan

Office: ACES 5.434
06/06/18

1


Other Design Styles: FPGA
• Field Programmable Gate Array
• First introduced by Xilinx in 1984.
• Pre-fabricated devices and interconnect, which are
programmable by user.
• Advantages:
–
–
–
–

short turnaround time.
low manufacturing cost.
fully testable.
re-programmable.

• Particularly suitable for prototyping, low or mediumvolume production, device controllers, etc.

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2


Comparison of Design Styles
Full-Custom

Standard
Cell

Gate Array

FPGA

Cell size

variable

fixed height

fixed

fixed

Cell type

variable

variable

fixed

programma
ble

Cell placement

variable

in row

fixed

fixed

Interconnections

variable

variable

variable

programma
ble

all layers

all
layers

routing
layers only

no layers

Fabrication
layers

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3


Comparison of Design Styles
Full-Custom Standard Cell

Gate Array

FPGA

Area

compact

compact to
moderate

moderate

large

Performance

high

high
to moderate

moderate

low

Design cost

high

medium

medium

low

Time-to-market

long

medium

medium

short

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4


Programming Technologies
•
•
•
•

SRAM to control pass transistor / multiplexer
EPROM – UV light Erasable PROM
EEPROM – Electrically Erasable PROM
Antifuses – One time programmable

• They are different in ease of manufacturing,
manufacturing reliability, area, ON and OFF
resistance, parasitic capacitance, power consumption,
re-programmability.

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5


Typical FPGA Architecture
• Consists of: Logic modules, Routing resources, and

I/O modules.

Logic Module
IO Module
Routing Tracks
& Switch boxes

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6


FPGA Architecture Examples
Array-based Model

Row-based Model

Logic
Sea-of-Gates Model Module Hierarchical Model
Routing
resources
overlayed
on logic
modules
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7


Two Types of Logic Modules

Look-Up Table (LUT) based:
• A block of RAM to store the truth table.
• A k-input 1-output functions needs 2k bits.
• k is usually 5 or 6.

e.g., f=ABC+ABC

Multiplexer based:

C
B
A
A
B
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f

8


Two Types of Switchboxes
• First Type:

• Second Type:

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9

Several Segmentation Models
• Non-Segmentation Model:

1 4 0 0 2 0 0 3 0 5 0 0 0 0

Not connecting
Connecting

0 0 0 1 0 0 4 0 2 0 3 0 0 5
• Uniform Segmentation Model:

1 4 0 0 2 0 0 3 0 5 0 0 0 0

Fuse or
Programmable
switch

0 0 0 1 0 0 4 0 2 0 3 0 0 5
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10


Several Segmentation Models
• Uniform Staggered Segmentation Model:

1 4 0 0 2 0 0 3 0 5 0 0 0 0
0 0 0 1 0 0 4 0 2 0 3 0 0 5
• Non-uniform Staggered Segmentation Model:

1 4 0 0 2 0 0 3 0 5 0 0 0 0
0 0 0 1 0 0 4 0 2 0 3 0 0 5
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11


Comparison of Segmentation Models
• The segmented model provides better utilization of
routing resources.
• However, segmented model uses more fuses or
programmable switches.
• The delay of a net is directly proportional to the # of
fuses or programmable switches in the route
– Manhattan-distance based delay model does NOT work
anymore
– The segmented model is slower in general

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12


Physical Design of FPGAs
• Very different from other design styles
• Architecture dependent:
–
–
–

–

LUT or Multiplexer in logic modules
Type of switchboxes used
Type of segmentation model used
......

• Physical Design:
– Partitioning
– Floorplanning/Placement
– Routing

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13


Partitioning
• Want to partition the circuit such that each partition
(cluster) can be implemented by a logic module.
• Also called Clustering.
• # of I/O pins, not cluster sizes, is important.
(For multiplexer based logic modules, functionality of
clusters is also important.)

Example:
Using 4-LUTs

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14


Placement
• Assign clusters formed during partitioning to logic
modules of FPGA.
• The problem is the same as gate-array placement.

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15


Routing
• Global routing:
– Similar to global routing in other design styles.
– Minimize wire length and balance densities.

• Detailed routing:
– Very different from other design styles.
– Different algorithms for different segmentation models.
– Channels and switchboxes have fixed capacities.

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16


Structured ASIC
• New buzz word, but essentially gate array

– Mask reconfigurable
– Not field reconfigurable

• Between FPGA and standard cells
– Balance delay/performance and mask cost

• Only programmable once
– by vias (e.g., Via-Programmable Gate Array – VPGA)

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17


Physcial Design Automation
of MCMs and SiPs

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18


MCM and SiP
• Multi-Chip Module
• System in package (SiP)
– Different package styles
– Thermal consideration for 3D

• Alternative packaging approach for high performance
systems.

• Similar to PCB and IC layout problems, but
– PCB layout tools cannot handle the dense and complex
wiring structure of MCM.
– IC layout tools cannot handle the complex electrical, thermal
and geometrical constraints.

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19


Example: Pentium

Substrate size:
32mmx32mm
Package size:
43mmx43mm
(4 times smaller)
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20


Partitioning
• Partitioning a circuit so that each sub-circuit can be
implemented into a chip.
• MCM may contain as many as 100 chips.
• Need to consider timing constraints and thermal
constraints
• In addition, also need to consider traditional I/O

constraints and area constraints.

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21


Placement
• # of components is much less as compared to IC
placement.
• However, need to consider timing constraints and
thermal constraints (as bare chips are placed close to
each other).
• Routing is done in routing layers, not between chips.
• So no routing region needs to be allocated.

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22


Routing
• Main objective is to satisfy timing constraints.
• Another objective is to minimize # of routing layers, not to
minimize routing area.
– Cost is directly proportional to # of layers

• Crosstalk, skin effect and parasitic effect are important
considerations.
• Wires are of smaller pitch and more dense than PCB layout.

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23


EE382 V -- Conclusions

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24


What Have Been Taught?
• Introduced different problems in Physical Design.
• Numerous algorithms which are different in terms of
–
–
–
–
–
–
–
–

design styles
objectives
constraints
techniques
optimality

efficiency
robustness
.....

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