kiến trúc máy tính phạm minh cường chương ter3 arithmetic for computers sinhvienzone com

Computer Architecture
Chapter 3: Arithmetic for Computers

Dr. Phạm Quốc Cường
Adapted from Computer Organization the Hardware/Software Interface – 5th

Computer Engineering – CSE – HCMUT
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Arithmetic for Computers
• Operations on integers
– Addition and subtraction
– Multiplication and division
– Dealing with overflow

• Floating-point real numbers
– Representation and operations

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Integer Addition

• Example: 7 + 6

• Overflow if result out of range
– Adding +ve and –ve operands, no overflow
– Adding two +ve operands
• Overflow if result sign is 1

– Adding two –ve operands
• Overflow if result sign is 0

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Integer Subtraction
• Add negation of second operand
• Example: 7 – 6 = 7 + (–6)
+7:
–6:
+1:

0000 0000 … 0000 0111
1111 1111 … 1111 1010
0000 0000 … 0000 0001

• Overflow if result out of range

– Subtracting two +ve or two –ve operands, no overflow
– Subtracting +ve from –ve operand
• Overflow if result sign is 0

– Subtracting –ve from +ve operand
• Overflow if result sign is 1

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Dealing with Overflow
• Some languages (e.g., C) ignore overflow
– Use MIPS addu, addui, subu instructions

• Other languages (e.g., Ada, Fortran) require
raising an exception
– Use MIPS add, addi, sub instructions
– On overflow, invoke exception handler
• Save PC in exception program counter (EPC) register
• Jump to predefined handler address
• mfc0 (move from coprocessor reg) instruction can
retrieve EPC value, to return after corrective action
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Arithmetic for Multimedia
• Graphics and media processing operates on
vectors of 8-bit and 16-bit data
– Use 64-bit adder, with partitioned carry chain
• Operate on 8×8-bit, 4×16-bit, or 2×32-bit vectors

– SIMD (single-instruction, multiple-data)

• Saturating operations
– On overflow, result is largest representable value
• c.f. 2s-complement modulo arithmetic

– E.g., clipping in audio, saturation in video
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Multiplication
• Start with long-multiplication approach
multiplicand
multiplier

product

1000
× 1001
1000
0000
0000
1000
1001000

Length of product is
the sum of operand
lengths

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Multiplication Hardware

Initially 0

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Example
• Using 4-bit numbers, multiply 210x310

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Optimized Multiplier
• Perform steps in parallel: add/shift

• One cycle per partial-product addition
– That’s ok, if frequency of multiplications is low
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Faster Multiplier

• Uses multiple adders
– Cost/performance tradeoff

• Can be pipelined
– Several multiplication performed in parallel
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MIPS Multiplication
• Two 32-bit registers for product
– HI: most-significant 32 bits
– LO: least-significant 32-bits

• Instructions
– mult rs, rt

/

multu rs, rt

• 64-bit product in HI/LO

– mfhi rd

/

mflo rd

• Move from HI/LO to rd
• Can test HI value to see if product overflows 32 bits

– mul rd, rs, rt
• Least-significant 32 bits of product –> rd

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Division
• Check for 0 divisor
• Long division approach

quotient

– If divisor ≤ dividend bits

dividend

1001
1000 1001010
-1000

divisor
10
101
1010
-1000
10
remainder
n-bit operands yield n-bit
quotient and remainder

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• 1 bit in quotient, subtract

– Otherwise
• 0 bit in quotient, bring down
next dividend bit

• Restoring division
– Do the subtract, and if
remainder goes < 0, add
divisor back

• Signed division
– Divide using absolute values
– Adjust sign of quotient and
remainder as required

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Division Hardware
Initially divisor
in left half

Initially dividend

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Example
• Using 4-bit numbers, let’s try dividing 710 by 210

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Optimized Divider

• One cycle per partial-remainder subtraction
• Looks a lot like a multiplier!
– Same hardware can be used for both

Dividend (initially)

Reminder (finally) Quotient (finally)
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Faster Division
• Can’t use parallel hardware as in multiplier
– Subtraction is conditional on sign of remainder

• Faster dividers (e.g. SRT division, use a backup
table instead of restoring) generate multiple
quotient bits per step
– Still require multiple steps

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MIPS Division
• Use HI/LO registers for result
– HI: 32-bit remainder
– LO: 32-bit quotient

• Instructions
– div rs, rt / divu rs, rt
– No overflow or divide-by-0 checking
• Software must perform checks if required

– Use mfhi, mflo to access result
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Floating Point
• Representation for non-integral numbers
– Including very small and very large numbers

• Like scientific notation
– –2.34 × 1056
– +0.002 × 10–4
– +987.02 × 109

normalized
not normalized

• In binary
– ±1.xxxxxxx2 × 2yyyy

• Types float and double in C
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Floating Point Standard
• Defined by IEEE Std 754-1985
• Developed in response to divergence of
representations
– Portability issues for scientific code

• Now almost universally adopted
• Two representations
– Single precision (32-bit)
– Double precision (64-bit)
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IEEE Floating-Point Format
• S: sign bit (0  non-negative, 1  negative)
• Normalize significand: 1.0 ≤ |significand| < 2.0
– Always has a leading pre-binary-point 1 bit, so no need to represent it
explicitly (hidden bit)
– Significand is Fraction with the “1.” restored

• Exponent: excess representation: actual exponent + Bias
– Ensures exponent is unsigned
– Single: Bias = 127; Double: Bias = 1203
single: 8 bits
double: 11 bits

S Exponent

single: 23 bits
double: 52 bits

Fraction

x  ( 1)S  (1 Fraction)  2(Exponent Bias)
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Single-Precision Range
• Exponents 00000000 and 11111111 reserved
• Smallest value
– Exponent: 00000001
 actual exponent = 1 – 127 = –126
– Fraction: 000…00  significand = 1.0
– ±1.0 × 2–126 ≈ ±1.2 × 10–38

• Largest value
– exponent: 11111110
 actual exponent = 254 – 127 = +127
– Fraction: 111…11  significand ≈ 2.0
– ±2.0 × 2+127 ≈ ±3.4 × 10+38
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Double-Precision Range
• Exponents 0000…00 and 1111…11 reserved
• Smallest value
– Exponent: 00000000001
 actual exponent = 1 – 1023 = –1022
– Fraction: 000…00  significand = 1.0
– ±1.0 × 2–1022 ≈ ±2.2 × 10–308

• Largest value
– Exponent: 11111111110
 actual exponent = 2046 – 1023 = +1023
– Fraction: 111…11  significand ≈ 2.0
– ±2.0 × 2+1023 ≈ ±1.8 × 10+308
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Floating-Point Precision
• Relative precision
– all fraction bits are significant
– Single: approx 2–23
• Equivalent to 23 × log102 ≈ 23 × 0.3 ≈ 6 decimal digits of
precision

– Double: approx 2–52
• Equivalent to 52 × log102 ≈ 52 × 0.3 ≈ 16 decimal digits
of precision

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Real to IEEE 754 Conversion
• Step 1: Decide S
• Step 2: Decide Fraction
– Convert the integer part to Binary
– Convert the fractional part to Binary
– Adjust the integer and fractional parts according
the Significand format (1.xxx)

• Step 3: Decide exponent

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