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2
COMPUTER SYSTEMS
ORGANIZATION

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Central processing unit (CPU)

Control
unit
Arithmetic
logical unit
(ALU)

I/O devices

Registers

…

…

Main
memory

Disk

Printer

Bus

Fig. 2-1. The organization of a simple computer with one CPU and
two I/O devices.

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A+B

A

Registers

B

A

B

ALU input register
ALU input bus

ALU

A+B

ALU output register

Fig. 2-2. The data path of a typical von Neumann machine.

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public class Interp {
static int PC;
// program counter holds address of next instr
static int AC;
// the accumulator, a register for doing arithmetic
static int instr;
// a holding register for the current instruction
static int instr type;
// the instruction type (opcode)
static int data loc;
// the address of the data, or −1 if none
static int data;
// holds the current operand
static boolean run bit = true;
// a bit that can be turned off to halt the ma

public static void interpret(int memory[ ], int starting address) {
// This procedure interprets programs for a simple machine with instructions
// one memory operand. The machine has a register AC (accumulator), used
// arithmetic. The ADD instruction adds an integer in memory to the AC, for e
// The interpreter keeps running until the run bit is turned off by the HALT ins
// The state of a process running on this machine consists of the memory, the
// program counter, the run bit, and the AC. The input parameters consist of
// of the memory image and the starting address.

PC = starting address;
while (run bit) {
instr = memory[PC]; // fetch next instruction into instr
PC = PC + 1;
// increment program counter
instr type = get instr type(instr); // determine instruction type
data loc = find data(instr, instr type);// locate data (−1 if none)
if (data loc >= 0)
// if data loc is −1, there is no operand
data = memory[data loc];
// fetch the data
execute(instr type, data);
//execute instruction
}
}
private static int get instr type(int addr) { ... }
private static int find data(int instr, int type) { ... }
private static void execute(int type, int data){ ... }
}

Fig. 2-3. An interpreter for a simple computer (written in Java).

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S1

S2

S3

S4

S5

Instruction
fetch
unit

Instruction
decode
unit

Operand
fetch
unit

Instruction
execution
unit

Write
back
unit

(a)
S1:

1

S2:

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

1

2

3

4

5

6

1

2

3

4

5

6

7

8

9

S3:
S4:
S5:
1

2

3

4
5

Time
(b)

…

Fig. 2-4. (a) A five-stage pipeline. (b) The state of each stage as a
function of time. Nine clock cycles are illustrated.

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S1

Instruction
fetch
unit

S2

S3

S4

S5

Instruction
decode
unit

Operand
fetch
unit

Instruction
execution
unit

Write
back
unit

Instruction
decode
unit

Operand
fetch
unit

Instruction
execution
unit

Write
back
unit

Fig. 2-5. (a) Dual five-stage pipelines with a common instruction
fetch unit.

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S4
ALU

ALU
S1

S2

S3

Instruction
fetch
unit

Instruction
decode
unit

Operand
fetch
unit

S5
LOAD

STORE

Floating
point

Fig. 2-6. A superscalar processor with five functional units.

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Write
back
unit


Control unit
Broadcasts instructions

8 × 8 Processor/memory grid
Processor
Memory

Fig. 2-7. An array processor of the ILLIAC IV type.

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Local memories

Shared
memory
CPU

CPU

CPU

CPU

Shared
memory
CPU

CPU

CPU

CPU

Bus
(a)

Bus
(b)

Fig. 2-8. (a) A single-bus multiprocessor. (b) A multicomputer
with local memories.

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Address

Address

1 Cell

Address

0

0

0

1

1

1

2

2

2

3

3

3

4

4

4

5

5

5

6

6

16 bits

7

7

(c)

8

12 bits

9

(b)

10
11
8 bits
(a)

Fig. 2-9. Three ways of organizing a 96-bit memory.

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Computer
Burroughs B1700
IBM PC
DEC PDP-8
IBM 1130
DEC PDP-15
XDS 940
Electrologica X8
XDS Sigma 9
Honeywell 6180
CDC 3600
CDC Cyber

Bits/cell
1
8
12
16
18
24
27
32
36
48
60

Fig. 2-10. Number of bits per cell for some historically interesting
commercial computers.

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Address

Big endian

Address

Little endian

0

0

1

2

3

3

2

1

0

0

4

4

5

6

7

7

6

5

4

4

8

8

9

10

11

11

10

9

8

8

12

12

13

14

15

15

14

13

12

12

Byte

Byte

32-bit word

32-bit word

(a)

(b)

Fig. 2-11. (a) Big endian memory. (b) Little endian memory.

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Big endian

Transfer from
big endian to
little endian

Little endian

0

J

I

M

4

S

M

I

T

8

H

0

0

12

0

16

0

M

I

J

J

I

M

T

I

M

S

S

M

I

T

4

0

0

0

H

H

0

0

0

8

12

21 0

0

0

0

0

0 21 12

16

4

0

0

0

0

1

M

I

J

0

T

I

M

S

4

0

0

0

0

H

8

0

0 21

0

0

0 21

0

1

0

0

1

(a)

4

(b)

4

Transfer and
swap

1
(c)

0

4 16

(d)

Fig. 2-12. (a) A personnel record for a big endian machine. (b)
The same record for a little endian machine. (c) The result of
transferring the record from a big endian to a little endian. (d) The
result of byte-swapping (c).

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Word size
8
16
32
64
128

256
512

Check bits Total size Percent overhead
4
12
50
5
21
31
6
38
19
7
71
11
8
136
6
9
265
4
10
522
2

Fig. 2-13. Number of check bits for a code that can correct a single
error.

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A
0
1

1

C

A

A

0

0

1

0
1

1

0

1
1

1

C

0
Parity
bits

B
(a)

1

0
0

B

C

Error

0
B
(c)

(b)

Fig. 2-14. (a) Encoding of 1100. (b) Even parity added. (c) Error

in AC.

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Memory word 1111000010101110
0
1

0
2

1
3

0
4

1
5

1
6

1
7

0
8

0 0 0 0 1 0 1 1 0 1 1 1 0
9 10 11 12 13 14 15 16 17 18 19 20 21

Parity bits

Fig. 2-15. Construction of the Hamming code for the memory
word 1111000010101110 by adding 5 check bits to the 16 data
bits.

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Main
memory
CPU
Cache

Bus
Fig. 2-16. The cache is logically between the CPU and main
memory. Physically, there are several possible places it could be
located.

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4-MB
memory

chip
Connector

Fig. 2-17. A single inline memory module (SIMM) holding 32
MB. Two of the chips control the SIMM.

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Registers
Cache

Main memory

Magnetic disk

Tape

Optical disk

Fig. 2-18. A five-level memory hierarchy.

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Intersector gap
or
ect

1s

ta bits
6 da
409

P

ble
am
re

Track
width is
5–10 microns

E
C
C

Direction
of arm
motion

Width of
1 bit is
0.1 to 0.2 microns

Dire
c

Preamb
le

Read/write
head

tion

of
d

isk

40
96
da
ta

rot
ati
on

bit
s
C

C

E

Disk
arm

Fig. 2-19. A portion of a disk track. Two sectors are illustrated.

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Read/write head (1 per surface)
Surface 7
Surface 6
Surface 5
Surface 4
Surface 3
Direction of arm motion
Surface 2
Surface 1
Surface 0

Fig. 2-20. A disk with four platters.

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Parameters
Size (inches)
Capacity (bytes)
Tracks

Sectors/track
Heads
Rotations/min
Data rate (kbps)
Type

LD 5.25′′
5.25
360K
40
9
2
300
250
Flexible

HD 5.25′′
5.25
1.2M
80
15
2
360
500
Flexible

LD 3.5′′
3.5
720K
80

9
2
300
250
Rigid

HD 3.5′′
3.5
1.44M
80
18
2
300
500
Rigid

Fig. 2-21. Characteristics of the four kinds of floppy disks.

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Name
Data bits
SCSI-1
8
Fast SCSI
8
Wide Fast SCSI
16

Ultra SCSI
8
Wide Ultra SCSI
16
Ultra2 SCSI
8
Wide Ultra2 SCSI
16

Bus MHz
5
10
10
20
20
40
40

MB/sec
5
10
20
20
40
40
80

Fig. 2-22. Some of the possible SCSI parameters.

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(a)

(b)

Strip 0

Strip 1

Strip 2

Strip 3

Strip 4

Strip 5

Strip 6

Strip 7

Strip 8

Strip 9

Strip 10

Strip 11

Strip 0

Strip 1

Strip 2

Strip 3

Strip 0

Strip 1

Strip 2

Strip 3

Strip 4

Strip 5

Strip 6

Strip 7

Strip 4

Strip 5

Strip 6

Strip 7

Strip 8

Strip 9

Strip 10

Strip 11

Strip 8

Strip 9

Strip 10

Strip 11

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

RAID level 0

(c)

RAID level 2

Bit 1

Bit 2

Bit 3

Bit 4

Parity
RAID level 3

(d)

(e)

(f)

RAID
level 1

Strip 0

Strip 1

Strip 2

Strip 3

P0-3

Strip 4

Strip 5

Strip 6

Strip 7

P4-7

Strip 8

Strip 9

Strip 10

Strip 11

P8-11

Strip 0

Strip 1

Strip 2

Strip 3

P0-3

Strip 4

Strip 5

Strip 6

P4-7

Strip 7

Strip 8

Strip 9

P8-11

Strip 10

Strip 11 RAID level 5

Strip 12

P12-15

Strip 13

Strip 14

Strip 15

P16-19

Strip 16

Strip 17

Strip 18

Strip 19

RAID level 4

Fig. 2-23. RAID levels 0 through 5. Backup and parity drives are
shown shaded.

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Spiral groove

Pit
Land

2K block of
user data

Fig. 2-24. Recording structure of a Compact Disc or CD-ROM.

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