kiến trúc máy tính dạng thanh tin figs 4 the microarchitecture level sinhvienzone com

4
THE MICROARCHITECTURE LEVEL

1

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MAR

To
and
from
main
memory

Memory
control
registers

MDR

PC

MBR

SP

LV

Control signals
Enable onto B bus

CPP

Write C bus to register
TOS

OPC
C bus

B bus
H
A

ALU control

B

6

N
Z

ALU

Shifter

Shifter control
2

Figure 4-1. The data path of the example microarchitecture used in this chapter.

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F0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0

F1
1
1
1
0

1
1
1
1
1
1
1
0
1
1
1
1

ENA
1
0
1
1
1
1
1
0
1
0
1
1
1
0
0
0

ENB
0
1
0
1
1
1
0
1
1
1
0
1
1
0
0
0

INVA
0
0
1
0
0
0
0
0
1
1

1
0
0
0
0
1

INC
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
0

Function
A
B
A
B

A+B
A+B+1
A+1
B+1
B−A
B−1
−A
A AND B
A OR B
0
1
−1

Figure 4-2. Useful combinations of ALU signals and the function performed.

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Registers loaded
instantaneously from
C bus and memory on
rising edge of clock

Shifter
output
stable

Cycle 1
starts

here

Clock cycle 1

∆w

∆x

Set up
signals
to drive
data path
Drive H
and
B bus

∆y

Clock cycle 2

New MPC used to
load MIR with next
microinstruction here

∆z

ALU
and
shifter

MPC
available
here

Propagation
from shifter
to registers

Figure 4-3. Timing diagram of one data path cycle.

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32-Bit MAR (counts in words)
Discarded
0 0

32-Bit address bus (counts in bytes)

Figure 4-4. Mapping of the bits in MAR to the address bus.

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Bits

9

3

NEXT_ADDRESS

Addr

J
M
P
C

J
A
M
N

8
J
A
M
Z

JAM

S
L
L
8

9

3

4

S F0 F1 E E I I H O T C L S P M M W R F
R
P O P V P C D A R E E
N N N N
I
T
R R T A C
A
C S P
A B V C
1
A
E D H

ALU

C

Mem

B
bus

B

B bus registers
0 = MDR
1 = PC
2 = MBR
3 = MBRU
4 = SP

5 = LV
6 = CPP
7 = TOS
8 = OPC
9 -15 none

Figure 4-5. The microinstruction format for the Mic-1.

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Memory control signals (rd, wr, fetch)
3
4
4-to-16
Decoder

MAR
MDR

MPC

9

PC
O

8

MBR
SP

512 × 36-Bit
control store
for holding
the microprogram

8

LV

JMPC

CPP

Addr

J

ALU

C

MIR
M B

TOS
JAMN/JAMZ

OPC
H

B bus

2
1-bit flip–flop

N

6
ALU
control

High
bit

ALU

Control
signals
Enable
onto

B bus

Z
Shifter
C bus

2
Write
C bus
to register

Figure 4-6. The complete block diagram of our example microarchitecture, the Mic-1.

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Address

Addr

JAM

0x75

0x92

001

Data path control bits

JAMZ bit set

…

0x92

…

0x192

One of
these
will follow
0x75
depending
on Z

Figure 4-7. A microinstruction with JAMZ set to 1 has two potential successors.

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SP
LV
SP

LV
SP
LV

a3
a2
a1
(a)

108
104
100

b4
b3
b2
b1
a3
a2
a1

c2
c1
b4
b3
b2
b1
a3
a2
a1

(b)

(c)

SP

LV

d5
d4
d3
d2
d1
a3
a2
a1
(d)

Figure 4-8. Use of a stack for storing local variables. (a)
While A is active. (b) After A calls B. (c) After B calls C. (d)
After C and B return and A calls D.

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,

,

,
SP

SP

LV

a2
a3
a2
a1

(a)

LV

a3
a2
a3
a2
a1

(b)

SP

LV

a2 + a3
a3
a2
a1
(c)

SP
LV

a3
a2
a2 + a3
(d)

Figure 4-9. Use of an operand stack for doing an arithmetic computation.

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Current
Operand
Stack 3

SP

Current
Local
Variable
Frame 3
LV
Local
Variable
Frame 2
Constant
Pool

Local
Variable
Frame 1

Method
Area

CPP

Figure 4-10. The various parts of the IJVM memory.

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PC


Hex
0x10
0x59
0xA7
0x60
0x7E
0x99
0x9B
0x9F
0x84
0x15
0xB6

0x80
0xAC
0x36
0x64
0x13
0x00
0x57
0x5F
0xC4

Mnemonic
BIPUSH byte
DUP
GOTO offset
IADD
IAND
IFEQ offset
IFLT offset
IF ICMPEQ offset
IINC varnum const
ILOAD varnum
INVOKEVIRTUAL disp
IOR
IRETURN
ISTORE varnum
ISUB
LDC W index
NOP
POP
SWAP

WIDE

Meaning
Push byte onto stack
Copy top word on stack and push onto stack
Unconditional branch
Pop two words from stack; push their sum
Pop two words from stack; push Boolean AND
Pop word from stack and branch if it is zero
Pop word from stack and branch if it is less than zero
Pop two words from stack; branch if equal
Add a constant to a local variable
Push local variable onto stack
Invoke a method
Pop two words from stack; push Boolean OR
Return from method with integer value
Pop word from stack and store in local variable
Pop two words from stack; push their difference
Push constant from constant pool onto stack
Do nothing
Delete word on top of stack
Swap the two top words on the stack
Prefix instruction; next instruction has a 16-bit index

Figure 4-11. The IJVM instruction set. The operands byte,
const, and varnum are 1 byte. The operands disp, index, and
offset are 2 bytes.

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Stack after
INVOKEVIRTUAL
Caller's LV
Caller's PC
Space for
caller's local
variables

Stack before
INVOKEVIRTUAL
Pushed
parameters

Caller's
local
variable
frame

Parameter 3
Parameter 2
Parameter 1
OBJREF
Previous LV
Previous PC

SP

Caller's

local
variables
Parameter 2
Parameter 1
Link ptr
(a)

Stack base
after
INVOKEVIRTUAL

Stack base
before
INVOKEVIRTUAL
LV

Parameter 3
Parameter 2
Parameter 1
Link ptr
Previous LV
Previous PC
Caller's
local
variables
Parameter 2
Parameter 1
Link ptr
(b)

Figure 4-12. (a) Memory before executing INVOKEVIRTUAL.
(b) After executing it.

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SP

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LV


Stack before
IRETURN
Return value
Previous LV
Previous PC

SP

Caller's
local
variables
Parameter 3
Parameter 2
Parameter 1
Link ptr
Previous LV
Previous PC
Caller's
local

variable
frame

Caller's
local
variables
Parameter 2
Parameter 1
Link ptr
(a)

Stack base
before
IRETURN
LV

Stack after
IRETURN
Return value
Previous LV
Previous PC

Stack base
after
IRETURN

SP

Caller's
local

variables
Parameter 2
Parameter 1
Link ptr

LV

(b)

Figure 4-13. (a) Memory before executing IRETURN. (b) After executing it.

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i = j + k;
if (i == 3)
k = 0;
else
j = j − 1;

(a)

1
ILOAD j // i = j + k
2
ILOAD k
3
IADD
4

ISTORE i
5
ILOAD i // if (i < 3)
6
BIPUSH 3
7
IF ICMPEQ L1
8
ILOAD j // j = j − 1
9
BIPUSH 1
10
ISUB
11
ISTORE j
12
GOTO L2
13 L1:
BIPUSH 0
14
ISTORE k
15 L2:
(b)

0x15 0x02
0x15 0x03
0x60
0x36 0x01
0x15 0x01
0x10 0x03

0x9F 0x00 0x0D
0x15 0x02
0x10 0x01
0x64
0x36 0x02
0xA7 0x00 0x07
// k = 0 0x10 0x00
0x36 0x03
(c)

Figure 4-14. (a) A Java fragment. (b) The corresponding Java
assembly language. (c) The IJVM program in hexadecimal.

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0

j
1

k
j
2

j+k
3

j

8

1
j
9

j–1
10

11

4

j
5

3
j
6

7

12

0
13

14

15

Figure 4-15. The stack after each instruction of Fig. 4-14(b).

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DEST = H
DEST = SOURCE
DEST = H
DEST = SOURCE
DEST = H + SOURCE
DEST = H + SOURCE + 1
DEST = H + 1
DEST = SOURCE + 1
DEST = SOURCE − H
DEST = SOURCE − 1
DEST = −H
DEST = H AND SOURCE
DEST = H OR SOURCE
DEST = 0
DEST = 1
DEST = −1
Figure 4-16. All permitted operations. Any of the above
operations may be extended by adding ‘‘<< 8’’ to them to shift
the result left by 1 byte. For example, a common operation is
H = MBR < < 8

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Label
Main1
nop1
iadd1
iadd2
iadd3
isub1
isub2
isub3
iand1
iand2
iand3
ior1
ior2
ior3
dup1
dup2
pop1
pop2
pop3
swap1
swap2
swap3
swap4
swap5
swap6
bipush1
bipush2

bipush3
iload1
iload2
iload3
iload4
iload5
istore1
istore2
istore3
istore4
istore5
istore6

Operations
PC = PC + 1; fetch; goto (MBR)
goto Main1
MAR = SP = SP − 1; rd
H = TOS
MDR = TOS = MDR + H; wr; goto Main1
MAR = SP = SP − 1; rd
H = TOS
MDR = TOS = MDR − H; wr; goto Main1
MAR = SP = SP − 1; rd
H = TOS
MDR = TOS = MDR AND H; wr; goto Main1
MAR = SP = SP − 1; rd
H = TOS
MDR = TOS = MDR OR H; wr; goto Main1
MAR = SP = SP + 1
MDR = TOS; wr; goto Main1

MAR = SP = SP − 1; rd
TOS = MDR; goto Main1
MAR = SP − 1; rd
MAR = SP
H = MDR; wr
MDR = TOS
MAR = SP − 1; wr
TOS = H; goto Main1
SP = MAR = SP + 1
PC = PC + 1; fetch
MDR = TOS = MBR; wr; goto Main1
H = LV
MAR = MBRU + H; rd
MAR = SP = SP + 1
PC = PC + 1; fetch; wr
TOS = MDR; goto Main1
H = LV
MAR = MBRU + H
MDR = TOS; wr
SP = MAR = SP − 1; rd
PC = PC + 1; fetch
TOS = MDR; goto Main1

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Comments
MBR holds opcode; get next byte; dispatch
Do nothing
Read in next-to-top word on stack
H = top of stack

Add top two words; write to top of stack
Read in next-to-top word on stack
H = top of stack
Do subtraction; write to top of stack
Read in next-to-top word on stack
H = top of stack
Do AND; write to new top of stack
Read in next-to-top word on stack
H = top of stack
Do OR; write to new top of stack
Increment SP and copy to MAR
Write new stack word
Read in next-to-top word on stack
Wait for new TOS to be read from memory
Copy new word to TOS
Set MAR to SP − 1; read 2nd word from stack
Set MAR to top word
Save TOS in H; write 2nd word to top of stack
Copy old TOS to MDR
Set MAR to SP − 1; write as 2nd word on stack
Update TOS
MBR = the byte to push onto stack
Increment PC, fetch next opcode
Sign-extend constant and push on stack
MBR contains index; copy LV to H
MAR = address of local variable to push
SP points to new top of stack; prepare write
Inc PC; get next opcode; write top of stack
Update TOS
MBR contains index; Copy LV to H

MAR = address of local variable to store into
Copy TOS to MDR; write word
Read in next-to-top word on stack
Increment PC; fetch next opcode
Update TOS

/>

wide1
wide iload1
wide iload2
wide iload3
wide iload4
wide istore1
wide istore2
wide istore3
wide istore4
ldc w1
ldc w2
ldc w3
ldc w4

PC = PC + 1; fetch; goto (MBR OR 0x100)
PC = PC + 1; fetch
H = MBRU << 8
H = MBRU OR H
MAR = LV + H; rd; goto iload3
PC = PC + 1; fetch
H = MBRU << 8
H = MBRU OR H

MAR = LV + H; goto istore3
PC = PC + 1; fetch
H = MBRU << 8
H = MBRU OR H
MAR = H + CPP; rd; goto iload3

Multiway branch with high bit set
MBR contains 1st index byte; fetch 2nd
H = 1st index byte shifted left 8 bits
H = 16-bit index of local variable
MAR = address of local variable to push
MBR contains 1st index byte; fetch 2nd
H = 1st index byte shifted left 8 bits
H = 16-bit index of local variable
MAR = address of local variable to store into
MBR contains 1st index byte; fetch 2nd
H = 1st index byte << 8
H = 16-bit index into constant pool
MAR = address of constant in pool

Figure 4-17. The microprogram for the Mic-1 (part 1 of 3).

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Label
iinc1
iinc2
iinc3

iinc4
iinc5
iinc6
goto1
goto2
goto3
goto4
goto5
goto6
iflt1
iflt2
iflt3
iflt4
ifeq1
ifeq2
ifeq3
ifeq4
if icmpeq1
if icmpeq2
if icmpeq3
if icmpeq4
if icmpeq5
if icmpeq6
T
F
F2
F3

Operations
Comments

H = LV
MBR contains index; Copy LV to H
MAR = MBRU + H; rd
Copy LV + index to MAR; Read variable
PC = PC + 1; fetch
Fetch constant
H = MDR
Copy variable to H
PC = PC + 1; fetch
Fetch next opcode
MDR = MBR + H; wr; goto Main1
Put sum in MDR; update variable
OPC = PC − 1
Save address of opcode.
PC = PC + 1; fetch
MBR = 1st byte of offset; fetch 2nd byte
H = MBR << 8
Shift and save signed first byte in H
H = MBRU OR H
H = 16-bit branch offset
PC = OPC + H; fetch
Add offset to OPC
goto Main1
Wait for fetch of next opcode
MAR = SP = SP − 1; rd
Read in next-to-top word on stack
OPC = TOS
Save TOS in OPC temporarily
TOS = MDR
Put new top of stack in TOS

N = OPC; if (N) goto T; else goto F
Branch on N bit
MAR = SP = SP − 1; rd
Read in next-to-top word of stack
OPC = TOS
Save TOS in OPC temporarily
TOS = MDR
Put new top of stack in TOS
Z = OPC; if (Z) goto T; else goto F
Branch on Z bit
MAR = SP = SP − 1; rd
Read in next-to-top word of stack
MAR = SP = SP − 1
Set MAR to read in new top-of-stack
H = MDR; rd
Copy second stack word to H
OPC = TOS
Save TOS in OPC temporarily
TOS = MDR
Put new top of stack in TOS
Z = OPC − H; if (Z) goto T; else goto F If top 2 words are equal, goto T, else goto F
OPC = PC − 1; fetch; goto goto2
Same as goto1; needed for target address
PC = PC + 1
Skip first offset byte
PC = PC + 1; fetch
PC now points to next opcode
goto Main1
Wait for fetch of opcode

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invokevirtual1
invokevirtual2
invokevirtual3
invokevirtual4
invokevirtual5
invokevirtual6
invokevirtual7
invokevirtual8
invokevirtual9
invokevirtual10
invokevirtual11
invokevirtual12
invokevirtual13
invokevirtual14
invokevirtual15
invokevirtual16
invokevirtual17
invokevirtual18
invokevirtual19
invokevirtual20
invokevirtual21
invokevirtual22

PC = PC + 1; fetch
H = MBRU << 8
H = MBRU OR H

MAR = CPP + H; rd
OPC = PC + 1
PC = MDR; fetch
PC = PC + 1; fetch
H = MBRU << 8
H = MBRU OR H
PC = PC + 1; fetch
TOS = SP − H
TOS = MAR = TOS + 1
PC = PC + 1; fetch
H = MBRU << 8
H = MBRU OR H
MDR = SP + H + 1; wr
MAR = SP = MDR;
MDR = OPC; wr
MAR = SP = SP + 1
MDR = LV; wr
PC = PC + 1; fetch
LV = TOS; goto Main1

MBR = index byte 1; inc. PC, get 2nd byte
Shift and save first byte in H
H = offset of method pointer from CPP
Get pointer to method from CPP area
Save Return PC in OPC temporarily
PC points to new method; get param count
Fetch 2nd byte of parameter count
Shift and save first byte in H
H = number of parameters
Fetch first byte of # locals

TOS = address of OBJREF − 1
TOS = address of OBJREF (new LV)
Fetch second byte of # locals
Shift and save first byte in H
H = # locals
Overwrite OBJREF with link pointer
Set SP, MAR to location to hold old PC
Save old PC above the local variables
SP points to location to hold old LV
Save old LV above saved PC
Fetch first opcode of new method.
Set LV to point to LV Frame

Figure 4-17. The microprogram for the Mic-1 (part 2 of 3).

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Label
ireturn1
ireturn2
ireturn3
ireturn4
ireturn5
ireturn6
ireturn7
ireturn8

Operations

MAR = SP = LV; rd

Comments
Reset SP, MAR to get link pointer
Wait for read
LV = MAR = MDR; rd
Set LV to link ptr; get old PC
MAR = LV + 1
Set MAR to read old LV
PC = MDR; rd; fetch
Restore PC; fetch next opcode
MAR = SP
Set MAR to write TOS
LV = MDR
Restore LV
MDR = TOS; wr; goto Main1 Save return value on original top of stack

Figure 4-17. The microprogram for the Mic-1 (part 3 of 3).

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BIPUSH
(0×10)

BYTE

Figure 4-18. The BIPUSH instruction format.

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ILOAD
(0x15)

INDEX

(a)

WIDE
(0xC4)

ILOAD
(0x15)

INDEX
BYTE 1

INDEX
BYTE 2

(b)

Figure 4-19. (a) ILOAD with a 1-byte index. (b) WIDE ILOAD
with a 2-byte index.

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Address
0×1FF

Control store
Microinstruction
execution order

0×115

wide_iload1

0×100

Main1

0×C4

wide1

0×15

iload1

WIDE
ILOAD ILOAD
3

1

1

2

2

0×00

Figure 4-20. The initial microinstruction sequence for ILOAD
and WIDE ILOAD. The addresses are examples.

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