Ebook Digital design (5th edition): Part 2

Chapter 6

Registers and Counters

6.1

REGISTERS
A clocked sequential circuit consists of a group of flip‐flops and combinational gates. The
flip‐flops are essential because, in their absence, the circuit reduces to a purely combinational
circuit (provided that there is no feedback among the gates). A circuit with flip‐flops is
considered a sequential circuit even in the absence of combinational gates. Circuits that
include flip‐flops are usually classified by the function they perform rather than by the name
of the sequential circuit. Two such circuits are registers and counters.
A register is a group of flip‐flops, each one of which shares a common clock and is
capable of storing one bit of information. An n‐bit register consists of a group of n
flip‐flops capable of storing n bits of binary information. In addition to the flip‐flops, a
register may have combinational gates that perform certain data‐processing tasks. In
its broadest definition, a register consists of a group of flip‐flops together with gates
that affect their operation. The flip‐flops hold the binary information, and the gates
determine how the information is transferred into the register.
A counter is essentially a register that goes through a predetermined sequence of
binary states. The gates in the counter are connected in such a way as to produce the
prescribed sequence of states. Although counters are a special type of register, it is
common to differentiate them by giving them a different name.
Various types of registers are available commercially. The simplest register is one that
consists of only flip‐flops, without any gates. Figure 6.1 shows such a register constructed
with four D‐type flip‐flops to form a four‐bit data storage register. The common clock
input triggers all flip‐flops on the positive edge of each pulse, and the binary data available
at the four inputs are transferred into the register. The value of (I3, I2, I1, I0) immediately
before the clock edge determines the value of (A3, A2, A1, A0) after the clock edge. The four
255

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Chapter 6

Registers and Counters
I0

A0

D
C

R

I1

A1

D
C

R

I2

A2

D

C

R

I3

A3

D
C

R

Clock Clear_b

FIGURE 6.1
Four‐bit register

outputs can be sampled at any time to obtain the binary information stored in the register.
The input Clear_b goes to the active‐low R (reset) input of all four flip‐flops. When this
input goes to 0, all flip‐flops are reset asynchronously. The Clear_b input is useful for clearing the register to all 0’s prior to its clocked operation. The R inputs must be maintained


Section 6.1

Registers

257

at logic 1 (i.e., de-asserted) during normal clocked operation. Note that, depending on the

flip‐flop, either Clear, Clear_b, reset, or reset_b can be used to indicate the transfer of the
register to an all 0’s state.

Register with Parallel Load
Registers with parallel load are a fundamental building block in digital systems. It is
important that you have a thorough understanding of their behavior. Synchronous digital systems have a master clock generator that supplies a continuous train of clock
pulses. The pulses are applied to all flip‐flops and registers in the system. The master
clock acts like a drum that supplies a constant beat to all parts of the system. A separate
control signal must be used to decide which register operation will execute at each clock
pulse. The transfer of new information into a register is referred to as loading or updating the register. If all the bits of the register are loaded simultaneously with a common
clock pulse, we say that the loading is done in parallel. A clock edge applied to the C
inputs of the register of Fig. 6.1 will load all four inputs in parallel. In this configuration,
if the contents of the register must be left unchanged, the inputs must be held constant
or the clock must be inhibited from the circuit. In the first case, the data bus driving the
register would be unavailable for other traffic. In the second case, the clock can be
inhibited from reaching the register by controlling the clock input signal with an enabling
gate. However, inserting gates into the clock path is ill advised because it means that
logic is performed with clock pulses. The insertion of logic gates produces uneven propagation delays between the master clock and the inputs of flip‐flops. To fully synchronize
the system, we must ensure that all clock pulses arrive at the same time anywhere in the
system, so that all flip‐flops trigger simultaneously. Performing logic with clock pulses
inserts variable delays and may cause the system to go out of synchronism. For this
reason, it is advisable to control the operation of the register with the D inputs, rather
than controlling the clock in the C inputs of the flip‐flops. This creates the effect of a
gated clock, but without affecting the clock path of the circuit.
A four‐bit data‐storage register with a load control input that is directed through gates
and into the D inputs of the flip‐flops is shown in Fig. 6.2. The additional gates implement
a two‐channel mux whose output drives the input to the register with either the data bus
or the output of the register. The load input to the register determines the action to be
taken with each clock pulse. When the load input is 1, the data at the four external inputs
are transferred into the register with the next positive edge of the clock. When the load

input is 0, the outputs of the flip‐flops are connected to their respective inputs. The feedback connection from output to input is necessary because a D flip‐flop does not have
a “no change” condition. With each clock edge, the D input determines the next state of
the register. To leave the output unchanged, it is necessary to make the D input equal to
the present value of the output (i.e., the output circulates to the input at each clock
pulse). The clock pulses are applied to the C inputs without interruption. The load input
determines whether the next pulse will accept new information or leave the information
in the register intact. The transfer of information from the data inputs or the outputs of
the register is done simultaneously with all four bits in response to a clock edge.


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Registers and Counters

Load

A0

D
I0

C

A1

D
I1
C

A2

D
I2

C

A3

D
I3

C

Clock

FIGURE 6.2
Four‐bit register with parallel load

6.2

SHIFT REGISTERS
A register capable of shifting the binary information held in each cell to its neighboring
cell, in a selected direction, is called a shift register. The logical configuration of a shift
register consists of a chain of flip‐flops in cascade, with the output of one flip‐flop connected to the input of the next flip‐flop. All flip‐flops receive common clock pulses,
which activate the shift of data from one stage to the next.
The simplest possible shift register is one that uses only flip‐flops, as shown in Fig. 6.3.
The output of a given flip‐flop is connected to the D input of the flip‐flop at its right. This
shift register is unidirectional (left‐to‐right). Each clock pulse shifts the contents of the

Section 6.2
Serial
input

SI

D

D

C

D

C

Shift Registers
SO

D

C

259

Serial
output

C

CLK

FIGURE 6.3
Four‐bit shift register

register one bit position to the right. The configuration does not support a left shift. The
serial input determines what goes into the leftmost flip‐flop during the shift. The serial
output is taken from the output of the rightmost flip‐flop. Sometimes it is necessary to
control the shift so that it occurs only with certain pulses, but not with others. As with the
data register discussed in the previous section, the clock’s signal can be suppressed by gating the clock signal to prevent the register from shifting. A preferred alternative in high‐
speed circuits is to suppress the clock action, rather than gate the clock signal, by leaving
the clock path unchanged, but recirculating the output of each register cell back through a
two‐channel mux whose output is connected to the input of the cell. When the clock action
is not suppressed, the other channel of the mux provides a datapath to the cell.
It will be shown later that the shift operation can be controlled through the D inputs of
the flip‐flops rather than through the clock input. If, however, the shift register of Fig. 6.3
is used, the shift can be controlled with an input by connecting the clock through an AND
gate. This is not a preferred practice. Note that the simplified schematics do not show a
reset signal, but such a signal is required in practical designs.

Serial Transfer
The datapath of a digital system is said to operate in serial mode when information
is transferred and manipulated one bit at a time. Information is transferred one bit at
a time by shifting the bits out of the source register and into the destination register.
This type of transfer is in contrast to parallel transfer, whereby all the bits of the
register are transferred at the same time.
The serial transfer of information from register A to register B is done with shift
registers, as shown in the block diagram of Fig. 6.4(a). The serial output (SO) of register

A is connected to the serial input (SI) of register B. To prevent the loss of information
stored in the source register, the information in register A is made to circulate by connecting the serial output to its serial input. The initial content of register B is shifted out
through its serial output and is lost unless it is transferred to a third shift register. The
shift control input determines when and how many times the registers are shifted. For
illustration here, this is done with an AND gate that allows clock pulses to pass into the
CLK terminals only when the shift control is active. (This practice can be problematic
because it may compromise the clock path of the circuit, as discussed earlier.)
Suppose the shift registers in Fig. 6.4 have four bits each. Then the control unit that
supervises the transfer of data must be designed in such a way that it enables the shift


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Registers and Counters

SIA

SOA

Shift register A

SIB

SOB

CLK

CLK

Clock
Shift
control

Shift register B

(a) Block diagram

Clock

Shift
control

CLK

T1

T2

T3

T4

(b) Timing diagram

FIGURE 6.4
Serial transfer from register A to register B

registers, through the shift control signal, for a fixed time of four clock pulses in order

to pass an entire word. This design is shown in the timing diagram of Fig. 6.4(b). The shift
control signal is synchronized with the clock and changes value just after the negative
edge of the clock. The next four clock pulses find the shift control signal in the active
state, so the output of the AND gate connected to the CLK inputs produces four pulses:
T1, T2, T3, and T4. Each rising edge of the pulse causes a shift in both registers. The
fourth pulse changes the shift control to 0, and the shift registers are disabled.
Assume that the binary content of A before the shift is 1011 and that of B is 0010.
The serial transfer from A to B occurs in four steps, as shown in Table 6.1. With the first
pulse, T1, the rightmost bit of A is shifted into the leftmost bit of B and is also circulated
into the leftmost position of A. At the same time, all bits of A and B are shifted one
position to the right. The previous serial output from B in the rightmost position is lost,
and its value changes from 0 to 1. The next three pulses perform identical operations,
shifting the bits of A into B, one at a time. After the fourth shift, the shift control goes
to 0, and registers A and B both have the value 1011. Thus, the contents of A are copied
into B, so that the contents of A remain unchanged i.e., the contents of A are restored
to their original value.
The difference between the serial and the parallel mode of operation should be apparent from this example. In the parallel mode, information is available from all bits of a
register and all bits can be transferred simultaneously during one clock pulse. In the serial


Section 6.2

Shift Registers

261

Table 6.1
Serial‐Transfer Example
Timing Pulse
Initial value

After T1
After T2
After T3
After T4

Shift Register A
1
1
1
0
1

0
1
1
1
0

1
0
1
1
1

1
1
0
1
1

Shift Register B
0
1
1
0
1

0
0
1
1
0

1
0
0
1
1

0
1
0
0
1

mode, the registers have a single serial input and a single serial output. The information
is transferred one bit at a time while the registers are shifted in the same direction.

Serial Addition
Operations in digital computers are usually done in parallel because that is a faster

mode of operation. Serial operations are slower because a datapath operation takes
several clock cycles, but serial operations have the advantage of requiring fewer hardware components. In VLSI circuits, they require less silicon area on a chip. To demonstrate the serial mode of operation, we present the design of a serial adder. The parallel
counterpart was presented in Section 4.4.
The two binary numbers to be added serially are stored in two shift registers. Beginning with the least significant pair of bits, the circuit adds one pair at a time through a
single full‐adder (FA) circuit, as shown in Fig. 6.5. The carry out of the full adder is transferred to a D flip‐flop, the output of which is then used as the carry input for the next
pair of significant bits. The sum bit from the S output of the full adder could be transferred into a third shift register. By shifting the sum into A while the bits of A are shifted
out, it is possible to use one register for storing both the augend and the sum bits. The
serial input of register B can be used to transfer a new binary number while the addend
bits are shifted out during the addition.
The operation of the serial adder is as follows: Initially, register A holds the augend,
register B holds the addend, and the carry flip‐flop is cleared to 0. The outputs (SO) of A
and B provide a pair of significant bits for the full adder at x and y. Output Q of the flip‐flop
provides the input carry at z. The shift control enables both registers and the carry flip‐flop,
so at the next clock pulse, both registers are shifted once to the right, the sum bit from S
enters the leftmost flip‐flop of A, and the output carry is transferred into flip‐flop Q. The
shift control enables the registers for a number of clock pulses equal to the number of bits
in the registers. For each succeeding clock pulse, a new sum bit is transferred to A, a new
carry is transferred to Q, and both registers are shifted once to the right. This process continues until the shift control is disabled. Thus, the addition is accomplished by passing each
pair of bits together with the previous carry through a single full‐adder circuit and transferring the sum, one bit at a time, into register A.
Initially, register A and the carry flip‐flop are cleared to 0, and then the first number
is added from B. While B is shifted through the full adder, a second number is transferred


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Chapter 6

Registers and Counters

Shift

control
CLK

SI
SO
Shift register A
(Augend)
x
y

Serial
input

S
FA
C

z

SI
SO
Shift register B
(Addend)

Q
D

C
Clear

FIGURE 6.5
Serial adder

to it through its serial input. The second number is then added to the contents of register
A, while a third number is transferred serially into register B. This can be repeated to
perform the addition of two, three, or more four‐bit numbers and accumulate their sum
in register A.
Comparing the serial adder with the parallel adder described in Section 4.4, we note
several differences. The parallel adder uses registers with a parallel load, whereas the
serial adder uses shift registers. The number of full‐adder circuits in the parallel adder
is equal to the number of bits in the binary numbers, whereas the serial adder requires
only one full‐adder circuit and a carry flip‐flop. Excluding the registers, the parallel
adder is a combinational circuit, whereas the serial adder is a sequential circuit which
consists of a full adder and a flip‐flop that stores the output carry. This design is typical
in serial operations because the result of a bit‐time operation may depend not only on
the present inputs, but also on previous inputs that must be stored in flip‐flops.
To show that serial operations can be designed by means of sequential circuit procedure, we will redesign the serial adder with the use of a state table. First, we assume that
two shift registers are available to store the binary numbers to be added serially. The
serial outputs from the registers are designated by x and y. The sequential circuit to
be designed will not include the shift registers, but they will be inserted later to show
the complete circuit. The sequential circuit proper has the two inputs, x and y, that
provide a pair of significant bits, an output S that generates the sum bit, and flip‐flop
Q for storing the carry. The state table that specifies the sequential circuit is listed in
Table 6.2. The present state of Q is the present value of the carry. The present carry in


Section 6.2

Shift Registers

263

Table 6.2
State Table for Serial Adder
Present State

Inputs

Next State

Output

Flip‐Flop Inputs

Q

x

y

Q

S

JQ

KQ

0
0

0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
0

1
1
1

0
1
1
0
1
0
0
1

0
0
0
1
X
X
X
X

X
X
X
X
1
0
0
0

Q is added together with inputs x and y to produce the sum bit in output S. The next
state of Q is equal to the output carry. Note that the state table entries are identical
to the entries in a full‐adder truth table, except that the input carry is now the present
state of Q and the output carry is now the next state of Q.
If a D flip‐flop is used for Q, the circuit reduces to the one shown in Fig. 6.5. If a JK flip‐
flop is used for Q, it is necessary to determine the values of inputs J and K by referring to
the excitation table (Table 5.12). This is done in the last two columns of Table 6.2. The two
flip‐flop input equations and the output equation can be simplified by means of maps to
JQ = xy
KQ = xЈyЈ = (x + y)Ј
S = x{y{Q
The circuit diagram is shown in Fig. 6.6. The circuit consists of three gates and a JK
flip‐flop. The two shift registers are included in the diagram to show the complete serial
adder. Note that output S is a function not only of x and y, but also of the present state
of Q. The next state of Q is a function of the present state of Q and of the values of x
and y that come out of the serial outputs of the shift registers.

Universal Shift Register
If the flip‐flop outputs of a shift register are accessible, then information entered serially
by shifting can be taken out in parallel from the outputs of the flip‐flops. If a parallel
load capability is added to a shift register, then data entered in parallel can be taken out
in serial fashion by shifting the data stored in the register.
Some shift registers provide the necessary input and output terminals for parallel
transfer. They may also have both shift‐right and shift‐left capabilities. The most general
shift register has the following capabilities:
1. A clear control to clear the register to 0.
2. A clock input to synchronize the operations.

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Chapter 6

Shift
control
CLK

Serial
input

Registers and Counters

SI
SO
Shift register A

x

SO
SI
Shift register B

y

S

J
C
K

Clear

FIGURE 6.6
Second form of serial adder

3. A shift‐right control to enable the shift‐right operation and the serial input and
output lines associated with the shift right.
4. A shift‐left control to enable the shift‐left operation and the serial input and output
lines associated with the shift left.
5. A parallel‐load control to enable a parallel transfer and the n input lines associated with the parallel transfer.
6. n parallel output lines.
7. A control state that leaves the information in the register unchanged in response
to the clock. Other shift registers may have only some of the preceding functions,
with at least one shift operation.
A register capable of shifting in one direction only is a unidirectional shift register.
One that can shift in both directions is a bidirectional shift register. If the register has
both shifts and parallel‐load capabilities, it is referred to as a universal shift register.
The block diagram symbol and the circuit diagram of a four‐bit universal shift register
that has all the capabilities just listed are shown in Fig. 6.7. The circuit consists of four D
flip‐flops and four multiplexers. The four multiplexers have two common selection inputs
s1 and s0. Input 0 in each multiplexer is selected when s1s0 = 00, input 1 is selected when
s1s0 = 01, and similarly for the other two inputs. The selection inputs control the mode
of operation of the register according to the function entries in Table 6.3. When s1s0 = 00,
the present value of the register is applied to the D inputs of the flip‐flops. This condition
forms a path from the output of each flip‐flop into the input of the same flip‐flop, so that
the output recirculates to the input in this mode of operation. The next clock edge transfers into each flip‐flop the binary value it held previously, and no change of state occurs.


Section 6.2

Shift Registers

265

A_ par
s1
s0

4

MSB_in

Shift_Register

CLK
Clear_b

LSB_in

4
I_par
(a)
Parallel outputs

Clear_b

C

A3

A2

A1

A0

Q

Q

Q

Q

D

C

C

D

D

C

D

CLK

y
s1

y

y

y

4ϫ1
MUX

4ϫ1
MUX

4ϫ1
MUX

4ϫ1
MUX

3 2 1 0

3 2 1 0

3 2 1 0

3 2 1 0

s0

Serial
input for
shift-right
I3

Serial
input for
shift-left
I2

I1
Parallel inputs
(b)

FIGURE 6.7
Four‐bit universal shift register

I0


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Chapter 6

Registers and Counters
Table 6.3
Function Table for the Register of Fig. 6.7
Mode Control

s1

s0

Register Operation

0
0
1
1

0
1
0
1

No change
Shift right
Shift left
Parallel load

When s1s0 = 01, terminal 1 of the multiplexer inputs has a path to the D inputs of the
flip‐flops. This causes a shift‐right operation, with the serial input transferred into flip‐flop
A3. When s1s0 = 10, a shift‐left operation results, with the other serial input going into
flip‐flop A0. Finally, when s1s0 = 11, the binary information on the parallel input lines is
transferred into the register simultaneously during the next clock edge. Note that data
enters MSB_in for a shift‐right operation and enters LSB_in for a shift‐left operation.
Clear_b is an active‐low signal that clears all of the flip‐flops.
Shift registers are often used to interface digital systems situated remotely from each
other. For example, suppose it is necessary to transmit an n‐bit quantity between two

points. If the distance is far, it will be expensive to use n lines to transmit the n bits in
parallel. It is more economical to use a single line and transmit the information serially,
one bit at a time. The transmitter accepts the n‐bit data in parallel into a shift register
and then transmits the data serially along the common line. The receiver accepts the
data serially into a shift register. When all n bits are received, they can be taken from
the outputs of the register in parallel. Thus, the transmitter performs a parallel‐to‐serial
conversion of data and the receiver does a serial‐to‐parallel conversion.

6.3

RIPPLE COUNTERS
A register that goes through a prescribed sequence of states upon the application of input
pulses is called a counter. The input pulses may be clock pulses, or they may originate
from some external source and may occur at a fixed interval of time or at random. The
sequence of states may follow the binary number sequence or any other sequence of
states. A counter that follows the binary number sequence is called a binary counter. An
n‐bit binary counter consists of n flip‐flops and can count in binary from 0 through 2n - 1.
Counters are available in two categories: ripple counters and synchronous counters.
In a ripple counter, a flip‐flop output transition serves as a source for triggering other
flip‐flops. In other words, the C input of some or all flip‐flops are triggered, not by the
common clock pulses, but rather by the transition that occurs in other flip‐flop outputs.
In a synchronous counter, the C inputs of all flip‐flops receive the common clock.
Synchronous counters are presented in the next two sections. Here, we present the
binary and BCD ripple counters and explain their operation.


Section 6.3

Ripple Counters

267

Binary Ripple Counter
A binary ripple counter consists of a series connection of complementing flip‐flops, with
the output of each flip‐flop connected to the C input of the next higher order flip‐flop.
The flip‐flop holding the least significant bit receives the incoming count pulses. A complementing flip‐flop can be obtained from a JK flip‐flop with the J and K inputs tied
together or from a T flip‐flop. A third possibility is to use a D flip‐flop with the complement
output connected to the D input. In this way, the D input is always the complement of
the present state, and the next clock pulse will cause the flip‐flop to complement. The
logic diagram of two 4‐bit binary ripple counters is shown in Fig. 6.8. The counter is constructed with complementing flip‐flops of the T type in part (a) and D type in part (b).
The output of each flip‐flop is connected to the C input of the next flip‐flop in sequence.
The flip‐flop holding the least significant bit receives the incoming count pulses. The T
inputs of all the flip‐flops in (a) are connected to a permanent logic 1, making each flip‐
flop complement if the signal in its C input goes through a negative transition. The bubble in front of the dynamic indicator symbol next to C indicates that the flip‐flops respond
to the negative‐edge transition of the input. The negative transition occurs when the
output of the previous flip‐flop to which C is connected goes from 1 to 0.
To understand the operation of the four‐bit binary ripple counter, refer to the first
nine binary numbers listed in Table 6.4. The count starts with binary 0 and increments
by 1 with each count pulse input. After the count of 15, the counter goes back to 0 to
repeat the count. The least significant bit, A0, is complemented with each count pulse
input. Every time that A0 goes from 1 to 0, it complements A1. Every time that A1 goes
from 1 to 0, it complements A2. Every time that A2 goes from 1 to 0, it complements A3,
and so on for any other higher order bits of a ripple counter. For example, consider the
transition from count 0011 to 0100. A0 is complemented with the count pulse. Since A0
goes from 1 to 0, it triggers A1 and complements it. As a result, A1 goes from 1 to 0, which
in turn complements A2, changing it from 0 to 1. A2 does not trigger A3, because A2
produces a positive transition and the flip‐flop responds only to negative transitions.
Thus, the count from 0011 to 0100 is achieved by changing the bits one at a time, so the
Table 6.4
Binary Count Sequence

A3

A2

A1

A0

0
0
0
0
0
0
0
0
1

0
0
0
0
1
1
1
1
0

0
0

1
1
0
0
1
1
0

0
1
0
1
0
1
0
1
0


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Registers and Counters

A0

T

C

Count

A1

T

C

R

A2

D

C

R

A3

C

A1

C

A2

T

R

D

R

T

C

C

Count

R

A0

D

R

A3

D

C

R

R

Logic 1
Reset

Reset
(a) With T flip-flops

FIGURE 6.8
Four‐bit binary ripple counter

(b) With D flip-flops


Section 6.3

Ripple Counters

269

count goes from 0011 to 0010, then to 0000, and finally to 0100. The flip‐flops change
one at a time in succession, and the signal propagates through the counter in a ripple
fashion from one stage to the next.
A binary counter with a reverse count is called a binary countdown counter. In a
countdown counter, the binary count is decremented by 1 with every input count pulse.
The count of a four‐bit countdown counter starts from binary 15 and continues to binary
counts 14, 13, 12, . . . , 0 and then back to 15. A list of the count sequence of a binary
countdown counter shows that the least significant bit is complemented with every count
pulse. Any other bit in the sequence is complemented if its previous least significant bit

goes from 0 to 1. Therefore, the diagram of a binary countdown counter looks the same
as the binary ripple counter in Fig. 6.8, provided that all flip‐flops trigger on the positive
edge of the clock. (The bubble in the C inputs must be absent.) If negative‐edge‐triggered
flip‐flops are used, then the C input of each flip‐flop must be connected to the complemented output of the previous flip‐flop. Then, when the true output goes from 0 to 1, the
complement will go from 1 to 0 and complement the next flip‐flop as required.

BCD Ripple Counter
A decimal counter follows a sequence of 10 states and returns to 0 after the count of 9.
Such a counter must have at least four flip‐flops to represent each decimal digit, since
a decimal digit is represented by a binary code with at least four bits. The sequence of
states in a decimal counter is dictated by the binary code used to represent a decimal
digit. If BCD is used, the sequence of states is as shown in the state diagram of Fig. 6.9.
A decimal counter is similar to a binary counter, except that the state after 1001 (the
code for decimal digit 9) is 0000 (the code for decimal digit 0).
The logic diagram of a BCD ripple counter using JK flip‐flops is shown in Fig. 6.10.
The four outputs are designated by the letter symbol Q, with a numeric subscript equal
to the binary weight of the corresponding bit in the BCD code. Note that the output of
Q1 is applied to the C inputs of both Q2 and Q8 and the output of Q2 is applied to the
C input of Q4. The J and K inputs are connected either to a permanent 1 signal or to
outputs of other flip‐flops.
A ripple counter is an asynchronous sequential circuit. Signals that affect the flip‐flop
transition depend on the way they change from 1 to 0. The operation of the counter can

0000

0001

0010

0011

0100

1001

1000

0111

0110

0101

FIGURE 6.9
State diagram of a decimal BCD counter


270

Chapter 6

Registers and Counters
Q1

J
Count

C
K

Q2

J
C
K

Q4

J
C
K

Q8

J
C
K

Logic 1

FIGURE 6.10
BCD ripple counter

be explained by a list of conditions for flip‐flop transitions. These conditions are derived from the logic diagram and from knowledge of how a
JK flip‐flop operates. Remember that when the C input goes from 1 to 0,
the flip‐flop is set if J = 1, is cleared if K = 1, is complemented if
J = K = 1, and is left unchanged if J = K = 0.


Section 6.4

Synchronous Counters

Q8 Q4 Q2 Q1

Q8 Q4 Q2 Q1

Q8 Q4 Q2 Q1

BCD
Counter

BCD
Counter

BCD
Counter

102 digit

101 digit

100 digit

271

Count
pulses

FIGURE 6.11

Block diagram of a three‐decade decimal BCD counter

To verify that these conditions result in the sequence required by a BCD ripple counter, it is necessary to verify that the flip‐flop transitions indeed follow a sequence of
states as specified by the state diagram of Fig. 6.9. Q1 changes state after each clock
pulse. Q2 complements every time Q1 goes from 1 to 0, as long as Q8 = 0. When Q8
becomes 1, Q2 remains at 0. Q4 complements every time Q2 goes from 1 to 0. Q8 remains
at 0 as long as Q2 or Q4 is 0. When both Q2 and Q4 become 1, Q8 complements when Q1
goes from 1 to 0. Q8 is cleared on the next transition of Q1.
The BCD counter of Fig. 6.10 is a decade counter, since it counts from 0 to 9. To
count in decimal from 0 to 99, we need a two‐decade counter. To count from 0 to 999,
we need a three‐decade counter. Multiple decade counters can be constructed by connecting BCD counters in cascade, one for each decade. A three‐decade counter is
shown in Fig. 6.11. The inputs to the second and third decades come from Q8 of the
previous decade. When Q8 in one decade goes from 1 to 0, it triggers the count for the
next higher order decade while its own decade goes from 9 to 0.

6.4

SYNCHRONOUS COUNTERS
Synchronous counters are different from ripple counters in that clock pulses are applied
to the inputs of all flip‐flops. A common clock triggers all flip‐flops simultaneously,
rather than one at a time in succession as in a ripple counter. The decision whether a
flip‐flop is to be complemented is determined from the values of the data inputs, such
as T or J and K at the time of the clock edge. If T = 0 or J = K = 0, the flip‐flop does
not change state. If T = 1 or J = K = 1, the flip‐flop complements.
The design procedure for synchronous counters was presented in Section 5.8, and the
design of a three‐bit binary counter was carried out in conjunction with Fig. 5.31. In this
section, we present some typical synchronous counters and explain their operation.

Binary Counter
The design of a synchronous binary counter is so simple that there is no need to go

through a sequential logic design process. In a synchronous binary counter, the flip‐flop
in the least significant position is complemented with every pulse. A flip‐flop in any other


272

Chapter 6

Registers and Counters

position is complemented when all the bits in the lower significant positions are equal to 1.
For example, if the present state of a four‐bit counter is A3A2A1A0 = 0011, the next
count is 0100. A0 is always complemented. A1 is complemented because the present
state of A0 = 1. A2 is complemented because the present state of A1A0 = 11. However,
A3 is not complemented, because the present state of A2A1A0 = 011, which does not
give an all‐1’s condition.
Synchronous binary counters have a regular pattern and can be constructed with
complementing flip‐flops and gates. The regular pattern can be seen from the four‐bit
counter depicted in Fig. 6.12. The C inputs of all flip‐flops are connected to a common
clock. The counter is enabled by Count_enable. If the enable input is 0, all J and K inputs
are equal to 0 and the clock does not change the state of the counter. The first stage,
A0, has its J and K equal to 1 if the counter is enabled. The other J and K inputs are
equal to 1 if all previous least significant stages are equal to 1 and the count is enabled.
The chain of AND gates generates the required logic for the J and K inputs in each
stage. The counter can be extended to any number of stages, with each stage having an
additional flip‐flop and an AND gate that gives an output of 1 if all previous flip‐flop
outputs are 1.
Note that the flip‐flops trigger on the positive edge of the clock. The polarity of the
clock is not essential here, but it is with the ripple counter. The synchronous counter can
be triggered with either the positive or the negative clock edge. The complementing

flip‐flops in a binary counter can be of either the JK type, the T type, or the D type with
XOR gates. The equivalency of the three types is indicated in Fig. 5.13.

Up–Down Binary Counter
A synchronous countdown binary counter goes through the binary states in reverse order,
from 1111 down to 0000 and back to 1111 to repeat the count. It is possible to design a
countdown counter in the usual manner, but the result is predictable by inspection of the
downward binary count. The bit in the least significant position is complemented with each
pulse. A bit in any other position is complemented if all lower significant bits are equal to 0.
For example, the next state after the present state of 0100 is 0011. The least significant
bit is always complemented. The second significant bit is complemented because the first
bit is 0. The third significant bit is complemented because the first two bits are equal to 0.
But the fourth bit does not change, because not all lower significant bits are equal to 0.
A countdown binary counter can be constructed as shown in Fig. 6.12, except that
the inputs to the AND gates must come from the complemented outputs, instead of
the normal outputs, of the previous flip‐flops. The two operations can be combined in
one circuit to form a counter capable of counting either up or down. The circuit of an
up–down binary counter using T flip‐flops is shown in Fig. 6.13. It has an up control
input and a down control input. When the up input is 1, the circuit counts up, since the
T inputs receive their signals from the values of the previous normal outputs of the
flip‐flops. When the down input is 1 and the up input is 0, the circuit counts down,
since the complemented outputs of the previous flip‐flops are applied to the T inputs.
When the up and down inputs are both 0, the circuit does not change state and remains


Section 6.4

Synchronous Counters
A0

J
C
Count_enable

K

A1

J
C
K

A2

J
C
K

A3

J
C
K

To next stage

CLK

FIGURE 6.12
Four‐bit synchronous binary counter

273


274

Chapter 6

Registers and Counters

Up

A0

T
Down
C

A1

T
C

A2

T
C

A3

T
C

CLK

FIGURE 6.13
Four‐bit up–down binary counter


Section 6.4

Synchronous Counters

275

in the same count. When the up and down inputs are both 1, the circuit counts up. This
set of conditions ensures that only one operation is performed at any given time. Note
that the up input has priority over the down input.

BCD Counter
A BCD counter counts in binary‐coded decimal from 0000 to 1001 and back to 0000.
Because of the return to 0 after a count of 9, a BCD counter does not have a regular
pattern, unlike a straight binary count. To derive the circuit of a BCD synchronous
counter, it is necessary to go through a sequential circuit design procedure.
The state table of a BCD counter is listed in Table 6.5. The input conditions for the
T flip‐flops are obtained from the present‐ and next‐state conditions. Also shown in the
table is an output y, which is equal to 1 when the present state is 1001. In this way, y can
enable the count of the next‐higher significant decade while the same pulse switches the
present decade from 1001 to 0000.
The flip‐flop input equations can be simplified by means of maps. The unused states

for minterms 10 to 15 are taken as don’t‐care terms. The simplified functions are
TQ1
TQ2
TQ4
TQ8
y

=
=
=
=
=

1
QЈ8Q1
Q2Q1
Q8Q1 + Q4Q2Q1
Q8Q1

The circuit can easily be drawn with four T flip‐flops, five AND gates, and one OR
gate. Synchronous BCD counters can be cascaded to form a counter for decimal numbers
of any length. The cascading is done as in Fig. 6.11, except that output y must be connected to the count input of the next‐higher significant decade.
Table 6.5
State Table for BCD Counter
Present State

Next State

Output

Flip‐Flop Inputs

Q8

Q4

Q2

Q1

Q8

Q4

Q2

Q1

y

TQ8

TQ4

TQ2

TQ1

0
0

0
0
0
0
0
0
1
1

0
0
0
0
1
1
1
1
0
0

0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
1
1
0

0
0
0
1
1
1
1

0
0
0

0
1
1
0
0
1
1
0
0
0

1
0
1
0
1
0
1
0
1
0

0
0
0
0

0
0
0
0
0
1

0
0
0
0
0
0
0
1
0
1

0
0
0
1
0
0
0
1
0
0

0

1
0
1
0
1
0
1
0
0

1
1
1
1
1
1
1
1
1
1


276

Chapter 6

Registers and Counters

Binary Counter with Parallel Load
Counters employed in digital systems quite often require a parallel‐load capability for

transferring an initial binary number into the counter prior to the count operation.
Figure 6.14 shows the top‐level block diagram symbol and the logic diagram of a four‐bit
register that has a parallel load capability and can operate as a counter. When equal to
1, the input load control disables the count operation and causes a transfer of data from
the four data inputs into the four flip‐flops. If both control inputs are 0, clock pulses do
not change the state of the register.
The carry output becomes a 1 if all the flip‐flops are equal to 1 while the count input is
enabled. This is the condition for complementing the flip‐flop that holds the next significant
bit. The carry output is useful for expanding the counter to more than four bits. The speed
of the counter is increased when the carry is generated directly from the outputs of all four
flip‐flops, because the delay to generate the carry bit is reduced. In going from state 1111
to 0000, only one gate delay occurs, whereas four gate delays occur in the AND gate chain
shown in Fig. 6.12. Similarly, each flip‐flop is associated with an AND gate that receives all
previous flip‐flop outputs directly instead of connecting the AND gates in a chain.
The operation of the counter is summarized in Table 6.6. The four control inputs—
Clear, CLK, Load, and Count—determine the next state. The Clear input is asynchronous and, when equal to 0, causes the counter to be cleared regardless of the presence
of clock pulses or other inputs. This relationship is indicated in the table by the X entries,
which symbolize don’t‐care conditions for the other inputs. The Clear input must be in
the 1 state for all other operations. With the Load and Count inputs both at 0, the outputs do not change, even when clock pulses are applied. A Load input of 1 causes a
transfer from inputs I0 - I3 into the register during a positive edge of CLK. The input
data are loaded into the register regardless of the value of the Count input, because the
Count input is inhibited when the Load input is enabled. The Load input must be 0 for
the Count input to control the operation of the counter.
A counter with a parallel load can be used to generate any desired count sequence.
Figure 6.15 shows two ways in which a counter with a parallel load is used to generate
the BCD count. In each case, the Count control is set to 1 to enable the count through
the CLK input. Also, recall that the Load control inhibits the count and that the clear
operation is independent of other control inputs.
The AND gate in Fig. 6.15(a) detects the occurrence of state 1001. The counter is
initially cleared to 0, and then the Clear and Count inputs are set to 1, so the counter is

active at all times. As long as the output of the AND gate is 0, each positive‐edge clock
Table 6.6
Function Table for the Counter of Fig. 6.14
Clear

CLK

Load

Count

0
1

X

X
1

X
X

Clear to 0
Load inputs

0

1

Count next binary state

0

0

No change

1
1

c
c
c

Function


Section 6.4

Synchronous Counters

277

Count
Load

Data_in

A_count

4-Bit Binary Counter
4

4

Clear
CLK

C_out
(a)

Count

Load

I0

A0

J
C
K

I1

A1

J
C
K

I2

A2

J
C
K

I3

A3

J
C
K

Clear
CLK
C_out
(b)

FIGURE 6.14
Four‐bit binary counter with parallel load


278

Chapter 6

Registers and Counters
A3 A2 A1 A0

A3 A2 A1 A0

Count ϭ 1

Load
Counter
of Fig. 6.14

Clear ϭ 1

Count ϭ 1

Clear
Counter
of Fig. 6.14

CLK
Inputs ϭ 0
(a) Using the load input

Load ϭ 0
CLK

Inputs have no effect
(b) Using the clear input

FIGURE 6.15

Two ways to achieve a BCD counter using a counter with parallel load

increments the counter by 1. When the output reaches the count of 1001, both A0 and
A3 become 1, making the output of the AND gate equal to 1. This condition activates
the Load input; therefore, on the next clock edge the register does not count, but is
loaded from its four inputs. Since all four inputs are connected to logic 0, an all‐0’s value
is loaded into the register following the count of 1001. Thus, the circuit goes through the
count from 0000 through 1001 and back to 0000, as is required in a BCD counter.
In Fig. 6.15(b), the NAND gate detects the count of 1010, but as soon as this count
occurs, the register is cleared. The count 1010 has no chance of staying on for any appreciable time, because the register goes immediately to 0. A momentary spike occurs in
output A0 as the count goes from 1010 to 1011 and immediately to 0000. The spike may
be undesirable, and for that reason, this configuration is not recommended. If the counter has a synchronous clear input, it is possible to clear the counter with the clock after
an occurrence of the 1001 count.

6.5

OTHER COUNTERS
Counters can be designed to generate any desired sequence of states. A divide‐by‐N
counter (also known as a modulo‐N counter) is a counter that goes through a repeated
sequence of N states. The sequence may follow the binary count or may be any other
arbitrary sequence. Counters are used to generate timing signals to control the sequence
of operations in a digital system. Counters can also be constructed by means of shift
registers. In this section, we present a few examples of nonbinary counters.

Counter with Unused States
A circuit with n flip‐flops has 2n binary states. There are occasions when a sequential
circuit uses fewer than this maximum possible number of states. States that are not used


Section 6.5

Other Counters

279

in specifying the sequential circuit are not listed in the state table. In simplifying the
input equations, the unused states may be treated as don’t‐care conditions or may be
assigned specific next states. It is important to realize that once the circuit is designed
and constructed, outside interference during its operation may cause the circuit to enter
one of the unused states. In that case, it is necessary to ensure that the circuit eventually
goes into one of the valid states so that it can resume normal operation. Otherwise, if the
sequential circuit circulates among unused states, there will be no way to bring it back to
its intended sequence of state transitions. If the unused states are treated as don’t‐care
conditions, then once the circuit is designed, it must be investigated to determine the
effect of the unused states. The next state from an unused state can be determined from
the analysis of the circuit after it is designed.
As an illustration, consider the counter specified in Table 6.7. The count has a
repeated sequence of six states, with flip‐flops B and C repeating the binary count 00,
01, 10, and flip‐flop A alternating between 0 and 1 every three counts. The count
sequence of the counter is not straight binary, and two states, 011 and 111, are not
included in the count. The choice of JK flip‐flops results in the flip‐flop input conditions
listed in the table. Inputs KB and KC have only 1’s and X’s in their columns, so these
inputs are always equal to 1. The other flip‐flop input equations can be simplified by
using minterms 3 and 7 as don’t‐care conditions. The simplified equations are
JA = B
JB = C
JC = BЈ

KA = B
KB = 1

KC = 1

The logic diagram of the counter is shown in Fig. 6.16(a). Since there are two unused
states, we analyze the circuit to determine their effect. If the circuit happens to be in
state 011 because of an error signal, the circuit goes to state 100 after the application of
a clock pulse. This action may be determined from an inspection of the logic diagram by
noting that when B = 1, the next clock edge complements A and clears C to 0, and when
C = 1, the next clock edge complements B. In a similar manner, we can evaluate the
next state from present state 111 to be 000.

Table 6.7
State Table for Counter
Present State

Next State

Flip‐Flop Inputs

A

B

C

A

B

C

JA

KA

JB

KB

JC

KC

0
0
0
1
1
1

0
0
1
0
0
1

0
1
0
0

1
0

0
0
1
1
1
0

0
1
0
0
1
0

1
0
0
1
0
0

0
0
1
X
X
X

X
X
X
0
0
1

0
1
X
0
1
X

X
X
1
X
X
1

1
X
0
1
X
0

X

1
X
X
1
X