H8-300H Instructions and Addressing Mode

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Chapter 5
H8/300H Instructions and Addressing Mode



Although programs were developed using simple instructions in
Chapter 4, many other instructions are available for the H8/300H. In this
chapter, all instructions for the H8/300H are listed in easy-to-understand tables.
Some instructions frequently appear in programs while others are hardly used.
At this stage, how to use each instruction is not described in detail. It does not
matter if you do not understand some points. Detailed explanations are given in
the next chapter, where sample programs are introduced.
Since developing programs require frequent reference to the
"instruction table", you should learn how to read the table at this stage.





5.1 Instructions

Instruction types
This section lists instructions provided in the H8/300H CPU. Not only
instructions but all descriptions in this chapter are common to the entire
H8/300H series including the H8/3048.

Data transfer instructions
Arithmetic instructions Logical instructions
Conditional branch

instructions
Unconditional branch instructions Bit handling instructions
Shift/Rotate instructions
Block transfer instructions System control instructions

- Data transfer instructions
Instruction Meaning Description Sample program
MOV
MOVe data Data transfer
PUSH
PUSH data Stores data in the stack -
POP
POP data Restores data from the stack -

- Arithmetic instructions
Instruction Meaning Description Sample program
ADD
ADD binary Binary addition
SUB
SUBtract binary Binary subtraction -
ADDX
ADD with eXtend carry Binary addition with a carry -
SUBX
SUBtract with eXtend carry Binary subtraction with a carry -
INC
INCrement Increment
DEC
DECrement Decrement

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ADDS
ADD with Sign extension Binary address data addition
SUBS
SUBtract with Sign extension Binary address data subtraction -
DAA
Decimal Adjust Add Decimal adjustment (addition) -
DAS
Decimal Adjust Subtract Decimal adjustment (subtraction) -
MULXU
MULtiply eXtend as Unsigned Unsigned multiplication
MULXS
MULtiply eXtend as Signed Signed multiplication
DIVXU
DIVide eXtend as Unsigned Unsigned division
DIVXS
DIVide eXtend as Signed Signed division
CMP
CoMPare Comparison
NEG
NEGate Sign change -
EXTS
EXTend as Signed Signed extension -
EXTU
EXTend as Unsigned Unsigned extension

- Logical instructions
Instruction Meaning Description Sample program
AND
AND logical Logical product
OR

inclusive OR logical Logical sum
XOR
eXclusive OR logical Exclusive logical sum
NOT
NOT (logical complement) Logical negation -

- Conditional branch instructions
Instruction Meaning Description Sample
program
BHI
Branch HIgh Branches if larger (unsigned) -
BLS
Branch Low or Same Branches if smaller or the same (unsigned) -
BCC
(BHS)
Branch Carry Clear
Branch High or Same
Branches if no carry occurs (unsigned)

BCS
(BLO)
Branch Carry Set
Branch LOw
Branches if a carry occurs (unsigned) -
BNE
Branch Not Equal Branches if not equal
BEQ
Branch EQual Branches if equal -
BVC
Branch oVerflow Clear Branches if no overflow occurs -

BVS
Branch oVerflow Set Branches if an overflow occurs -
BPL
Branch PLus Branches if positive -
BMI
Branch MInus Branches if negative -
BGE
Branch Greater or Equal Branches if larger or the same (signed) -
BLT
Branch Less Than Branches if smaller (signed) -
BGT
Branch Greater Than Branches if larger (signed) -
BLE
Branch Less or Equal Branches if smaller or the same (signed) -

- Unconditional branch instructions
Instruction Meaning Description Sample program
JMP
JuMP Unconditional jump -
JSR
Jump to SubRoutine Jumps to a subroutine
BRA
BRanch Always Unconditional branch

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BSR
Branch to SubRoutine Branches to a subroutine
-
RTS
ReTurn from Subroutine

Returns from a
subroutine


- Bit handling instructions
Instruction Meaning Description Sample program
BSET
Bit SET Sets one bit
BCLR
Bit CLeaR Clears one bit
BNOT
Bit NOT Inverts one bit
BTST
Bit TeST 1-bit test
BAND
Bit AND 1-bit logical product -
BIAND
Bit Invert AND 1-bit inversion and logical product -
BOR
Bit inclusive OR 1-bit logical sum -
BIOR
Bit Invert OR 1-bit inversion and logical sum -
BXOR
Bit eXclusive OR Exclusive logical sum with one bit -
BIXOR
Bit Invert eXclusive OR 1-bit inversion and exclusive logical sum -
BLD
Bit LoaD Loads one bit (to a carry) -
BILD
Bit Invert LoaD Inverts and loads one bit (to a carry) -

BST
Bit STore Stores one bit (from a carry) -
BIST
Bit Invert STore Inverts and stores one bit (from a carry) -

- Shift/Rotate instructions
Instruction Meaning Description Sample program
SHAL
SHift Arithmetic Left Arithmetic left shift -
SHAR
SHift Arithmetic Right Arithmetic right shift -
SHLL
SHift Logical Left Logical left shift -
SHLR
SHift Logical Right Logical right shift -
ROTL
ROTate Left Left rotation -
ROTR
ROTate Right Right rotation -
ROTXL
ROTate with eXtend carry Left Left rotation with a carry -
ROTXR
ROTate with eXtend carry Right Right rotation with a carry -

- Block transfer instructions
Instruction Meaning Description Sample program
EEPMOV
MOVe data to EEPROM Data block transfer -
* Serves as a data block transfer instruction since no EEPROM is provided
with the H8/300H series.

- System control instructions
Instruction Meaning Description Sample program
TRAPA
TRAP Always Generates a trap -
RTE
ReTurn from Exception Returns from an exception
handling routine
-
SLEEP
SLEEP Sets the CPU in sleep state -
LDC
LoaD to Control register Loads data to the CCR -

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STC
STore from Control register Stores data from the CCR -
ANDC
AND Control register Logical product with the CCR -
ORC
inclusive OR Control register Logical sum with the CCR -
XORC
eXclusive OR Control register Exclusive logical sum with the
CCR
-
NOP
No OPeration No operation -

5.2 Addressing Modes

As described in Chapter 4, most instructions consist of mnemonics and
operands (targets for calculation or operation). Addressing modes represent
how to specify targets for calculation or operation, in other words, how to write
operands. There are nine addressing modes in all, each of which is selected
according to whether the target is a general-purpose register or memory, and
other factors.
Some addressing modes are available only for specific instructions.



Table 5.1: Addressing Mode Types
Addressing mode Symbol Description
Sample
program
Register direct
Rn, En, ERn
RnL, RnH
Addressing for handling the contents of
a general-purpose register.

Immediate
#xx
Addressing for handling numeric
values directly.

Absolute address
@aa
Addressing for handling the contents of
the memory.
A memory address is directly written in

an instruction.

Register indirect
@ERn
Addressing for handling the contents of
the memory.
A memory address is represented by
the contents of a general-purpose
register.

Register indirect with
displacement
@(disp,ERn)
Addressing for handling the contents of
the memory.
A memory address is represented by
the contents of a general-purpose
register with displacement (distance)
added.

Post-increment
register indirect
@ERn+
Addressing for handling the contents of
the memory.
Although the contents of a general-
purpose register is used as a memory


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address, the contents are incremented
after instruction execution.
Predecrement
register indirect
@-ERn
Addressing for handling the contents of
the memory.
Although the contents of a general-
purpose register is used as a memory
address, the contents are decremented
before instruction execution.

Memory indirect
@@aa
Addressing for branching by storing the
destination address in the memory and
specifying it.
—
Program counter
relative
Symbol
Addressing for specifying a branch
destination address.

* n: General register number xx: Numeric value
aa: Address disp: Displacement

5.3 Assembler Control Instructions

The assembler control instructions are used to specify operation of the

assembler when it converts a source program into an object program.
Specifically, they instruct the assembler where a program starts and ends, how
to reserve data or areas, and how to define symbols (no machine code is
generated except for some data generation instructions).
More than 30 assembler control instructions are available for the H8/300H
series assembler. Among them, basic instructions are described in this section.

For the assembler control instructions used in the sample programs in
Chapter 6, check the specifications in the table below:

Table 5.2: Assembler Control Instruction List
Type
Control
instruction
Functions
1.Section/
location
.ALIGN
Aligns an address to an even-numbered address or a 256-byte
boundary.
Put a boundary alignment number (2n) in the operand.
Samples
.ALIGN 2 ------------- (1)
.DATA.W 1000
.ALIGN 256 ------------- (2)
.DATA.W 2000
(1) Aligns an address to an even-numbered one.
(2) Aligns an address to a 256-byte boundary.
.SECTION
Specifies start and resume of a section and declares the attribute.

You can specify the name, attribute and start address of a section in
the operand.
Section attribute