Top-Level System Design

CHAPTER
12
Top-Level
System Design
In the last few chapters, we have discussed VHDL language
features and the VHDL synthesis process. In the next few
chapters, we tie all of these ideas together by developing
a top-down design for a small CPU design, verify its func-
tionality, verify that it can be synthesized, and implement
the design in an FPGA device.
12
Chapter Twelve
290
Reg0
Reg1
Reg2
Reg3
•
•
Reg7
Regsel
ProgCnt
AddrReg
Addr(15:0)
Data(15:0)
ALU
Control
Ready
R/W
VMA
Shifter

Shiftsel
Alusel
OutReg
Progsel
Addrsel
Outsel
OpReg
OpRegsel
InstrReg
Instrsel
Clock
Reset
Comp
Compsel
CompoutCompout
Figure 12-1
CPU Block Diagram.
CPU Design
The example is a small, 16-bit microprocessor. A block diagram is shown
in Figure 12-1.
The processor contains a number of basic pieces. There is a register
array of eight 16-bit registers, an ALU (Arithmetic Logic Unit), a shifter,
a program counter, an instruction register, a comparator, an address reg-
ister, and a control unit. All of these units communicate through a com-
mon, 16-bit tristate data bus.
Top-Level System Operation
The top-level design consists of the processor block and a memory block
communicating through a bidirectional databus, an address bus, and a few
control lines. The processor fetches instructions from the external memory
and executes these instructions to run a program. These instructions are

291
Top-Level System Design
stored in the instruction register and decoded by the control unit. The
control unit causes the appropriate signal interactions to make the
processor unit execute the instruction.
If the instruction is an add of two registers, the control unit would
cause the first register value to be written to register OpReg for temporary
storage. The second register value would then be placed on the data bus.
The ALU would be placed in add mode and the result would be stored in
register OutReg. Register OutReg would store the resulting value until it
is copied to the final destination.
When executing an instruction, a number of steps take place. The pro-
gram counter holds the address in memory of the current instruction. After
an instruction has finished execution, the program counter is advanced to
where the next instruction is located. If the processor is executing a linear
stream of instructions, this is the next instruction. If a branch was taken,
the program counter is loaded with the next instruction location directly.
The control unit copies the program counter value to the address reg-
ister, which outputs the new address on the address bus. At the same
time, the control unit sets the R/W (read write signal) to a
‘0’
value for
a read operation and sets signal VMA (Valid Memory Address) to a
‘1’
,
signaling the memory that the address is now valid. The memory decodes
the address and places the memory data on the data bus. When the data
has been placed on the data bus, the memory has set the READY signal
to a
‘1’

value indicating that the memory data is ready for consumption.
The control unit causes the memory data to be written into the instruc-
tion register. The control unit now has access to the instruction and decodes
the instruction. The decoded instruction executes, and the process starts
over again.
Instructions
Instructions can be divided into a number of different types as follows:
■ Load
—
These instructions load register values from other registers,
memory locations, or with immediate values given in the instruction.
■ Store
—
These instructions store register values to memory locations.
■ Branch
—
These instructions cause the processor to go to another
location in the instruction stream. Some branch instructions test
values before branching; others branch without testing.
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292
■ ALU
—
These instructions perform arithmetic and logical opera-
tions such as ADD, SUBTRACT, OR, AND, and NOT.
■ Shift
—
These instructions use the shift unit to perform shift
operations on the data passed to it.
Sample Instruction Representation

Instructions share common attributes, but come in a number of flavors.
Sample instructions are shown in Figure 12-2.
All instructions contain the opcode in the five most significant bits of
the instruction. Single-word instructions also contain two 3-bit register
fields in the lowest 6 bits of the instruction. Some instructions, such as
INC (Increment), only use one of the fields, but other instructions, such
as MOV (Move), use both register fields to specify the From register and the
To register. In double-word instructions, the first word contains the opcode
and destination register address, and the second word contains the im-
mediate instruction location or data value to be loaded. For instance, a
LoadI (Load Immediate) instruction would look like this:
LoadI 1, 16#15
Opcode
SRC
DST
15
14
13
12
11
0
1
2
3
4
5
Single Word
Opcode
DST
15

14
13
12
11
0
1
2
15
14
13
12
11
0
1
2
3
4
5
Address or Data
Double Word
Figure 12-2
Instruction Words.
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Top-Level System Design
This instruction loads the hex value 15 into register 1. The instruction
words look like those shown in Figure 12-3.
When the control unit decodes the opcode of the first word, it deter-
mines that the instruction is two words long and loads the second word
to complete the instruction.
The instructions implemented in the processor and their opcodes are

listed in Figure 12-4.
Not all of the possible instructions have been implemented in this
processor example to limit the complexity for ease of publication. Typical
commercial processors are much more complicated and have pipelined
instruction streams for faster execution. To reduce complexity, this example
is not pipelined.
CPU Top-Level Design
The next few sections contain the VHDL description for each of the CPU
components. First of all, a top-level package
cpu_lib.vhd
is needed to de-
scribe the signal types that are used to communicate between the CPU
components. Following is this package:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package cpu_lib is
type t_shift is (shftpass, shl, shr, rotl, rotr);
subtype t_alu is unsigned(3 downto 0);
constant alupass : unsigned(3 downto 0) := “0000”;
Opcode
DST
0
0
1
0
0
1
0
0

0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
5
LoadI
1
Figure 12-3
Instruction Data.