Áp dụng các kỹ thuật điều chế độ rộng xung để cải tiến chất lượng điện cho bộ nghịch lưu ba bậc NPC

ĐẠI HỌC QUỐC GIA TP. HCM
TRƯỜNG ĐẠI HỌC BÁCH KHOA
--------------------

PHẠM ĐĂNG KHOA

ÁP DỤNG CÁC KỸ THUẬT ĐIỀU CHẾ ĐỘ RỘNG
XUNG ĐỂ CẢI TIẾN CHẤT LƯỢNG ĐIỆN NĂNG
CHO BỘ NGHỊCH LƯU BA BẬC NPC

Chuyên ngành : Kỹ Thuật Điện
Mã số: 60520202

LUẬN VĂN THẠC SĨ

TP. HỒ CHÍ MINH, năm 201


CƠNG TRÌNH ĐƯỢC HỒN THÀNH TẠI
TRƯỜNG ĐẠI HỌC BÁCH KHOA –ĐHQG -HCM
Cán bộ hướng dẫn khoa học : PGS.TS. Nguyễn Văn Nhờ
(Ghi rõ họ, tên, học hàm, học vị và chữ ký)

Cán bộ chấm nhận xét 1 :...........................................................................
(Ghi rõ họ, tên, học hàm, học vị và chữ ký)

Cán bộ chấm nhận xét 2 :...........................................................................
(Ghi rõ họ, tên, học hàm, học vị và chữ ký)

Luận văn thạc sĩ được bảo vệ tại Trường Đại học Bách Khoa, ĐHQG
Tp. HCM ngày . . . . . tháng . . . . năm .201

Thành phần Hội đồng đánh giá luận văn thạc sĩ gồm:
(Ghi rõ họ, tên, học hàm, học vị của Hội đồng chấm bảo vệ luận văn
thạc sĩ)

1.
2.
3.
4.
5.

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Xác nhận của Chủ tịch Hội đồng đánh giá LV và Trưởng Khoa quản lý
chuyên ngành sau khi luận văn đã được sửa chữa (nếu có).
CHỦ TỊCH HỘI ĐỒNG

TRƯỞNG KHOA ĐIỆN-ĐIỆN TỬ


ĐẠI HỌC QUỐC GIA TP.HCM
TRƯỜNG ĐẠI HỌC BÁCH KHOA

CỘNG HÒA XÃ HỘI CHỦ NGHĨA VIỆT NAM
Độc lập - Tự do - Hạnh phúc

NHIỆM VỤ LUẬN VĂN THẠC SĨ

Họ tên học viên : PHẠM ĐĂNG KHOA

MSHV:7140413

Ngày, tháng, năm sinh: 10/01/1990

Nơi sinh: TP HỒ CHÍ MINH

Chuyên ngành: Kỹ Thuật Điện

Mã số : 60520202

I. TÊN ĐỀ TÀI: ÁP DỤNG CÁC KỸ THUẬT ĐIỀU CHẾ ĐỘ RỘNG XUNG ĐỂ
CẢI TIẾN CHẤT LƯỢNG ĐIỆN NĂNG CHO BỘ NGHỊCH LƯU BA BẬC NPC
II. NHIỆM VỤ VÀ NỘI DUNG:
+ Khảo sát và chọn các kỹ thuật điều chế độ rộng xung cho nghịch lưu ba bậc NPC.
+ Đề ra phương pháp để đánh giá và so sánh các kỹ thuật điều chế độ rộng xung đã
chọn.
+ Xây dựng mơ hình mơ phỏng trên MATLAB cho tất cả các phương pháp đã chọn
để tiến hành lấy kết quả và so sánh kết quả của tất cả các phương pháp.
+ Xây dựng mơ hình thực của bộ NPC ba bậc. Các phương pháp đã chọn được lập
trình trên vi điều khiển TMS320F377D. Kết quả lấy từ thực nghiệm sẽ được so sánh
với nhau, đồng thời kiểm chứng kết quả mô phỏng.
+ Áp dụng kỹ thuật điều chế độ rộng xung của năm bậc NPC và bảy bậc cascade
nghịch lưu vào bộ nghịch lưu ba bậc NPC để triệt tiêu điện áp common mode, đồng
thời giảm độ méo dạng dòng và giảm tổn hao đóng cắt.
III. NGÀY GIAO NHIỆM VỤ : 10/07/2017
IV. NGÀY HOÀN THÀNH NHIỆM VỤ : 03/12/2017
V. CÁN BỘ HƯỚNG DẪN: PGS.TS. Nguyễn Văn Nhờ

Tp. HCM, ngày 03 tháng 12 năm 2017
CÁN BỘ HƯỚNG DẪN
(Họ tên và chữ ký)

CHỦ NHIỆM BỘ MÔN ĐÀO TẠO
(Họ tên và chữ ký)

TRƯỞNG KHOA ĐIỆN-ĐIỆN TỬ
(Họ tên và chữ ký)


ACKNOWLEDGEMENTS
Thank you to Prof. Nguyen Van Nho who have helped guide me through this exciting and
challenging journey, provide insightful feedback, and teach me how to conduct thorough
research. His wisdom and expertise in this field of study is exceptional, and it was both a
pleasure and an honor to have him as an advisor and a professor.
I would like to thank Mr. Nguyen Van Vui for his practical experience during the experiment
setup.
Finally, I sincerely thank my family for all of their support they have given to me over the years.

1


ABSTRACT
Multilevel Inverters especially the three-level Neutral Point Clamped Inverters are widely used in
motor drive applications. Compared to the conventional two-level inverters, the three-level
inverters offer better harmonic performance. However, Common-mode Voltage and Neutral
Point Voltage Imbalance are the two technical challenges that need to be addressed in order to
optimize the performance of motor drive systems. The Common-mode voltage causes bearing
failure and Electromagnetic Interference (EMI). These two problems reduce the life expectancy

of motors and have other equipment working in close proximity not to function properly.
Moreover, the Neutral Point Voltage Imbalance causes excessive stress on switching devices and
low-order harmonics at the output. Therefore, both common-mode voltage and neutral point
voltage imbalance must be mitigated by either hardware or software solutions. In this thesis, the
software solutions, specifically Pulse-Width Modulation (PWM) strategies are the main focus.
The thesis tackles the problem in the literature, which is the common-mode voltage and neutral
point voltage imbalance are solved separately. For example, a certain proposed PWM method
for CMV reduction does not mention neutral point voltage imbalance, and vice versa. Therefore,
the thesis aims to select some prominent PWM strategies in the literature and make a
comparison among them in terms of CMV mitigation, NP voltage balancing performance, and
harmonic distortion. The simulation of all the PWM methods are implemented from MATLAB
2016b while the experiment is conducted at PERLAB. The simulation results are compared against
one another. The experimental results are also compared against one another validate the
simulation results.

TÓM TẮT
Nghịch lưu đa bậc, đặc biệt là bộ nghịch lưu ba bậc NPC được sử dụng rộng rãi trong các ứng
dụng điều khiển động cơ. So với bộ nghịch lưu hai bậc thông thường, bộ nghịch lưu ba bậc cho
chất lượng đầu ra tốt hơn. Tuy nhiên, điện áp common mode và lệch điện áp trung tính là hai vấn
đề cần được giải quyết để tối ưu hóa các hệ thống điều khiển động cơ. Điện áp common mode
gây ra nhiều hư hỏng cho động cơ và nhiễu điện từ trường. Hai vấn đề này làm giảm tuổi thọ của
động cơ và các thiết bị xung quanh. Hơn nữa, lệch điện áp trung tính tụ gây ra hài bậc thấp ở
dịng và áp ngõ ra. Do đó, điện áp common mode và lệch điện áp trung tính tụ cần được giải
quyết bởi các phương pháp phần cứng hay phần mềm. Trong luận văn này, phương pháp phần
mềm đặc biệt là các phương pháp độ rộng xung là trọng tâm chính. Luận văn giải quyết vấn đề là
điện áp common mode và lệch điện áp tụ trung tính thường giải quyết riêng lẽ. Do đó, luận văn
sẽ chọn một số phương pháp điều chế độ rộng xung tiêu biểu và so sánh giữa các phương pháp
về mặc giảm common mode, khả năng cân bằng tụ, và độ méo dạng song hài ở ngõ ra. Kết quả
mô phỏng của phương pháp sẽ được thực hiện trên MATLAB và thực nghiệm sẽ được tiến hành
ở phịng thí nghiệm PERLAB. Kết quả mô phỏng sẽ được so sánh đối chiếu với nhau. Kết quả thực

nghiệm sẽ được so sánh đối chiếu với nhau và xác nhận kết quả mô phỏng.

2


DECLARATION
I certify that the work is that of the author alone. The work has not been submitted previously.
The content of the thesis is the result of work which has been carried out since the official
commencement date of the thesis.

Pham Dang Khoa

3


TABLE OF CONTENTS
Acknowledgements…………………………………………………………………………………………………………………….1
Abstract……………………………………………………………………………………………………………………………….……..2
Declaration…………………………………………………………………………………………………………………………….…...3
Table of Contents…………………………………………………………………………………………………….………………….4
List of Figures…………………………………………………………………………………………………………..………………….7
List of Tables……………………………………………………………………………………………………………………………..15
1. Introduction………………………………………………………………………………………………………………………....16
1.1 Background………………………………………………………………………………………………………………….17
1.2 Problem Definition………………………………………………………………………………………….……………18
1.3 Current Understanding of the Problem, Existing Solutions, and Barriers to these
Solutions…………………………………………………………………………………………………………………………….19
1.4 Expected Results and its Significance…………………………………………………………………………...20
2. Literature Review of Common-Mode Voltage Problem……………………………………………………….…21
2.1 Common-mode Voltage Definition……………………………………………………………………………....21

2.2 Causes of Common-Mode Voltage……………………………………………………………………………….21
2.3 Common-Mode Voltage’s Effects on motor drive systems…………………………………………...22
2.4 Solutions to Mitigate Common-Mode Voltage……………………………………………………………..26
2.4.1 Hardware Solutions to Mitigate Common-Mode Voltage…………………………………..26
2.4.2 Software Solutions to Mitigate Common-Mode Voltage………………………….………...33
3. Literature Review of Neutral Point Voltage Imbalance Problem……………………………….……….…38
3.1 Neutral Point Voltage Imbalance Definition……………………………………………………….………..38
3.2 Causes of Neutral Point Voltage Imbalance……………………………………………………….…………38
3.3 NP Voltage Imbalance’s Effects……………………………………………………………………….……………39
3.4 Solutions to Mitigate Neutral Point Voltage Imbalance…………………………………….………….39
4. Methodology…………………………………………………………………………………………………………..…………….47
5. Implementations of the Selected Pulse-Width Modulation (PWM) Methods in Three-Level
Neutral Point Clamped Inverters……………………………………………………………………………………..………..49
4


5.1 Conventional Sinusoidal Pulse-Width Modulation (SPWM)………………………………………….49
5.2 Sinusoidal Pulse-Width Modulation with the Proportional Controller (SPWM+P)…………50
5.3 Sinusoidal Pulse-Width Modulation by Song (SPWM+Song)…………………………………………52
5.4 Centered Space Vector Pulse Width Modulation with the Proportional Controller
(CSVPWM+P)……………………………………………………………………………………………………………………..55
5.5 Optimized Nearest Three Virtual Vectors (ONTVV)………………………………………………………58
5.6 Zero Common-Mode Voltage Pulse-Width Modulation with reduced switching loss
(ZCMV PWM with reduced switching loss)…………………………………………………………………………61
5.7 Zero Common-Mode Voltage Pulse-Width Modulation with reduced current ripple
(ZCMV PWM with reduced current ripple)…………………………………………………………………………65
6. Simulation and Experiment…………………………………………………………………………………………………..67
6.1 Simulation Setup…………………………………………………………………………………………………………67
6.1.1The SPWM with Proportional Controller (SPWM+P)……………………………………………68
6.1.2 The Centered Space Vector with Proportional Controller (CSVPWM+P)…………….69

6.1.3 The SPWM+Song……………………………………………………………………………………………….70
6.1.4 The Optimized Nearest Three Virtual Vector (ONTVV)……………………………………….71
6.1.5 The Zero Common Mode Voltage PWM with reduced switching loss (ZCMV PWM +
reduced switching loss)……………………………………………………………………………………………….72
6.1.6 The Zero Common Mode Voltage PWM with reduced current ripple (ZCMV PWM +
reduced current ripple)……………………………………………………………………………………………….73
6.2 Simulation Results……………………………………………………………………………………………………..74
6.2.1 The SPWM with Proportional Controller (SPWM+P)…………………………………………74
6.2.2 The Centered Space Vector with Proportional Controller (CSVPWM+P)…….……..80
6.2.4 The SPWM+Song………………………………………………………………………………………….……85
6.2.3 The Optimized Nearest Three Virtual Vector (ONTVV)……………………….……………..90
6.2.5 The Zero Common Mode Voltage PWM with reduced switching loss (ZCMV PWM
+ reduced switching loss)………………………………………………………………………….……………….95
6.2.6 The Zero Common Mode Voltage PWM with reduced current ripple (ZCMV PWM
+ reduced current ripple)………………………………………………………………………………………..100

5


6.3 Comparison and Evaluation of Simulation Results……………………………………………….……104
6.4 Experiment Setup…………………………………………………………………………….………….……………117
6.5 Experiment Results………………………………………………………………..……………………………...…124
6.5.1 The SPWM with Proportional Controller (SPWM+P)………………………………..….…..124
6.5.2 The Centered Space Vector with Proportional Controller (CSVPWM+P)…….…….129
6.5.3 The Optimized Nearest Three Virtual Vector (ONTVV)…………………………..…………135
6.5.4 The SPWM+Song……………………………………………………………………………….……..……..140
6.5.5 The Zero Common Mode Voltage PWM with reduced switching loss (ZCMV PWM
+ reduced switching loss)……………………………………………………………………...…………………146
6.5.6 The Zero Common Mode Voltage PWM with reduced current ripple (ZCMV PWM
+ reduced current ripple)……………………………………………………………….…………………..……151

6.6 Comparison and Evaluation of Experimental Results…………………….…………..…………..156
7. Conclusion and Future Works………………………………………………………………………………………..…162

6


LIST OF FIGURES
Figure 1: Topology of Three-Level NPC Inverter………………………………………………………………….……17
Figure 2: Space Vector diagram of the NPC converter………………………………………………………………19
Figure 3: A three-level NPC inverter with a diode front-end………………………………………………….…21
Figure 4: Electrical and physical models of parasitic capacitances in a motor…………………………..22
Figure 5: Electrical representation of parasitic capacitances in a motor…………………………………..22
Figure 6: The shaft voltage and common-mode voltage in a driven-PWM inverter………………….24
Figure 7: Bearing currents in a motor……………………………………………………………………………………….24
Figure 8: An isolation transformer for CMV mitigation…………………………………………………………….27
Figure 9: Differential mode (DM) noise……………………………………………………………………………………27
Figure 10: Common-mode (CM) noise……………………………………………………………………………………..28
Figure 11: Integrated DC choke in the CSI for CMV elimination………………………………………………..28
Figure 12: Integrated AC choke in VSI for CMV elimination………………………………………………………29
Figure 13: Integrated DC Choke……………………………………………………………………………………………….29
Figure 14: Circular-shaped integrated AC choke………………………………………………………………………30
Figure 15: A three-level NPC inverter with an addition of a fourth-leg…………………………………….31
Figure 16: Two 2-level Inverters connected to an Induction Motor with Open-End Windings….31
Figure 17: Two Cascaded H-bridge Inverter connected to an Induction Motor with Open-End
Windings………………………………………………………………………………………………………………………………….32
Figure 18: An auxiliary circuit for CMV elimination…………………………………………………………………..32
Figure 19: Phase leg during O -> P transition……………………………………………………………………………36
Figure 20: Impact of Dead time on CM voltage generation………………………………………………………36
Figure 21: The three-level NPC inverter with diode front-end………………………………………………….38
Figure 22: Effects of inverter operating modes on NP voltage and NP current…………………………39

Figure 23: Absolute NP Ripple Magnitude for 4200uF vs 840uF……………………………………………….40
Figure 24: Dynamic NP Performance for 4200uF vs 840uF……………………………………………………….40
Figure 25: Space Vector Diagram for Sector 1. VREF is within the subsector 2……………………………41
7


Figure 26: Approximate Medium and Small vector duty cycle variation versus modulation
depth……………………………………………………………………………………………………………………………………….43
Figure 27: Maximum NP disturbance and loss of NP control as load power factor angle
increases………………………………………………………………………………………………………………………………….43
Figure 28: Space Vector Diagram for Sector 1………………………………………………………………………….33
Figure 29: SV Diagram for Sector 1 in Medium-Vector-Elimination Strategies………………………….45
Figure 30: SVM for Nearest Three Virtual Vector (NTVV) for Sector 1………………………………………46
Figure 31: The Three Reference Sinusoidal Signals…………………………………………………………………..49
Figure 32: The two carrier signals in PD arrangement………………………………………………………………50
Figure 33: The three reference signals in SPWM+P………………………………………………………………….51
Figure 34: Offset added to the three reference signals in SPWM+P…………………………………………52
Figure 35: The reference signal of phase A in SPWM+Song……………………………………………………..54
Figure 36: The offset added to the three reference signals in SPWM+Song…………………………….54
Figure 37: The 3 reference signals in CSVPWM+P……………………………………………………………………56
Figure 38: The offset added to the 3 reference signals in CSVPWM+P…………………………………….57
Figure 39: Region A, B, C for the approximation of the optimum value of amplitude K. Image
obtained from [19]………………………………………………………………………………………………………………….59
Figure 40: The duty cycle dap and dan in ONTVV……………………………………………………..…………….61
Figure 41: Two PWM patterns resulting in zero common mode voltage….………………………….….63
Figure 42: Block diagram of current-based mapping PWM to optimize switching loss ……….….64
Figure 43: Flowchart of the ZCMV PWM with reduced switching loss………………………………..…..65
Figure 44: Algorithm of determining which phase is mapped to d sequence………………………….66
Figure 45: The mapping of s1 and s2 to other two phases when transitioning to a new zone...66
Figure 46: The three-level NPC inverter implemented in MATLAB Simulink………………………..…67

Figure 47: The control block of the SPWM+P in MATLAB Simulink………………………………..……..69
Figure 48: The control block of the Centered Space Vector PWM with Proportional
Controller(CSVPWM+P)…………………………………………………………………………………………………….….70
Figure 49: The control block of the SPWM+Song……………………………………………………..…………..71

8


Figure 50: The control block of the ONTVV……………………………………………………………………...………72
Figure 51: The control block of the ZCMV with reduced switching loss in MATLAB Simulink……73
Figure 52: The control block of the ZCMV with reduced current ripple…………………………………...74
Figure 53: The three-phase voltages Van, Vbn, Vcn……………………………………………………….……………75
Figure 54: The Frequency Spectrum of A-Phase Voltage Van……………………………………………………75
Figure 55: The Line-Line Voltage Vab………………………………………………………………………..……………..76
Figure 56: The Frequency Spectrum of Line-Line Voltage Vab…………………………………..……………..76
Figure 57: The three-phase currents ia, ib, ic…………………………………………………………………….……..77
Figure 58: The Frequency Spectrum of A-phase current ia……………………………………………….……..77
Figure 59: The DC-Link Voltages Vc1, Vc2…………………………………………………………………………………78
Figure 60: The Frequency Spectrum of Neutral Point Voltage Vn (Vc1-Vc2)……………………………..78
Figure 61: The Common-Mode Voltage Vno…………………………………………………………………………..79
Figure 62: The Frequency Spectrum of Common-Mode Voltage Vno………………………………….….80
Figure 63: The three-phase voltages Van, Vbn, Vcn………………………………………………………. ………..80
Figure 64: The Frequency Spectrum of A-Phase Voltage Van…………………………………………..…….80
Figure 65: The Line-Line Voltage Vab…………………………………………………………………………………..…81
Figure 66: The Frequency Spectrum of Vab……………………………………………………………….…………..81
Figure 67: The Three-Phase Currents ia, ib, ic…………………………………………………………………………82
Figure 68: The Frequency Spectrum of A-Phase Current ia………………………………………….………..82
Figure 69: The DC-link Capacitor Voltage Vc1, Vc2…………………………………………………….……………..83
Figure 70: The Frequency Spectrum of Neutral Point Voltage Vn (Vc1 – Vc2)…………………..……..83
Figure 71: The Common-Mode Voltage Vno…………………………………………………………………………..84

Figure 72: The Frequency Spectrum of Common-Mode Voltage Vno……………………………..………84
Figure 73: The Three-Phase Voltage Van, Vbn, Vcn……………………………………………………….………….85
Figure 74: The Frequency Spectrum of A-Phase Voltage Van…………………………………………………85
Figure 75: The Line-Line Voltage Vab………………………………………………………………………………..…..86
Figure 76: The Frequency Spectrum of Line-Line Voltage Vab………………………………….……………86
9


Figure 77: The Three-Phase Currents ia, ib, ic…………………………………………………………………………..87
Figure 78: The Frequency Spectrum of A-Phase Current ia………………………………….……….………….87
Figure 79: The DC-Link Capacitor Voltages Vc1, Vc2………………………………………………………..…………88
Figure 80: The Frequency Spectrum of Neutral Point Voltage Vn (Vc1 – Vc2)…………………..….…….88
Figure 81: The Common-Mode Voltage Vno………………………………………………………………….…….…..89
Figure 82: The Frequency Spectrum of Common-Mode Voltage Vno……………………………...….…..89
Figure 83: The Three-Phase Voltages Van, Vbn, Vcn……………………………………………….………….………90
Figure 84: The Frequency Spectrum of A-Phase Voltage Van…………………………….….…………………90
Figure 85: The Line-Line Voltage Vab…………………………………………………………………..………..…………91
Figure 86: The Frequency Spectrum of Line-Line Voltage Vab…………………………….………….………..91
Figure 87: The Three-Phase Current ia, ib, ic……………………………………………………………………………92
Figure 88: The Frequency Spectrum of A-Phase Current ia…………………………………………….………92
Figure 89: The DC-Link Capacitor Voltages Vc1, Vc2…………………………………………………………………93
Figure 90: The Frequency Spectrum of Neutral Point Voltage Vn (Vc1 – Vc2)…………….……………..93
Figure 91: The Common-Mode Voltage Vno………………………………………………………….…………..……94
Figure 92: The Frequency Spectrum of Common-Mode Voltage Vno…………….…..………………….94
Figure 93: The A-Phase Voltage Van……………………………………………………………….………………………95
Figure 94: The Frequency Spectrum of A-Phase Voltage Van…………….………….………………………..95
Figure 95: The Line-Line Voltage Vab……………………………………………………………….…………………….96
Figure 96: The Frequency Spectrum of Line-Line Voltage Vab……………………….……….………………96
Figure 97: The Three-Phase Currents ia, ib, ic………………………………….……………….……………….……97
Figure 98: The Frequency Spectrum of A-Phase Current ia……………….…………….……………..……..97

Figure 99: The DC-Link Capacitor Voltages Vc1, Vc2…………………………………………….….……………..98
Figure 100: The Frequency Spectrum of Neutral Point Voltage Vn…………………….…………………98
Figure 101: The Common-Mode Voltage Vno……………………………………………………….………..……99
Figure 102: The Frequency Spectrum of Common-Mode Voltage Vno………………………….……..99
Figure 103: The A-Phase Voltage Van……………………………………………………………………….……….100
10


Figure 104: The Frequency Spectrum of A-Phase Voltage Van…………………………………..………..100
Figure 105: The Line-Line Voltage Vab…………………………………………………………………..………..…..101
Figure 106: The Frequency Spectrum of Line-Line Voltage Vab………………..…………..……………..101
Figure 107: The Three-Phase Currents ia, ib, ic………………………………………………………..………..….102
Figure 108: The Frequency Spectrum of A-Phase Current ia…………………………………..……….……102
Figure 109: The DC-Link Capacitor Voltages Vc1, Vc2………………………………………………...………….103
Figure 110: The Frequency Spectrum of Neutral Point Voltage Vn (Vc1 – Vc2)…………..……………103
Figure 111: The Common-Mode Voltage Vno…………………………………………………………..……………104
Figure 112: The Frequency Spectrum of Common-Mode Voltage Vno…………………………..………105
Figure 113: THD of Phase Voltage Van of 7 PWM strategies for 25.250 load angle………..……….105
Figure 114: THD of Phase Voltage Van of 7 PWM strategies for 48.540 load angle………..…..…..105
Figure 115: THD of Phase Voltage Van of 7 PWM strategies for 620 load angle………………..….…106
Figure 116: THD of Phase Current ia of 7 PWM strategies for 25.250 load angle……….…..………107
Figure 117: THD of Phase Current ia of 7 PWM strategies for 48.540 load angle…………..…….…107
Figure 118: THD of Phase Current ia of 7 PWM strategies for 620 load angle……………..…………108
Figure 119: WTHD of output voltage Van of 7 PWM strategies for 25.250 load angle…..……….108
Figure 120: WTHD of output voltage Van of 7 PWM strategies for 48.540 load angle………...….109
Figure 121: WTHD of output voltage Van of 7 PWM strategies for 620 load angle………..……....109
Figure 122: Absolute maximum magnitude of NP voltage imbalance under balanced condition,
4700 𝜇𝐹, 25.250 load angle…………………………………………………………………………..………………..……110
Figure 123: Absolute maximum magnitude of NP voltage imbalance under balanced condition,
4700 𝜇𝐹, 48.540 load angle…………………………………………………………………………..………………………111

Figure 124: Absolute maximum magnitude of NP voltage imbalance under balanced condition,
4700 𝜇𝐹, 620 load angle…………………………………………………………………………………..…………………..111
Figure 125: Dynamic Performance under balanced load condition, 25.250 load angle, C = 4700
𝜇𝐹…………………………………………………………………………………………………………………..………….………..112
Figure 126: Dynamic Performance under balanced load condition, 48.540 load angle, C = 4700
𝜇𝐹…………………………………………………………………………………………………………………..…………………...112

11


Figure 127: Dynamic Performance under balanced load condition, 48.540 load angle, C = 4700
𝜇𝐹…………………………………………………………………………………………………………………………….…………113
Figure 128: The THD of line-line output voltage Vab under unbalanced load condition for C =
4700 𝜇𝐹……………………………………………………………………………………………………..…………….………..113
Figure 129: The THD of output phase current ia under unbalanced condition for C = 4700
𝜇𝐹……………………………………………………………………………………………………………………………………..114
Figure 130: The WTHD of output phase voltage Van under unbalanced condition for C = 4700
𝜇𝐹………………………………………………………………………………………………………………………….…………..115
Figure 131: Dynamic Performance under unbalanced condition for C = 4700 𝜇𝐹…………...….116
Figure 132: Absolute maximum magnitude NP voltage imbalance under unbalanced condition
for C = 4700 𝜇𝐹…………………………………………………………………………………………………………………..116
Figure 133: The block diagram of the power and control circuit………………………………..………117
Figure 134: The pole voltages VAO, VBO, VCO (top -> bottom)………………………………….…………..118
Figure 135: The pole voltage Vao, Vbo, Vco with the resistor load………………………………..………118
Figure 136: The two DC-Link Capacitor voltages Vc1 and Vc2 read by the ADC module……….119
Figure 137: The phase current ia read by the ADC module………………………………………………..119
Figure 138: The phase current ib read by the ADC module…………………………………………….….120
Figure 140: The IGBT gate driver…………………………………………………………………………..…………..121
Figure 139: The three-level NPC inverter………………………………………………………………….……….121
Figure 141: The TMSF28377D microcontroller…………………………………………………………..……..122

Figure 142: The voltage sensing circuit……………………………………………………………….…………….123
Figure 143: The current sensing circuit……………………………………………………….…………………….123
Figure 144: The auxiliary power supply………………………………………………………..…………………..123
Figure 145: The 2 DC-Link Capacitors…………………………………………………………………………….….124
Figure 146: The balanced three-phase R-L load (R = 33.3 Ω, L = 2.71 mH)………………….124
Figure 147: The three-phase voltages Van, Vbn, Vcn (100V/div, 5.00 ms/div)………………………124
Figure 148: The Frequency Spectrum of A-Phase Voltage Van………………………………..………….125
Figure 149: The line-line voltage Vab (100V/div, 5.00ms/div)…………………………………………….125
12


Figure 150: The Frequency Spectrum of Line-Line Voltage Vab………………………………………….126
Figure 151: The three-phase currents ia, ib, ic……………………………………………….……………………126
Figure 152: The Frequency Spectrum of Phase Current ia………………………………………………….127
Figure 153: The Common-Mode Voltage (100V/div,5.00ms/div)………………………………….…..128
Figure 154: The Frequency Spectrum of Common-Mode Voltage Vno……………………………….129
Figure 155: The DC-link capacitor voltages Vc1, Vc2 at the transient state (100V/div,
5.00ms/div)………………………………………………………………………………………………………………………129
Figure 156: The DC-link capacitor voltages Vc1, Vc2 at the steady state (100V/div, 5.00ms/div).
Figure 157: The Frequency Spectrum of NP voltage Vn (Vc1 – Vc2)…………………………………….130
Figure 158: The three-phase voltages Van, Vbn, Vcn (100V/div, 5.00ms/div)………………….…..130
Figure 159: The Frequency Spectrum of Phase Voltage Van…………………………….………….…….131
Figure 160: The Line-Line Voltage Vab (100V/div,
5.00ms/div)……………………………………………………………………………………………………….………….…131
Figure 161: The Frequency Spectrum of Line-Line Voltage Vab……..………………………………….132
Figure 162: The three-phase current ia, ib, ic……………………………………………………..……………..132
Figure 163: The Frequency Spectrum of Phase Current ia……………………………………….………..132
Figure 164: The Common-Mode Voltage Vno (100V/div, 5.00ms/div)………………..……………..133
Figure 165: The Frequency Spectrum of Common-Mode Voltage Vno……………………..………..134
Figure 166: The DC-link capacitor voltages Vc1, Vc2 at the transient state (100V/div,

5.00ms/div)…………………………………………………………………………………………………………….………..135
Figure 167: The DC-link capacitor voltages Vc1, Vc2 at the steady state (100V/div,
5.00ms/div)………………………………………………………………………………………………………………….……135
Figure 168: The Frequency Spectrum of NP voltage Vn (Vc1 – Vc2)…………………….………………..136
Figure 169: The three-phase voltages Van (top), Vbn (middle), Vcn (bottom) (100V/div,
5.00ms/div)…………………………………………………………………………………………….……………………..….136
Figure 170: The Frequency Spectrum of Phase Voltage Van………………..………………………………137
Figure 171: The Line-Line Voltage Vab (100V/div, 5.00ms/div)…………………………….……………..137
Figure 172: The Frequency Spectrum of Line-Line Voltage Vab………………….……………………….138
Figure 173: The three-phase current ia, ib, ic…………………………………………………………………..….138
13


Figure 174: The Frequency Spectrum of Phase Current ia………………………………………….…..……139
Figure 175: The Common-Mode Voltage Vno (100V/div, 5.00ms/div)……….……………….………..139
Figure 176: The Frequency Spectrum of Common-Mode Voltage Vno……………………….………..139
Figure 177: The DC-link capacitor voltages Vc1, Vc2 at the transient state (100V/div,
5.00ms/div)…………………………………………………………………………………………………………….……..…..139
Figure 178: The DC-link capacitor voltages Vc1, Vc2 at the steady state (100V/div,
5.00ms/div)…………………………………………………………………………………………………………………….…140
Figure 179: The Frequency Spectrum of NP voltage Vn (Vc1 – Vc2)………………………………..………140
Figure 180: The three-phase voltages Van, Vbn, Vcn (100V/div, 5.00ms/div)………………..………..141
Figure 181: The Frequency Spectrum of Phase Voltage Van………………………….……………..………142
Figure 182: The Line-Line Voltage Vab (100V/div, 5.00ms/div)…………………………………..………..143
Figure 183: The Frequency Spectrum of Line-Line Voltage Vab…………………..………………..……..143
Figure 184: The three-phase current ia, ib, ic………………………………………………………..….………….143
Figure 185: The Frequency Spectrum of Phase Current ia……………………………………..……………143
Figure 186: The Common-Mode Voltage Vno (50V/div, 5.00ms/div)…………………………..………144
Figure 187: The Frequency Spectrum of Common-Mode Voltage Vno………………..……………….144
Figure 188: The DC-link capacitor voltages Vc1, Vc2 at the transient state (100V/div,

5.00ms/div)…………………………………………………………………………………………………………………..……145
Figure 189: The DC-link capacitor voltages Vc1, Vc2 at the steady state (100V/div,
5.00ms/div)………………………………………………………………………………………………………………….……..145
Figure 190: The Frequency Spectrum of NP voltage Vn (Vc1 – Vc2)……………………………….……….146
Figure 191: The three-phase voltages Van (top), Vbn (middle), Vcn (bottom) (40V/div,
5.00ms/div)………………………………………………………………………………………………………………………….146
Figure 192: The Frequency Spectrum of Phase Voltage Van………………………………………………….147
Figure 193: The Line-Line Voltage Vab (40V/div, 5.00ms/div)……………………………………………….147
Figure 194: The Frequency Spectrum of Line-Line Voltage Vab…………………………………………....148
Figure 195: The three-phase current ia, ib, ic………………………………………………………………………..148
Figure 196: The Frequency Spectrum of Phase Current ia…………………………………………………….149
Figure 197: The Common-Mode Voltage Vno (20V/div, 5.00ms/div)……………………………………..149
14


Figure 198: The Frequency Spectrum of Common-Mode Voltage Vno……………………….…………..149
Figure 199: The DC-link capacitor voltages Vc1, Vc2 at the steady state (40V/div,
5.00ms/div)……………………………………………………………………………………………………………………………150
Figure 200: The Frequency Spectrum of NP voltage Vn (Vc1 – Vc2)…………………………………………..151
Figure 201: The three-phase voltages Van, Vbn, Vcn (100V/div, 5.00ms/div)…………………………….151
Figure 202: The Frequency Spectrum of Phase Voltage Van…………………………………………………….152
Figure 203: The Line-Line Voltage Vab (100V/div, 5.00ms/div)………………………………………………..152
Figure 204: The Frequency Spectrum of Line-Line Voltage Vab……………………………………………….153
Figure 205: The three-phase current ia, ib, ic…………………………………………………………………………..153
Figure 206: The Frequency Spectrum of Phase Current ia…………………………………………………….154
Figure 207: The Common-Mode Voltage Vno (100V/div, 5.00ms/div)…………………………………..154
Figure 208: The Frequency Spectrum of Common-Mode Voltage Vno…………………………………..155
Figure 209: The DC-link capacitor voltages Vc1, Vc2 at the steady state (100V/div,
5.00ms/div)…………………………………………………………………………………………………….…………………….155
Figure 210: The Frequency Spectrum of NP voltage Vn (Vc1 – Vc2)…………………….……………………156

Figure 211: The THD of Phase Voltage Van under balanced condition for C = 4700
𝜇𝐹…………………………………………………………………………………………………………………………………………157
Figure 212: THD of Line-Line Voltage Vab under balanced condition for C = 4700 𝜇𝐹………….…158
Figure 213: The WTHD of Line-Line Voltage Vab under balanced condition for C = 4700 𝜇𝐹.…158
Figure 214: The THD of the Phase Current ia under balanced load condition C = 4700 𝜇𝐹…….159
Figure 215: The dynamic NP voltage balancing performance under balanced load condition C =
4700 𝜇𝐹 at the transient state……………………………………………………………………………………………..159
Figure 216: The Magnitude of DC Component of NP voltage at the steady state under load
condition C = 4700 𝜇𝐹………………………………………………………………………………………………………….160
Figure 217: The Magnitude of the 3rd component of NP voltage at steady state under load
condition C = 4700 𝜇𝐹………………………………………………………………………………………………………….160

15


LIST OF TABLES
Table 1: Phase leg output voltages and associated switching command……………………………….…18
Table 2: Comparison of Design Data Between the Integrated Choke and Separate Reactors
(Chokes)…………………………………………………………………………………………………………………………………..30
Table 3: CMV magnitude corresponding to each voltage vector………………………………………………34
Table 4: The effects of switching states on NP current…………………………………………………………….41
Table 5: NTVV’s Virtual Vector Composition for Sector 1…………………………………………………………46
Table 6: Mapping function in Zero Common Mode Voltage PWM…………………………………………..64
Table 7: The three-level NPC inverter parameters…………………………………………………………………..67
Table 8: The operating condition of the three-level NPC inverter………………………………………….117

LIST OF SYMBOLS
NPC: Neutral Point Clamped
PWM: Pulse Width Modulation
m: modulation index

R: load resistor
L: load inductor
SPWM: Sinusoidal Pulse-Width Modulation
SPWM+P: Sinusoidal Pulse-Width Modulation
CSVPWM+P: Centered Space Vector Pulse-Width Modulation
SPWM+Song: Sinusoidal Pulse-Width Modulation by author Song
ONTVV: Optimized Nearest Three Virtual Vectors
ZCMV PWM + reduced switching loss: Zero Common-Mode Voltage Pulse-Width Modulation
with reduced switching loss
ZCMV PWM + reduced current ripple: Zero Common-Mode Voltage Pulse-Width Modulation
with reduced current ripple

16


Chapter 1: Introduction
1.1 Background
Multilevel inverters have gained a tremendous interest in motor drive applications, especially in
medium and high voltage range due to higher output voltage quality, higher voltage rating for
each phase leg, and more redundant states of voltage vectors than conventional 2-level
inverters. The output voltage quality is superior thanks to having more voltage levels, i.e. three,
five, seven levels…. Hence, the output voltage waveform in multilevel inverters more closely
resembles the pure sinusoidal waveform than that of the conventional 2-level inverters. Some
prominent topologies of multilevel inverters include three-level Neutral Point Clamped (NPC)
inverters, flying-capacitor inverters, H-bridge cascaded inverters. In this thesis, the three-level
NPC inverter is investigated thoroughly.

Figure 1: Topology of Three-Level NPC Inverter.
Since the introduction of the three-Level NPC Inverter in 1981 by Nabae et al [1], it has widely
used in industry, especially in medium-voltage applications. The voltage rating of each phase

leg is higher than that of conventional 2-level inverters since each leg contains 4 switching
power devices. Therefore, each switch only endures half of the input voltage (V DC/2) as
opposed to VDC in 2-level inverters. In terms of PWM control, there are 27 voltage vectors in 3level NPC inverters compared to 8 voltage vectors in 2-level inverters. Hence, this offers more
flexibility or more degrees of freedom in 3 NPC inverters to achieve certain performance (CMV
reduction/elimination, NP voltage balancing) than 2-level inverters.
The topology of the 3-level NPC inverter is shown in Fig 1. It includes 2 DC-link capacitors at the
input, 12 power switching devices for 3 phase legs, and 2 clamping diodes for each phase leg.
Two DC-link capacitors are connected through a neutral point (NP). Ideally speaking, the NP
17


voltage has to be half of the DC-link voltage. However, in practice, the NP voltage can deviate
from this level. The load could be a three-phase RL load or a motor with a floating neutral point.
For each phase leg, S1x and S3x are complementary as well as S2x and S4x {x = a, b, c}. The
switching states of these switches determining the output voltage of each leg V X {x = a, b, c} are
shown in Table 1:
S1X
0
1
0

S2X
S3X
S4X
VX
0
1
1
0
1

0
0
+VDC
1
1
0
+VNP
Table 1: Phase leg output voltages and associated switching commands

The three phase legs of the converter produce 33 = 27 switching states and 19 space vectors (SV)
as shown in the figure 2. The space vector diagram has six sectors. Each sector has four
subsectors.

Figure 2: Space Vector diagram of the NPC converter.
1.2 Problem Definition
Three-level NPC inverter has superior performance compared to a two-level inverter, but it still
subjects to some limitations, i.e. Neutral Point Voltage imbalance, Common-Mode voltage. The
NP voltage has to be kept at half of the DC-link voltage. Otherwise, it would put unnecessary
stress on switching devices. Moreover, the low-frequency ripple existing in the NP voltage
needs to be suppressed or reduced since it causes low-frequency harmonics in the line-line
output voltage. Common-mode voltage has been known for decades to be the cause of bearing
damage, breakdown of winding insulation, motor leakage current, and EMI in motor-drive
applications. Therefore, it must be reduced or eliminated so as to make the three-level NPC
inverter still attractive in motor-drive applications. Furthermore, switching loss is a major
18


concern in medium-high voltage motor drive applications since it dictates the efficiency of a
converter. In fact, switching loss reduction has been a research topic of the field. Numerous
papers [2][3][4][5] has focused on it by using Discontinuous PWM (DPWM) or not letting

switches commutate when a phase current magnitude is maximum. As far as the output quality
is concerned, current ripple reduction has been a major focus of the field since it leads to lower
torque pulsation in a motor.
In terms of the NP voltage balancing, the steady and transient state are investigated
thoroughly. In steady state, the maximum NP ripple magnitude is measured for a particular
PWM method. In transient state, the NP voltage performance, which is how long it takes for a
particular PWM method to reduce NP imbalance from an initial value to an acceptable level, is
measured.
In terms of CMV control, the magnitude of CMV, the step height of CMV, and the number of
CMV transitions in one carrier cycle will be observed for each PWM method. Since these factors
will determine how effective a particular PWM is in CMV reduction/elimination.
In terms of output quality, the total harmonic distortion and the weighted total harmonic
distortion of output voltage and current are calculated for each PWM method.
All of these performance criteria above are used to address the following research questions
relating to the NP voltage control, common-mode voltage, switching loss, and output quality of
the three-level NPC inverter, which includes:
1/ What performance criteria does a particular PWM compromise in order to achieve a NP
voltage balancing?
2/ What performance criteria does a particular PWM compromise in order to achieve CMV
reduction/elimination?
3/ What performance criteria does a particular PWM compromise in order to achieve superior
output quality?
4/ Is there any PWM method that can achieve all performance criteria at the same time?
In order to answer all the questions above, some prominent PWM methods in the literature are
selected and then quantitatively compared with one another.
1.3 Current Understanding of the Problem, Existing Solutions, and Barriers to these Solutions
The problem of PWM strategies presented in the literature is that they are not analyzed in a
comprehensive manner. For example, most papers which develop PWM methods for NP voltage
balancing only pay attention to NP voltage imbalance and neglect CMV reduction/elimination.
While PWM strategies developed for CMV control in other papers ignore the NP voltage

balancing. All papers show the output quality in terms of harmonic distortion of current and
voltage. However, the switching loss may or may not be included in the papers. Therefore, in
19


order to evaluate the effectiveness of any PWM strategy, it must be investigated in a
comprehensive manner.
Some papers in the literature do attempt to analyze the performance of PWM methods in terms
of NP voltage balancing and CMV control. However, they do not compare their performance with
that of the well-known PWM methods, such as convention Sinusoidal PWM (SPWM) or Space
Vector Modulation (SVPWM). Moreover, switching loss is not mentioned in these papers since it
is a crucial factor in medium-high voltage applications. Therefore, it fails to give a designer or
beginner a ‘big picture’ of the performance of PWM strategies.
The barriers to give a ‘big picture’ of the performance of PWM methods available in the literature
is the number of the strategies. There are a large number of PWM methods presented in the
literature. Most of them can be categorized into 3 main groups, i.e. carrier-based PWM (CPWM),
Space Vector PWM (SVPWM), and Selected Harmonics Elimination (SHE). In fact, a huge number
of PWM strategies are only the variants of these 3 main types. For example, in carrier-based
PWM, a new method can be developed by modifying the offset. If the offset is zero, then it
becomes a Sinusoidal PWM. In addition, the offset can be different from zero (either fixed or
variable) depending upon a specific control purpose, i.e. NP voltage balancing, CMV
reduction/elimination, and switching loss reduction. Therefore, the number of PWM strategies
will be limited in order for the thesis to be manageable.
1.4 Expected Results and Its Significance
The results of the thesis will pinpoint the strengths and weaknesses of some prominent PWM
strategies presented in the literature. They are going to help the designers choose which PWM
method is the suitable one for their own applications. Moreover, PWM strategies which will be
developed in the future should be assessed in a comprehensive manner by considering all the
performance criteria.

20


Chapter 2: Literature Review of Common Mode Voltage
Problem
2.1 Common Mode Voltage Definition in Three-Level Neutral Point Clamped Inverters

Figure 3: A three-level NPC inverter with a diode front-end.
Figure 3 shows a three-level NPC inverter with a diode front-end. The rectifier includes a threephase diode bridge which has the task of converting three-phase AC supply from the grid into
DC voltage. The two DC-link capacitor is to smooth out the DC voltage, which is converted into
three-phase AC voltages by a three-level NPC inverter to supply three-phase AC loads. These AC
voltages generated by an inverter are variable in terms of frequency and amplitude. Therefore,
it is suitable for motor drive applications. The total common-mode voltage is defined as:
VCM,total = VCM,rectifier + VCM,inverter
VCM,rectifier = VPG
VCM,inverter = VNP
Where: VCM,total = the total common-mode voltage generated by a rectifier and an inverter
VCM,rectifier = the common-mode voltage generated by a rectifier
VCM,inverter = the common-mode voltage generated by an inverter
In this thesis, however, it focuses on the common-mode voltage generated by an inverter
(VCM,inverter) and the instantaneous VCM,inverter is calculated as:
VCM,inverter =

𝑉𝐴𝑃 +𝑉𝐵𝑃 +𝑉𝐶𝑃
3

(1)

2.2 Causes of Common Mode Voltage in Three-Level Neutral Point Clamped Inverters
21

The switching modulation of an inverter produces a switched output voltage waveform, which,
according to the formula (1), results in non-zero instantaneous common-mode voltage.
2.3 Common Mode Voltage’s Effects on Motor Drive Systems
Shaft Voltage and Bearing Current
Shaft voltage and bearing current has been a well-known problem for motors since 1924 [6].
There are three sources of shaft voltage, namely electromagnetic induction, electrostatic
coupled from internal sources and external sources. The high level of common-mode voltage
dv/dt is the external source that causes shaft voltage and bearing current due to parasitic
capacitances present in motors. These types of parasitic capacitance are shown in the Fig 4.

Figure 4: Electrical and physical models of parasitic capacitances in a motor [7].

Figure 5: Electrical representation of parasitic capacitances in a motor [7].
Figure 5 shows the various parasitic capacitances in an AC motor that become relevant when
the motor is driven by a PWM voltage source inverter. The high level of CM dv/dt applied
across the stator and grounded frame of the motor causes pulsed currents to flow through the
parasitic capacitances. These parasitic capacitances include:
1/ Stator to frame capacitance or CSF: This is the primary capacitance that is formed between
the stator winding and the grounded frame. It is the largest single parasitic capacitance in the
motor. Most of the common mode current due to the high CM dv/dt flow through this path [7].

22